CN105551969B - A kind of current regulator diode structure and forming method thereof - Google Patents
A kind of current regulator diode structure and forming method thereof Download PDFInfo
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- CN105551969B CN105551969B CN201610082486.7A CN201610082486A CN105551969B CN 105551969 B CN105551969 B CN 105551969B CN 201610082486 A CN201610082486 A CN 201610082486A CN 105551969 B CN105551969 B CN 105551969B
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- 238000001459 lithography Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 4
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 20
- 229910052814 silicon oxide Inorganic materials 0.000 description 14
- 238000000137 annealing Methods 0.000 description 11
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- 239000007924 injection Substances 0.000 description 11
- 150000002500 ions Chemical class 0.000 description 9
- 238000002513 implantation Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000003321 amplification Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000003199 nucleic acid amplification method Methods 0.000 description 5
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- 238000004528 spin coating Methods 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
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- 239000004065 semiconductor Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000005465 channeling Effects 0.000 description 2
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
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- 229910052709 silver Inorganic materials 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
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- 238000005468 ion implantation Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
- H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
Abstract
The present invention provides a kind of current regulator diode structures and forming method thereof, p-type emitter region is added in N-type epitaxy layer, N-type source region, P-type grid electrode area, N-type epitaxy layer, N-type drain region form current regulator diode, P type substrate, N-type epitaxy layer and p-type emitter region form PNP triode, thus, unit area current greatly improves, and the temperature stability of device and uniformity are preferable.
Description
Technical field
The invention belongs to technical field of semiconductors more particularly to a kind of current regulator diode structure and forming method thereof.
Background technique
Current regulator diode is a kind of both ends constant current device of silicon materials manufacture.Current regulator diode accesses circuit loop by polarity
In, positive constant current conducting is reversed to end, and constant current is exported, using simple.Currently, current regulator diode is widely used in friendship
In the electronic circuits such as dc amplifier, D.C. regulated power supply, waveform generator and protection circuit.
Traditional current regulator diode generallys use planar channeling junction field effect transistor (Junction Field-
Effect Transistor, JFET) structure, JFET is two highly doped areas P of production on same N shape semiconductor, is drawn
Electrode out is known as grid G, and forms the highly doped area N, and the electrode drawn is known as drain D, source S, and current regulator diode is logical
It crosses and is shorted the grid G of JFET and source S to form constant-current characteristics.Specifically, as shown in Figure 1, current regulator diode includes: p-type lining
Bottom 10, N-type epitaxy layer 11, P-type grid electrode area 12a, N-type source region 12b, N-type drain region 12c, p-type isolation 12d and front electrode 13,
Wherein, P-type grid electrode area 12a, N-type source region 12b are connected by front electrode 13, and p-type isolation 12d penetrates N-type epitaxy layer 11 and p-type
Substrate 10 is connected.However, it is found by the inventors that there are the following problems for traditional current regulator diode:
One, the constant current size of traditional current regulator diode is to 110 thickness of N-type epitaxy layer, 110 resistance of N-type epitaxy layer
The junction depth in rate and P-type grid electrode area 121 is very sensitive, causes final constant current value uniformity very poor, yield rate is lower；
Two, the current capacity of planar channeling JFET structure depends primarily on channel width, and channel width is by front electrode
Figure limitation, the channel width of unit area is smaller, and then causes unit area current smaller, higher cost；
Three, conventional current regulator diode has very big negative temperature coefficient, and high-temperature constant fluidity can be bad.
Summary of the invention
It is an object of the invention to solve the problems, such as that the constant current value uniformity of existing current regulator diode is poor.
Another object of the present invention is to solve the problems, such as that the unit area current of existing current regulator diode is lesser.
Another object of the present invention is to solve the problems, such as that the high-temperature constant fluidity of existing current regulator diode can be bad.
In order to solve the above technical problems, the present invention provides a kind of current regulator diode structure, comprising:
P type substrate；
The N-type epitaxy layer being formed on the P type substrate front；
Be formed in P-type grid electrode area, N-type source region, N-type drain region, p-type emitter region and p-type in the N-type epitaxy layer every
From；And
The front electrode being formed in the P-type grid electrode area, N-type source region and p-type emitter region；
Wherein, the P type substrate, N-type epitaxy layer and p-type emitter region form PNP triode, the N-type source region, p-type grid
Polar region, N-type epitaxy layer, N-type drain region form current regulator diode.
Optionally, in the current regulator diode structure, the P-type grid electrode area, N-type source region, N-type drain region, p-type transmitting
The doping concentration of area and p-type isolation is greater than the doping concentration of the N-type epitaxy layer.
Optionally, in the current regulator diode structure, the P-type grid electrode area, p-type emitter region, p-type isolation and p-type
Substrate is p-type heavy doping, and the N-type source region and N-type drain region are N-type heavy doping.
Optionally, in the current regulator diode structure, the depth in the N-type source region and N-type drain region is less than the p-type
The depth of gate regions and p-type emitter region.
Optionally, in the current regulator diode structure, the p-type isolation penetrates the N-type epitaxy layer and the p-type
Substrate is connected.
It optionally, further include the back side electricity being formed on the P type substrate back side in the current regulator diode structure
Pole.
Optionally, in the current regulator diode structure, the p-type emitter region and P-type grid electrode area diffuse to form simultaneously.
Optionally, in the current regulator diode structure, the p-type emitter region is strip structure, and the N-type drain region is
Ring structure, and the N-type drain region surrounds the p-type emitter region.The current regulator diode structure include Liang Ge P-type grid electrode area and
Two N-type source regions, described two P-type grid electrode areas and described two N-type source regions are strip structure, and described two P-type grid electrodes
Area is located at the two sides in the N-type drain region, and described two N-type source regions are located at the two sides in described two P-type grid electrode areas.The p-type every
From for ring structure, and the N-type source region is surrounded in p-type isolation.
Optionally, in the current regulator diode structure, collector of the P type substrate as the PNP triode,
Base stage of the N-type epitaxy layer as the PNP triode, emitter of the p-type emitter region as the PNP triode.
Optionally, in the current regulator diode structure, the base current of the PNP triode passes through p-type emitter region
Afterwards, followed by N-type drain region, N-type epitaxy layer, P-type grid electrode area, N-type source region, finally it is isolated via p-type from the back side of P type substrate
Outflow；The collector current of the PNP triode flows through N-type epitaxy layer and flows from the back side of P type substrate after p-type emitter region
Out.
The present invention also provides a kind of forming methods of current regulator diode structure, comprising:
One P type substrate is provided；
N-type epitaxy layer is formed on the P type substrate front；
P-type grid electrode area, N-type source region, N-type drain region, p-type emitter region and p-type isolation are formed in the N-type epitaxy layer；
And
Front electrode is formed in the P-type grid electrode area, N-type source region and p-type emitter region；
Wherein, the P type substrate, N-type epitaxy layer and p-type emitter region form PNP triode, the N-type source region, p-type grid
Polar region, N-type epitaxy layer, N-type drain region form current regulator diode.
Optionally, in the forming method of the current regulator diode structure, p-type grid are formed in the N-type epitaxy layer
The step of polar region, N-type source region, N-type drain region, p-type emitter region and p-type are isolated include:
The p-type isolation is formed in the N-type epitaxy layer；
The P-type grid electrode area and p-type emitter region are formed in the N-type epitaxy layer；
The N-type source region and N-type drain region are formed in the N-type epitaxy layer.
Optionally, in the forming method of the current regulator diode structure, the p-type emitter region and P-type grid electrode area are same
When diffuse to form.
Optionally, in the forming method of the current regulator diode structure, the P-type grid electrode area, N-type source region, N-type leakage
The doping concentration in area, p-type emitter region and p-type isolation is greater than the doping concentration of the N-type epitaxy layer.
Optionally, in the forming method of the current regulator diode structure, the P-type grid electrode area, p-type emitter region, p-type
Isolation and P type substrate are p-type heavy doping, and the N-type source region and N-type drain region are N-type heavy doping.
Optionally, in the forming method of the current regulator diode structure, the depth of the N-type source region and N-type drain region
Less than the depth in the P-type grid electrode area and p-type emitter region.
Optionally, in the forming method of the current regulator diode structure, the p-type isolation penetrates the N-type extension
Layer is connected with the P type substrate.
Optionally, in the forming method of the current regulator diode structure, the P-type grid electrode area, N-type source region and
The step of formation front electrode, includes: in p-type emitter region
Insulating layer is formed in the N-type epitaxy layer；
Fairlead is formed in the insulating layer by lithography and etching technique；
Front metal layer is formed by sputtering technology；
By lithography and etching technique, graphically the front metal layer forms the front electrode.
Optionally, in the forming method of the current regulator diode structure, the P-type grid electrode area, N-type source region and
It is formed after front electrode in p-type emitter region, further includes: form rear electrode on the back side of the P type substrate.
Optionally, in the forming method of the current regulator diode structure, the p-type emitter region is strip structure, institute
Stating N-type drain region is ring structure, and the N-type drain region surrounds the p-type emitter region.The current regulator diode structure includes two
P-type grid electrode area and two N-type source regions, described two P-type grid electrode areas and described two N-type source regions are strip structure, and described
Liang Ge P-type grid electrode area is located at the two sides in the N-type drain region, and described two N-type source regions are located at the two of described two P-type grid electrode areas
Side.The p-type is isolated into ring structure, and the N-type source region is surrounded in p-type isolation.
Optionally, in the forming method of the current regulator diode structure, the P type substrate is as tri- pole PNP
The collector of pipe, base stage of the N-type epitaxy layer as the PNP triode, the p-type emitter region is as tri- pole PNP
The emitter of pipe.
Optionally, in the forming method of the current regulator diode structure, the base current of the PNP triode passes through
After p-type emitter region, followed by N-type drain region, N-type epitaxy layer, P-type grid electrode area, N-type source region, finally it is isolated via p-type from p-type
It flows out at the back side of substrate；The collector current of the PNP triode flows through N-type epitaxy layer and serves as a contrast from p-type after p-type emitter region
It flows out at the back side at bottom.
In current regulator diode structure provided by the invention, p-type emitter region, N-type source region, p-type are added in N-type epitaxy layer
Gate regions, N-type epitaxy layer, N-type drain region form current regulator diode, and P type substrate, N-type epitaxy layer and p-type emitter region form PNP tri-
Pole pipe, the constant current of current regulator diode exports after PNP triode Current amplifier as a result, and unit area current substantially mentions
It is high.In addition, PNP triode amplification factor β has positive temperature coefficient, and current regulator diode constant current is negative temperature coefficient, such as
This, the temperature stability of device is preferable.In addition, when the fluctuating change in the same direction of the junction depth of PNP triode and current regulator diode, PNP tri-
The constant current Id inverse variation direction of pole pipe amplification factor β and current regulator diode, it is more stable that entire device always exports electric current,
Uniformity is preferable.
Detailed description of the invention
Fig. 1 is the schematic diagram of the section structure of traditional current regulator diode structure；
Fig. 2 is the schematic diagram of the section structure of the current regulator diode structure of one embodiment of the invention；
Fig. 3 is the schematic equivalent circuit of the current regulator diode structure of one embodiment of the invention；
Fig. 4 a~4e is the schematic diagram of the section structure in the current regulator diode structure-forming process of one embodiment of the invention；
Fig. 5 is the overlooking structure diagram of the current regulator diode structure of one embodiment of the invention；
Fig. 6 is the overlooking structure diagram of the current regulator diode structure of another embodiment of the present invention.
Specific embodiment
Current regulator diode structure proposed by the present invention is described in further detail below in conjunction with the drawings and specific embodiments.
According to following explanation and claims, advantages and features of the invention will be become apparent from.It should be noted that attached drawing is all made of very
Simplified form and non-accurate ratio is used, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
As shown in Fig. 2, the application provides a kind of current regulator diode structure, comprising: P type substrate 100；It is formed in the p-type
N-type epitaxy layer 110 on 100 front of substrate；It is formed in P-type grid electrode area 121 in the N-type epitaxy layer 110, N-type source region
122, N-type drain region 123, p-type emitter region 124 and p-type isolation 125；Be formed in the P-type grid electrode area 121, N-type source region 122 with
And the front electrode 130 in p-type emitter region 124.
Wherein, the P-type grid electrode area 121, N-type source region 122, N-type drain region 123, p-type emitter region 124 and p-type isolation
125 doping concentration is greater than the doping concentration of the N-type epitaxy layer 110, and the P-type grid electrode area 121, N-type source region 122 pass through institute
It states front electrode 130 to be connected, the p-type isolation 125 penetrates the N-type epitaxy layer 110 and is connected with the P type substrate 100.
The equivalent circuit structure of the current regulator diode structure as shown in figure 3, as shown in connection with fig. 2, the P type substrate 100,
N-type epitaxy layer 110 and p-type emitter region 124 form PNP triode, wherein collection of the P type substrate 100 as longitudinal P NP triode
Electrode, base stage of the N-type epitaxy layer 110 as PNP triode, emitter of the p-type emitter region 124 as PNP triode.The N
Type source region 122, P-type grid electrode area 121, N-type epitaxy layer 110, N-type drain region 123 form current regulator diode.The base stage of PNP triode
Electric current is after p-type emitter region 124, followed by N-type drain region 123, N-type epitaxy layer 110, P-type grid electrode area 121, N-type source region
122, it is finally flowed out via p-type isolation 125 from the back side of P type substrate 100, the base current size of PNP triode is by constant current two
The constant current Id of pole pipe is determined；The collector current of PNP triode flows through N-type epitaxy layer 110 after p-type emitter region 124
It is flowed out from the back side of P type substrate 100, which is equal to β times of base current, the i.e. constant electricity of current regulator diode
β times for flowing Id.
The present invention thus forms PNP triode, the constant current Id of current regulator diode by adding p-type emitter region 124
It is exported after β times of PNP triode Current amplifier, the total current I of entire device architecture final output is equal to current regulator diode
(the 1+ β) of constant current Id times, unit area current greatly improves, and cost is relatively low.In addition, PNP triode amplification factor β has
Positive temperature coefficient, and current regulator diode constant current Id is negative temperature coefficient, in this way, the temperature of device architecture of the invention is stablized
Property is relatively good.In addition, when the fluctuating change in the same direction of the junction depth of PNP triode and current regulator diode, PNP triode amplification factor β with
The constant current Id inverse variation direction of current regulator diode, the entire more stable (width of N-type epitaxy layer 110 of device total current I
It is smaller, resistivity is higher, the electric current of current regulator diode is smaller, and PNP triode amplification factor β is then bigger, can so offset
A part fluctuation), uniformity is preferable.The especially P-type grid electrode area of the p-type emitter region 124 of PNP triode and JFET structure
121 use same process, diffuse to form simultaneously, are more advantageous to the stability for improving the total current I of entire device final output.
In preferred embodiment, the P-type grid electrode area 121, p-type emitter region 124, p-type isolation 125 are p-type heavy doping (P+),
The N-type source region 122, N-type drain region 123 are N-type heavy doping (N+), and the P type substrate is also p-type heavy doping (P+).
Further, the current regulator diode structure further includes the rear electrode 150 being formed on 100 back side of P type substrate,
The rear electrode 150 is, for example, to be formed by materials such as gold, silver, aluminium.
Fig. 5 is the overlooking structure diagram of the current regulator diode structure of one embodiment of the invention.For clearer PNP tri-
The structure of pole pipe and current regulator diode does not represent front electrode 130 in Fig. 5.In the present embodiment, as shown in figure 5, p-type is sent out
Penetrating area 124 is strip structure, and N-type drain region 123 is ring structure, and N-type drain region 123 surrounds p-type emitter region 124；P-type grid electrode area
121 and N-type source region 122 be strip structure, and Liang Ge P-type grid electrode area 121 is respectively in the two sides in N-type drain region 123, two N-types
Source region 122 is respectively in the two sides in Liang Ge P-type grid electrode area 121；P-type isolation 125 is ring structure, and it surrounds described two N-types
Source region 122.It should be understood that the above arrangement mode is illustrated not to limit current regulator diode structure of the invention, example
Such as, as shown in fig. 6, in an alternative embodiment of the invention, the p-type emitter region 124 is also possible to I-shaped structure, to increase
The emitter region perimeter of PNP triode improves PNP triode current capacity, correspondingly, the N-type drain region 123 is the annular of indent
Structure, to guarantee the spacing in N-type drain region 123 Yu p-type emitter region 124.Meanwhile the quantity of the p-type emitter region 124 can be one
It is a be also possible to it is multiple, if chip includes that multiple p-type emitter region can accordingly increase current capacity.In short, the present invention is simultaneously
The number and shape of p-type emitter region 124 are not limited.
The forming process of current regulator diode structure of the invention is discussed in detail below with reference to Fig. 4 a to Fig. 4 e.
As shown in fig. 4 a, firstly, providing a P type substrate 100.The material of the P type substrate 100 can be silicon, germanium or
One of germanium silicon compound, organic compound semiconductor material.The P type substrate 100 can select 5 inches, 6 inches, 8 English
Very little and larger size silicon wafer.The resistivity of the P type substrate 100 is preferably less than 0.02 Ω cm.
As shown in Figure 4 b, then, N-type epitaxy layer 110 is formed on 100 front of P type substrate.Epitaxial growth can be passed through
Technique forms N-type epitaxy layer 110 in the P type substrate 100.The thickness of the N-type epitaxy layer 110 is, for example, 2 μm~6 μm.
As illustrated in fig. 4 c, then, p-type isolation 125 is formed in the N-type epitaxy layer 110, the p-type isolation 125 penetrates
The N-type epitaxy layer 110 is connected with the P type substrate 100.
As a unrestricted example, the specific steps for forming the p-type isolation 125 include: firstly, outside N-type
Prolong and forms silicon oxide layer on layer 110, the spin coating photoresist layer on silicon oxide layer；Development is exposed to the photoresist layer, in light
P-type isolation pattern of windows is formed on photoresist layer；Again using photoresist layer as exposure mask, p-type isolation pattern of windows is transferred to silica
On layer, it is exposed to N-type epitaxy layer 110 under p-type isolation window；Then P is carried out to 110 part of the N-type epitaxy layer of the exposure
Type ion implanting, Implantation Energy are, for example, 50~70Kev, preferably 60Kev, and implantation dosage is, for example, 1E14~1E16 ㎝-2, note
The P-type ion entered is, for example, boron ion；After the completion of injection, photoresist layer and silicon oxide layer are removed；Finally, in nitrogen (N2) atmosphere
Lower carry out annealing process, annealing temperature are, for example, 1150 DEG C~1250 DEG C, and annealing time is, for example, 30~240 minutes, form institute
State p-type isolation 125.The film-forming process and thermal anneal process of above-mentioned photoresist layer, silicon oxide layer are all that industry generallys use
Technique, just do not repeat them here herein.
As shown in figure 4d, then, P-type grid electrode area 121 and p-type emitter region while in the N-type epitaxy layer 110 are formed
124.The depth of the P-type grid electrode area 121 and p-type emitter region 124 is less than the thickness of N-type epitaxy layer 110.
As a unrestricted example, the specific steps packet of the p-type isolation 125 and P-type grid electrode area 121 is formed
It includes: firstly, silicon oxide layer is formed in N-type epitaxy layer 110, the spin coating photoresist layer on silicon oxide layer；To the photoresist layer into
Row exposure development forms p-type emitter window pattern on photoresist layer；Again using photoresist layer as exposure mask, by p-type emitter region window
Mouth pattern is transferred on silicon oxide layer, is exposed to N-type epitaxy layer 110 under the p-type emitter window；Then to the N of the exposure
110 part of type epitaxial layer carries out P-type ion injection, and Implantation Energy is, for example, 50~70Kev, preferably 60Kev, implantation dosage example
1E14~5E15 ㎝ in this way-2, the P-type ion of injection is, for example, boron ion；After the completion of injection, photoresist layer and silica are removed
Layer；Then, silicon oxide layer, and the spin coating photoresist layer on silicon oxide layer are formed in N-type epitaxy layer 110 again；Then to this
Photoresist layer is exposed development, and P-type grid electrode area pattern of windows is formed on photoresist layer；Again using photoresist layer as exposure mask, by P
Type gate regions pattern of windows is transferred on silicon oxide layer, is exposed to N-type epitaxy layer 110 under the P-type grid electrode area window；It is sudden and violent to this
110 part of N-type epitaxy layer of dew carries out P-type ion injection, and Implantation Energy is, for example, 50~70Kev, preferably 60Kev, injection
Dosage is, for example, 1E13~5E14 ㎝-2, the P-type ion of injection is, for example, boron ion；After the completion of injection, photoresist layer and oxygen are removed
SiClx layer；Finally, in nitrogen (N2) annealing process is carried out under atmosphere, annealing temperature is, for example, 1000 DEG C~1100 DEG C, when annealing
Between be, for example, 30~180 minutes, be formed simultaneously the P-type grid electrode area 121 and p-type emitter region 124.It is understood that above-mentioned P
Type isolation 125 and P-type grid electrode area 121 can using identical ion implantation technology condition and annealing to be formed simultaneously, but also
Using different ion implanting conditions, annealing is formed respectively.It should be understood that the p-type emitter region 124 of PNP triode and JFET are tied
The P-type grid electrode area 121 of structure uses same process, diffuses to form simultaneously, is more advantageous to and improves the total defeated of entire device final output
The stability of electric current out.
As shown in fig 4e, N-type source region 122, N-type drain region 123, the N-type source region are formed in the N-type epitaxy layer 110
122, the depth in N-type drain region 123 is less than the depth in P-type grid electrode area 121, p-type emitter region 124.
As a unrestricted example, the N-type source region 122 is formed, the specific steps in N-type drain region 123 include: head
First, silicon oxide layer is formed in N-type epitaxy layer 110, the spin coating photoresist layer on silicon oxide layer；The photoresist layer is exposed
Development forms N-type source region, N-type drain region pattern of windows on photoresist layer；Again using photoresist layer as exposure mask, by N-type source region, N-type
Drain region pattern of windows is transferred on silicon oxide layer, is exposed to N-type epitaxy layer 110 under the N-type source region, N-type drain region window；Then
N-type ion injection is carried out to 110 part of N-type epitaxy layer of the exposure, Implantation Energy is, for example, 140~160Kev, preferably
150Kev, implantation dosage are, for example, 5E14~2E16 ㎝-2, the N-type ion of injection is, for example, phosphonium ion；After the completion of injection, removal
Photoresist layer and silicon oxide layer；Finally, in nitrogen (N2) carrying out annealing process under atmosphere, annealing temperature is, for example, 850 DEG C~
1050 DEG C, annealing time is, for example, 30~60 minutes, is formed simultaneously the N-type source region 122, N-type drain region 123.
Then, refering to what is shown in Fig. 2, forming insulating layer 140 in the N-type epitaxy layer 110, and pass through lithography and etching work
Skill forms fairlead in the insulating layer 140, then forms front metal layer by sputtering technology, then pass through lithography and etching
Graphically the front metal layer forms front electrode 130 to technique, the P-type grid electrode area 121, N-type source region 122 by it is described just
Face electrode 130 is connected, finally, forming rear electrode 150 on the back side of P type substrate 100.The material example of the insulating layer 140
The material of silica in this way, the front electrode 130 and rear electrode 150 is, for example, gold, silver, aluminium etc., is not limited herein
System.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (26)
1. a kind of current regulator diode structure characterized by comprising
P type substrate；
The N-type epitaxy layer being formed on the P type substrate front；
P-type grid electrode area, N-type source region, N-type drain region, p-type emitter region and the p-type isolation being formed in the N-type epitaxy layer；With
And
The front electrode being formed in the P-type grid electrode area, N-type source region and p-type emitter region；
Wherein, the P type substrate, N-type epitaxy layer and p-type emitter region form PNP triode, the N-type source region, P-type grid electrode area,
N-type epitaxy layer, N-type drain region form current regulator diode.
2. current regulator diode structure as described in claim 1, which is characterized in that the P-type grid electrode area, N-type source region, N-type leakage
The doping concentration in area, p-type emitter region and p-type isolation is greater than the doping concentration of the N-type epitaxy layer.
3. current regulator diode structure as claimed in claim 2, which is characterized in that the P-type grid electrode area, p-type emitter region, p-type
Isolation and P type substrate are p-type heavy doping, and the N-type source region and N-type drain region are N-type heavy doping.
4. current regulator diode structure as described in claim 1, which is characterized in that the N-type source region and the depth in N-type drain region are small
Depth in the P-type grid electrode area and p-type emitter region.
5. current regulator diode structure as described in claim 1, which is characterized in that the p-type isolation penetrates the N-type epitaxy layer
It is connected with the P type substrate.
6. current regulator diode structure as described in claim 1, which is characterized in that further include being formed in the P type substrate back side
On rear electrode.
7. current regulator diode structure as described in claim 1, which is characterized in that the p-type emitter region and P-type grid electrode area are simultaneously
It diffuses to form.
8. the current regulator diode structure as described in any one of claims 1 to 7, which is characterized in that the p-type emitter region is item
Shape structure, the N-type drain region is ring structure, and the N-type drain region surrounds the p-type emitter region.
9. the current regulator diode structure as described in any one of claims 1 to 7, which is characterized in that the current regulator diode knot
Structure includes Liang Ge P-type grid electrode area and two N-type source regions, and described two P-type grid electrode areas and described two N-type source regions are bar shaped knot
Structure, and described two P-type grid electrode areas are located at the two sides in the N-type drain region, described two N-type source regions are located at described two p-type grid
The two sides of polar region.
10. the current regulator diode structure as described in any one of claims 1 to 7, which is characterized in that the p-type is isolated into ring
Shape structure, and the N-type source region is surrounded in p-type isolation.
11. the current regulator diode structure as described in any one of claims 1 to 7, which is characterized in that the P type substrate conduct
The collector of the PNP triode, base stage of the N-type epitaxy layer as the PNP triode, the p-type emitter region conduct
The emitter of the PNP triode.
12. current regulator diode structure as claimed in claim 11, which is characterized in that the base current of the PNP triode passes through
After crossing p-type emitter region, followed by N-type drain region, N-type epitaxy layer, P-type grid electrode area, N-type source region, finally it is isolated via p-type from P
It flows out at the back side of type substrate；The collector current of the PNP triode flows through N-type epitaxy layer from p-type after p-type emitter region
It flows out at the back side of substrate.
13. a kind of forming method of current regulator diode structure characterized by comprising
One P type substrate is provided；
N-type epitaxy layer is formed on the P type substrate front；
P-type grid electrode area, N-type source region, N-type drain region, p-type emitter region and p-type isolation are formed in the N-type epitaxy layer；And
Front electrode is formed in the P-type grid electrode area, N-type source region and p-type emitter region；
Wherein, the P type substrate, N-type epitaxy layer and p-type emitter region form PNP triode, the N-type source region, P-type grid electrode area,
N-type epitaxy layer, N-type drain region form current regulator diode.
14. the forming method of current regulator diode structure as claimed in claim 13, which is characterized in that in the N-type epitaxy layer
The step of middle formation P-type grid electrode area, N-type source region, N-type drain region, p-type emitter region and p-type are isolated include:
The p-type isolation is formed in the N-type epitaxy layer；
The P-type grid electrode area and p-type emitter region are formed in the N-type epitaxy layer；
The N-type source region and N-type drain region are formed in the N-type epitaxy layer.
15. the forming method of current regulator diode structure as claimed in claim 14, which is characterized in that the p-type emitter region and P
Type gate regions diffuse to form simultaneously.
16. the forming method of current regulator diode structure as claimed in claim 13, which is characterized in that the P-type grid electrode area, N
Type source region, N-type drain region, p-type emitter region and the doping concentration of p-type isolation are greater than the doping concentration of the N-type epitaxy layer.
17. the forming method of current regulator diode structure as claimed in claim 16, which is characterized in that the P-type grid electrode area, P
Type emitter region, p-type isolation and P type substrate are p-type heavy doping, and the N-type source region and N-type drain region are N-type heavy doping.
18. the forming method of current regulator diode structure as claimed in claim 13, which is characterized in that the N-type source region and N-type
The depth in drain region is less than the depth in the P-type grid electrode area and p-type emitter region.
19. the forming method of current regulator diode structure as claimed in claim 13, which is characterized in that the p-type isolation penetrates
The N-type epitaxy layer is connected with the P type substrate.
20. the forming method of current regulator diode structure as claimed in claim 13, which is characterized in that the P-type grid electrode area,
The step of formation front electrode, includes: in N-type source region and p-type emitter region
Insulating layer is formed in the N-type epitaxy layer；
Fairlead is formed in the insulating layer by lithography and etching technique；
Front metal layer is formed by sputtering technology；
By lithography and etching technique, graphically the front metal layer forms the front electrode.
21. the forming method of current regulator diode structure as claimed in claim 13, which is characterized in that the P-type grid electrode area,
It is formed after front electrode in N-type source region and p-type emitter region, further includes:
Rear electrode is formed on the back side of the P type substrate.
22. the forming method of the current regulator diode structure as described in any one of claim 13 to 21, which is characterized in that described
P-type emitter region is strip structure, and the N-type drain region is ring structure, and the N-type drain region surrounds the p-type emitter region.
23. the forming method of the current regulator diode structure as described in any one of claim 13 to 21, which is characterized in that described
Current regulator diode structure includes Liang Ge P-type grid electrode area and two N-type source regions, described two P-type grid electrode areas and described two N-type sources
Area is strip structure, and described two P-type grid electrode areas are located at the two sides in the N-type drain region, and described two N-type source regions are located at institute
The two sides in Shu Liangge P-type grid electrode area.
24. the forming method of the current regulator diode structure as described in any one of claim 13 to 21, which is characterized in that described
P-type is isolated into ring structure, and the N-type source region is surrounded in p-type isolation.
25. the forming method of the current regulator diode structure as described in any one of claim 13 to 21, which is characterized in that described
Collector of the P type substrate as the PNP triode, base stage of the N-type epitaxy layer as the PNP triode, the p-type
Emitter of the emitter region as the PNP triode.
26. the forming method of current regulator diode structure as claimed in claim 25, which is characterized in that the PNP triode
Base current is after p-type emitter region, followed by N-type drain region, N-type epitaxy layer, P-type grid electrode area, N-type source region, finally via P
Type isolation is flowed out from the back side of P type substrate；The collector current of the PNP triode flows through outside N-type after p-type emitter region
Prolong layer to flow out from the back side of P type substrate.
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| JP2003224139A (en) * | 2002-01-30 | 2003-08-08 | Sony Corp | Semiconductor device and its manufacturing method |
| US6696706B1 (en) * | 2002-10-22 | 2004-02-24 | Lovoltech, Inc. | Structure and method for a junction field effect transistor with reduced gate capacitance |
| CN1716562A (en) * | 2004-06-14 | 2006-01-04 | 海力士半导体有限公司 | Method for manufacturing cell transistor |
| CN205542795U (en) * | 2016-02-05 | 2016-08-31 | 杭州士兰集成电路有限公司 | Current regulator diode structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003224139A (en) * | 2002-01-30 | 2003-08-08 | Sony Corp | Semiconductor device and its manufacturing method |
| US6696706B1 (en) * | 2002-10-22 | 2004-02-24 | Lovoltech, Inc. | Structure and method for a junction field effect transistor with reduced gate capacitance |
| CN1716562A (en) * | 2004-06-14 | 2006-01-04 | 海力士半导体有限公司 | Method for manufacturing cell transistor |
| CN205542795U (en) * | 2016-02-05 | 2016-08-31 | 杭州士兰集成电路有限公司 | Current regulator diode structure |
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