CN103646965A - Junction field effect transistor (JFET) device and manufacturing method thereof - Google Patents
Junction field effect transistor (JFET) device and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 230000005669 field effect Effects 0.000 title abstract 2
- 238000001259 photo etching Methods 0.000 claims description 65
- 238000002347 injection Methods 0.000 claims description 28
- 239000007924 injection Substances 0.000 claims description 28
- 239000003292 glue Substances 0.000 claims description 22
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 21
- 238000009826 distribution Methods 0.000 claims description 21
- 229910052760 oxygen Inorganic materials 0.000 claims description 21
- 239000001301 oxygen Substances 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000004806 packaging method and process Methods 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 238000005245 sintering Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000012360 testing method Methods 0.000 claims description 4
- 238000003466 welding Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000013459 approach Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
- H01L29/7832—Field effect transistors with field effect produced by an insulated gate with multiple gate structure the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
Abstract
The invention relates to a semiconductor technology, in particular to a junction field effect transistor (JFET) device and a manufacturing method thereof. The JFET device is characterized in that junction depths of a P+ gate region 1 are uneven and are gradually increased from one end close to an N+ drain region 2 to one end close to an N+ source region 3. The JFET device has the advantages that the constant-current characteristics are good, and the requirements of smaller constant-current precision can be met. The manufacturing method is particularly suitable for the JFET device and manufacturing of the JFET device.
Description
Technical field
The present invention relates to semiconductor technology, relate to specifically a kind of JFET device and manufacture method thereof.
Background technology
Along with being widely used of LED lamp, LED constant current drives and also dominates the market rapidly, constant current JFET device is the constant-flow driver that aims at low-power LED design, it can realize constant current output in the wide-voltage range of 4V～150V, and can realize ± 15% constant current accuracy, can arrange in pairs or groups with LED lamp pearl, be widely used in room lighting.Fig. 1 is a kind of scheme of constant-current driving LED, and because output voltage is higher, this scheme is particularly suitable for the LED application that current value is 5mA～500mA, is especially applicable to high-voltage LED.This scheme comprises 6 components and parts altogether, simple and practical, and low-cost.In Fig. 1, after the full-wave rectifying circuit that electric main consists of D1-D4 and C1, directly drive constant current device and LED lamp string.Fig. 2 is another scheme of constant-current driving LED, and the resistance R adj newly adding can suitably regulate electric current according to different LED.Its driving circuit structure is simple, and cost is extremely low, and the core of constant current is provided, is exactly a n raceway groove JFET device of often opening, but current JFET device constant current accuracy is poor, is not well positioned to meet the application of constant-current source circuit.
Summary of the invention
To be solved by this invention, be exactly the precision problem existing for above-mentioned JFET device, a kind of JFET device and manufacture method thereof are proposed.
The present invention solves the problems of the technologies described above adopted technical scheme: a kind of JFET device, its structure cell comprises P type substrate 6 and is arranged on the P type epitaxial loayer 5 of P type substrate 6 upper surfaces, in described P type epitaxial loayer 5, be provided with N-shaped bulk channel district 4, the two ends of P type epitaxial loayer 5 are provided with P type isolated area 7, described P type epitaxial loayer 5, the upper surface of N-shaped bulk channel district 4 and P type isolated area 7 is provided with dielectric layer 9, in described N-shaped bulk channel district 4, be provided with separate P+ gate regions 1, N+ drain region 2 and N+ source area 3, wherein P+ gate regions 1 is between N+ drain region 2 and N+ source area 3, the upper surface of described P+ gate regions 1 is provided with gate metal 11, the upper surface of described N+ drain region 2 is provided with drain metal 10, the upper surface of described N+ source area 3 is provided with source metal 13, it is characterized in that, the junction depth of described P+ gate regions 1 is inhomogeneous, junction depth from the one end near N+ drain region 2 to the P+ gate regions, one end 1 near N+ source area 3 increases gradually.
The technical scheme that the present invention is total, proposes inhomogeneous gate regions 1 structure, utilize the variation of grid region junction depth to weaken channel modulation effect, thereby in wide range input voltage, the rate of change of output current is little.
Concrete, the junction depth of described P+ gate regions 1 is rendered as 3 times from the one end near N+ drain region 2 to the one end near N+ source area 3 and increases progressively.
A manufacture method for JFET device, is characterized in that, comprises the following steps:
The first step: select the less NTD<111> single-chip of defect, thick approximately 400～700 μ m of sheet, resistivity 0.001～0.005 Ω cm, mark is cleaned, dries stand-by;
Second step: silicon chip surface growing P-type epitaxial loayer 5, temperature is at 1100 ℃～1150 ℃, and thickness is 5～25 μ m, and resistivity is 8～12 Ω cm;
The 3rd step: thermal growth oxide layer, thickness exists
The 4th step: a photoetching, after photoetching, at the two ends of P type epitaxial loayer 5, carry out P type isolated area 7 and inject, be specially and adopt the injection of removing photoresist, the thick oxide layer of 40～100nm of growing before injecting, ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 40～80KeV, then distribution occasion is: oxygen free condition, 1100～1150 ℃ of temperature, time 100min～120min;
The 5th step: secondary photoetching, after photoetching, carry out N-shaped bulk channel district 4, be specially and adopt the injection of removing photoresist, the thick oxide layer of 40～100nm of growing before injecting, ion implanting conditions is: dosage 1e12～5e12cm
-2, energy 40～80KeV, then distribution occasion is: oxygen free condition, 1100～1150 ℃ of temperature, time 230min～250min;
The 6th step: field oxide growth, thickness exists
The 7th step: third photo etching, active area etching, injects and etches active area for the drain-gate district, source in follow-up active area;
The 8th step: four mask, after photoetching, carrying out P+ gate regions 1 injects, form the inhomogeneous P+ gate regions 1 of junction depth, and the junction depth from the one end near N+ drain region 2 to the P+ gate regions, one end 1 near N+ source area 3 increases gradually, be specially adopt repeatedly photoetching, repeatedly different Implantation Energies mode or adopt repeatedly photoetching, repeatedly identical energy injects and the mode of knot repeatedly;
The 9th step: five photoetching, after photoetching, carry out N+ drain region 2 and 3 injections of N+ source area; The concrete band glue that adopts injects, the thick oxide layer of 40～100nm of growing before injecting, and ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 60～80KeV, then distribution occasion is: oxygen free condition, 1100～1150 ℃ of temperature, time 230min～250min;
The tenth step: six photoetching, etch contact hole;
The 11 step: metal deposit, at the upper surface of P+ gate regions 1 deposit gate metal 11, in the upper surface of N+ drain region 2 deposit drain metal 10, in 13, seven photoetching of the upper surface of N+ source area 3 deposit source metal, anti-carve aluminium;
The 12 step: alloy, 550 ℃ of furnace temperature, time 10min～30min, passivation;
The 13 step: eight times chemical wet etching goes out pressure welding point;
The 14 step: process annealing, 500 ℃～510 ℃ of temperature, constant temperature 30min;
The 15 step: silicon chip preliminary survey, cut, shelve, sintering, packaging and testing.
Concrete, in described the 8th step, P+ gate regions 1 injection mode, for adopting the mode of third photo etching and three different Implantation Energies, is specially:
After four mask, carry out the injection for the first time of P+ gate regions 1; Be specially and adopt band glue to inject, ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 20～40KeV;
Again carry out carrying out after photoetching the injection for the second time of P+ gate regions 1; Be specially and adopt band glue to inject, ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 60～200KeV;
Again carry out carrying out after photoetching the injection for the third time of P+ gate regions 1; Be specially and adopt band glue to inject, ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 200～1000KeV.
Concrete, in described the 8th step, P+ gate regions 1 injection mode, for adopting the mode of third photo etching, three identical energy injections and three knots, is specially:
After four mask, carrying out P+ gate regions 1 injects and pushes away trap for the first time; Be specially and adopt band glue to inject, ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 30～60KeV, push away trap again distribution occasion be: oxygen free condition, 950～1000 ℃ of temperature, time 25min～30min;
The injection for the second time of again carrying out P+ gate regions 1 after photoetching pushes away trap; Be specially and adopt band glue to inject, ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 30～60KeV, push away trap again distribution occasion be: oxygen free condition, 950～1000 ℃ of temperature, time 25min～30min;
Again after photoetching, carrying out P+ gate regions 1 injects and pushes away trap for the third time; Be specially and adopt band glue to inject, ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 30～60KeV, push away trap again distribution occasion be: oxygen free condition, 950～1000 ℃ of temperature, time 25min～30min.
Beneficial effect of the present invention is, on manufacture craft uncomplicated basis, constant-current characteristics is better, in wide range input voltage, the rate of change of output current is very little, than conventional JFET device, improved approximately 100%, can meet the demand of less constant current accuracy, be particularly suitable for low-power LED lamp constant current and drive.
Accompanying drawing explanation
Fig. 1 is that LED drives and application circuit schematic diagram;
Fig. 2 is that another kind of LED drives and application circuit schematic diagram;
Fig. 3 is device architecture schematic diagram of the present invention;
Fig. 4 is the constant-current characteristics contrast schematic diagram of JFET of the present invention and general structure JFET;
Fig. 5 is material P+ substrat structure schematic diagram in constant current device manufacturing approach craft step of the present invention;
Fig. 6 is extension P-structural representation in constant current device manufacturing approach craft step of the present invention;
Fig. 7 is isolated area P+ injecting structure schematic diagram in constant current device manufacturing approach craft step of the present invention;
Fig. 8 is N trap Channeling implantation structural representation in constant current device manufacturing approach craft step of the present invention;
Fig. 9 is the grid region third photo etching-tri-time different Implantation Energy that in constant current device manufacturing approach craft step of the present invention, grid region fabrication scheme one adopts, and P+ is injecting structure schematic diagram for the first time;
Figure 10 is the grid region third photo etching-tri-time different Implantation Energy that in constant current device manufacturing approach craft step of the present invention, grid region fabrication scheme one adopts, and P+ is injecting structure schematic diagram for the second time;
Figure 11 is the grid region third photo etching-tri-time different Implantation Energy that in constant current device manufacturing approach craft step of the present invention, grid region fabrication scheme one adopts, and P+ is injecting structure schematic diagram for the third time;
Figure 12 is that the grid region third photo etching-tri-time identical energy that in constant current device manufacturing approach craft step of the present invention, grid region fabrication scheme two adopts injects-tri-knots, and P+ injects knot structural representation for the first time;
Figure 13 is that the grid region third photo etching-tri-time identical energy that in constant current device manufacturing approach craft step of the present invention, grid region fabrication scheme two adopts injects-tri-knots, and P+ injects knot structural representation for the second time;
Figure 14 is that the grid region third photo etching-tri-time identical energy that in constant current device manufacturing approach craft step of the present invention, grid region fabrication scheme two adopts injects-tri-knots, and P+ injects knot structural representation for the third time;
Figure 15 is that in constant current device manufacturing approach craft step of the present invention, N+ injecting structure schematic diagram is leaked in source;
Figure 16 is structural representation after etching AL in constant current device manufacturing approach craft step of the present invention.
Embodiment
Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail:
As shown in Figure 3, a kind of JFET device of the present invention, its structure cell comprises P type substrate 6 and is arranged on the P type epitaxial loayer 5 of P type substrate 6 upper surfaces, in described P type epitaxial loayer 5, be provided with N-shaped bulk channel district 4, the two ends of P type epitaxial loayer 5 are respectively arranged with P type isolated area 7, described P type epitaxial loayer 5, the upper surface of N-shaped bulk channel district 4 and P type isolated area 7 is provided with dielectric layer 9, in described N-shaped bulk channel district 4, be provided with separate P+ gate regions 1, N+ drain region 2 and N+ source area 3, wherein P+ gate regions 1 is between N+ drain region 2 and N+ source area 3, the upper surface of described P+ gate regions 1 is provided with gate metal 11, the upper surface of described N+ drain region 2 is provided with drain metal 10, the upper surface of described N+ source area 3 is provided with source metal 13, the junction depth of described P+ gate regions 1 is inhomogeneous, junction depth from the one end near N+ drain region 2 to the P+ gate regions, one end 1 near N+ source area 3 increases gradually, the junction depth of described P+ gate regions 1 is rendered as 3 times from the one end near N+ drain region 2 to the one end near N+ source area 3 and increases progressively.
Operation principle of the present invention is: this JFET device belongs to often opens device, adds forward voltage between drain-source, and when raceway groove occurs after pinch off, along with the increase of drain-source voltage, electric current trends towards constant.The present invention adopts the repeatedly photoetching of P+ gate regions 1, repeatedly injects or adopt inject-knot repeatedly of repeatedly photoetching-repeatedly, formed the drain region shown in Fig. 3 to source region, the junction depth in grid region is the JFET increasing gradually, its advantage is to make constant-current characteristics to become better, and reason is to add positive voltage at drain terminal, when raceway groove occurs after pinch off, effect due to slope grid, can make slower close to source of pinch-off point, so it is little to can be described as channel-length modulation, what also just make that constant-current characteristics becomes is better.Thereby the variation that utilizes junction depth weakens channel modulation effect, in wide range input voltage, the rate of change of output current is little, as shown in Figure 4, for traditional jfet device and gatejfet device of the present invention constant-current characteristics contrast schematic diagram under the same conditions, traditional jfet device that represents that lines end is square, circle and equilateral triangle, lines end is del, the sleeping leg-of-mutton gatejfet device of triangle and right side of lying on the left side, by contrast, can draw, the conventional JFET device of ratio of the present invention has improved approximately 100%.
---epitaxial growth---------------------contact hole etching---metal deposit, etching---the processing step preparations such as alloy---passivation---annealing that source is leaked and injected that grid injects for the third time that grid injects for the second time that grid injects for the first time that N trap channel region is injected that P+ type isolated area is injected that device of the present invention is mainly prepared by silicon chip.
Embodiment 1:
This example adopts grid region third photo etching-tri-time different Implantation Energy to form, and is specially:
The first step: select the less NTD<111> single-chip of defect, the thick scope of sheet of single-chip is 400～700 μ m, and electrical resistivity range is 0.001～0.005 Ω cm, mark is cleaned, dries stand-by, as shown in Figure 5;
Second step: silicon chip surface grown epitaxial layer, temperature range is 1100 ℃～1150 ℃, and thickness is 5～25 μ m, and resistivity is 8～12 Ω cm, as shown in Figure 6;
The 3rd step: thermal growth oxide layer, thickness exists
The 4th step: a photoetching, after photoetching, carry out the injection of P+ isolated area, as shown in Figure 7; Body adopts the injection of removing photoresist, the thick oxide layer of 40～100nm of growing before injecting, and ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 40～80KeV, then distribution occasion is: oxygen free condition, 1100～1150 ℃ of temperature, time 100min～120min;
The 5th step: secondary photoetching, after photoetching, carry out N trap channel region and inject, as shown in Figure 8.Specifically adopt the injection of removing photoresist, the thick oxide layer of 40～100nm of growing before injecting, ion implanting conditions is: dosage 1e12～5e12cm
-2, energy 40～80KeV, then distribution occasion is: oxygen free condition, 1100～1150 ℃ of temperature, time 230min～250min;
The 6th step: field oxide growth, thickness exists
The 7th step: third photo etching, active area etching, injects and etches active area for the drain-gate district, source in follow-up active area;
The 8th step: four mask, carries out P+ gate regions and injects for the first time, as shown in Figure 9 after photoetching.The concrete band glue that adopts injects, and ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 20～40KeV;
The 9th step: five photoetching, after photoetching, carry out P+ gate regions and inject for the second time, as shown in figure 10.The concrete band glue that adopts injects, and ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 60～200KeV;
The tenth step: six photoetching, after photoetching, carry out P+ gate regions and inject for the third time, as shown in figure 11.The concrete band glue that adopts injects, and ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 200～1000KeV;
The 11 step: seven photoetching, after photoetching, carry out the injection of N+ source-drain area, as shown in figure 15.The concrete band glue that adopts injects, the thick oxide layer of 40～100nm of growing before injecting, and ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 60～80KeV, then distribution occasion is: oxygen free condition, 1100～1150 ℃ of temperature, time 230min～250min.
The 11 step: eight photoetching, etch contact hole;
The 12 step: metal deposit, nine photoetching, anti-carve aluminium, as shown in figure 16;
The 13 step: alloy, 550 ℃ of furnace temperature, time 10min～30min, passivation;
The 14 step: nine times chemical wet etching goes out pressure welding point;
The 15 step: process annealing, 500 ℃～510 ℃ of temperature, constant temperature 30min;
The 16 step: silicon chip preliminary survey, cut, shelve, sintering, packaging and testing.
Embodiment 2:
This example adopts grid region third photo etching-tri-time identical energy to inject the mode of-tri-knots, is specially:
The first step: select the less NTD<111> single-chip of defect, the thick scope of sheet is 400～700 μ m, and electrical resistivity range is 0.001～0.005 Ω cm, mark is cleaned, dries stand-by, as shown in Figure 5;
Second step: silicon chip surface grown epitaxial layer, temperature is at 1100 ℃～1150 ℃, and thickness is 5～25 μ m, and resistivity is 8～12 Ω cm, as shown in Figure 6;
The 3rd step: thermal growth oxide layer, thickness exists
The 4th step: a photoetching, after photoetching, carry out the injection of P+ isolated area, as shown in Figure 7; Body adopts the injection of removing photoresist, the thick oxide layer of 40～100nm of growing before injecting, and ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 40～80KeV, then distribution occasion is: oxygen free condition, 1100～1150 ℃ of temperature, time 100min～120min;
The 5th step: secondary photoetching, after photoetching, carry out N trap channel region and inject, as shown in Figure 8.Specifically adopt the injection of removing photoresist, the thick oxide layer of 40～100nm of growing before injecting, ion implanting conditions is: dosage 1e12～5e12cm
-2, energy 40～80KeV, then distribution occasion is: oxygen free condition, 1100～1150 ℃ of temperature, time 230min～250min;
The 6th step: field oxide growth, thickness exists
The 7th step: third photo etching, active area etching, injects and etches active area for the drain-gate district, source in follow-up active area;
The 8th step: four mask, carries out P+ gate regions and injects for the first time and push away trap, as shown in figure 12 after photoetching.The concrete band glue that adopts injects, and ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 30～60KeV, push away trap again distribution occasion be: oxygen free condition, 950～1000 ℃ of temperature, time 25min～30min;
The 9th step: five photoetching, after photoetching, carry out P+ gate regions and inject for the second time and push away trap, as shown in figure 13.The concrete band glue that adopts injects, and ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 30～60KeV, push away trap again distribution occasion be: oxygen free condition, 950～1000 ℃ of temperature, time 25min～30min;
The tenth step: six photoetching, after photoetching, carry out P+ gate regions and inject for the third time and push away trap, as shown in figure 14.The concrete band glue that adopts injects, and ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 30～60KeV, push away trap again distribution occasion be: oxygen free condition, 950～1000 ℃ of temperature, time 25min～30min;
The 11 step: seven photoetching, after photoetching, carry out the injection of N+ source-drain area, as shown in figure 15.The concrete band glue that adopts injects, the thick oxide layer of 40～100nm of growing before injecting, and ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 60～80KeV, then distribution occasion is: oxygen free condition, 1100～1150 ℃ of temperature, time 230min～250min.
The 11 step: eight photoetching, etch contact hole;
The 12 step: metal deposit, nine photoetching, anti-carve aluminium, as shown in figure 16;
The 13 step: alloy, 550 ℃ of furnace temperature, time 10min～30min, passivation;
The 14 step: nine times chemical wet etching goes out pressure welding point;
The 15 step: process annealing, 500 ℃～510 ℃ of temperature, constant temperature 30min;
The 16 step: silicon chip preliminary survey, cut, shelve, sintering, packaging and testing.
Claims (5)
1. a JFET device, its structure cell comprises P type substrate (6) and is arranged on the P type epitaxial loayer (5) of P type substrate (6) upper surface, in described P type epitaxial loayer (5), be provided with N-shaped bulk channel district (4), the two ends of P type epitaxial loayer (5) are provided with P type isolated area (7), described P type epitaxial loayer (5), the upper surface of N-shaped bulk channel district (4) and P type isolated area (7) is provided with dielectric layer (9), in described N-shaped bulk channel district (4), be provided with separate P+ gate regions (1), N+ drain region (2) and N+ source area (3), wherein P+ gate regions (1) is positioned between N+ drain region (2) and N+ source area (3), the upper surface of described P+ gate regions (1) is provided with gate metal (11), the upper surface of described N+ drain region (2) is provided with drain metal (10), the upper surface of described N+ source area (3) is provided with source metal (13), it is characterized in that, the junction depth of described P+ gate regions (1) is inhomogeneous, junction depth from the one end near N+ drain region (2) to the P+ gate regions, one end (1) near N+ source area (3) increases gradually.
2. a kind of JFET device according to claim 1, is characterized in that, the junction depth of described P+ gate regions (1) is rendered as 3 times from the one end near N+ drain region (2) to the one end near N+ source area (3) and increases progressively.
3. a manufacture method for JFET device, is characterized in that, comprises the following steps:
The first step: select NTD<111> single-chip;
Second step: silicon chip surface growing P-type epitaxial loayer (5);
The 3rd step: thermal growth oxide layer;
The 4th step: a photoetching, after photoetching, at the two ends of P type epitaxial loayer (5), carry out P type isolated area and inject, be specially and adopt the injection of removing photoresist, the thick oxide layer of 40～100nm of growing before injecting, ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 40～80KeV, then distribution occasion is: oxygen free condition, 1100～1150 ℃ of temperature, time 100min～120min;
The 5th step: secondary photoetching, after photoetching, carry out N-shaped bulk channel district (4), be specially and adopt the injection of removing photoresist, the thick oxide layer of 40～100nm of growing before injecting, ion implanting conditions is: dosage 1e12～5e12cm
-2, energy 40～80KeV, then distribution occasion is: oxygen free condition, 1100～1150 ℃ of temperature, time 230min～250min;
The 6th step: field oxide growth, thickness range is
The 7th step: third photo etching, active area etching, injects and etches active area for the drain-gate district, source in follow-up active area;
The 8th step: four mask, after photoetching, carrying out P+ gate regions (1) injects, form the inhomogeneous P+ gate regions (1) of junction depth, and near one end of N+ drain region (2), the junction depth to the P+ gate regions, one end (1) near N+ source area (3) increases gradually, be specially adopt repeatedly photoetching, repeatedly different Implantation Energies mode or adopt repeatedly photoetching, repeatedly identical energy injection and the mode of knot repeatedly;
The 9th step: five photoetching, after photoetching, carry out N+ drain region (2) and N+ source area (3) and inject; The concrete band glue that adopts injects, the thick oxide layer of 40～100nm of growing before injecting, and ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 60～80KeV, then distribution occasion is: oxygen free condition, 1100～1150 ℃ of temperature, time 230min～250min;
The tenth step: six photoetching, etch contact hole;
The 11 step: metal deposit, upper surface deposit gate metal (11) in P+ gate regions (1), upper surface deposit drain metal (10) in N+ drain region (2), the upper surface deposit source metal (13) in N+ source area (3), seven photoetching, anti-carves aluminium;
The 12 step: alloy, condition is 550 ℃ of furnace temperature, time 10min～30min, passivation;
The 13 step: eight times chemical wet etching goes out pressure welding point;
The 14 step: process annealing, 500 ℃～510 ℃ of temperature, constant temperature 30min;
The 15 step: silicon chip preliminary survey, cut, shelve, sintering, packaging and testing.
4. the manufacture method of a kind of JFET device according to claim 3, is characterized in that, in described the 8th step, P+ gate regions (1) injection mode, for adopting the mode of third photo etching and three different Implantation Energies, is specially:
After four mask, carry out the injection for the first time of P+ gate regions (1); Be specially and adopt band glue to inject, ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 20～40KeV;
Again carry out carrying out after photoetching the injection for the second time of P+ gate regions (1); Be specially and adopt band glue to inject, ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 60～200KeV;
Again carry out carrying out after photoetching the injection for the third time of P+ gate regions (1); Be specially and adopt band glue to inject, ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 200～1000KeV.
5. the manufacture method of a kind of JFET device according to claim 3, is characterized in that, in described the 8th step, P+ gate regions (1) injection mode, for adopting the mode of third photo etching, three identical energy injections and three knots, is specially:
After four mask, carrying out P+ gate regions (1) injects and pushes away trap for the first time; Be specially and adopt band glue to inject, ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 30～60KeV, push away trap again distribution occasion be: oxygen free condition, 950～1000 ℃ of temperature, time 25min～30min;
The injection for the second time of again carrying out P+ gate regions (1) after photoetching pushes away trap; Be specially and adopt band glue to inject, ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 30～60KeV, push away trap again distribution occasion be: oxygen free condition, 950～1000 ℃ of temperature, time 25min～30min;
Again after photoetching, carrying out P+ gate regions (1) injects and pushes away trap for the third time; Be specially and adopt band glue to inject, ion implanting conditions is: dosage 1e15～8e15cm
-2, energy 30～60KeV, push away trap again distribution occasion be: oxygen free condition, 950～1000 ℃ of temperature, time 25min～30min.
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| CN103956385A (en) * | 2014-04-30 | 2014-07-30 | 电子科技大学 | JFET device and manufacturing method thereof |
| CN103972295A (en) * | 2014-05-30 | 2014-08-06 | 电子科技大学 | JFET (junction field-effect transistor) device and manufacturing method thereof |
| CN103972302A (en) * | 2014-05-26 | 2014-08-06 | 电子科技大学 | JFET (junction field-effect transistor) device and manufacturing method thereof |
| CN105632932A (en) * | 2014-11-07 | 2016-06-01 | 北大方正集团有限公司 | Method for manufacturing JFET |
| CN104201208B (en) * | 2014-08-26 | 2016-11-30 | 电子科技大学 | A kind of constant current JFET device and manufacture method thereof |
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