CN102693959A - Grid resistor test structure for MOS transistor - Google Patents
Grid resistor test structure for MOS transistor Download PDFInfo
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- CN102693959A CN102693959A CN2011100729997A CN201110072999A CN102693959A CN 102693959 A CN102693959 A CN 102693959A CN 2011100729997 A CN2011100729997 A CN 2011100729997A CN 201110072999 A CN201110072999 A CN 201110072999A CN 102693959 A CN102693959 A CN 102693959A
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- mos transistor
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Abstract
The invention discloses a grid resistor test structure for a metal-oxide-semiconductor (MOS) transistor. The test structure includes m groups of MOS transistors; each group of the MOS transistors comprises n MOS transistors with various channel widths, wherein the MOS transistors in the same group have the identical channel length and different groups of MOS transistors have different channel lengths; and all the MOS transistors have the same type. According to the grid resistor test structure of MOS transistors, all coefficients in a resistance element Rg functional expression in an MOS transistor model can be visually obtained with consideration of the influence of a grid resistor on MOS transistor characteristics.
Description
Technical field
The present invention relates to the semiconductor test technology, particularly a kind of test structure that quantizes resistance to the device property influence.
Background technology
Along with MOS (Metal-Oxide-Semiconductor; Metal-oxide semiconductor (MOS)) transistor size dwindles; Resistance increases the influence of MOS transistor characteristic gradually, particularly in 45 nanometers and following technology, when the MOS transistor modelling, needs this factor is introduced.
When considering resistance to the influencing of MOS transistor characteristic; The model of MOS transistor is as shown in Figure 2; Mainly be on the MOS transistor grid, to add a resistive element Rg; This resistive element Rg can be expressed as channel length L, the channel width W of MOS transistor, the function of temperature T: Rg=Func (W, L, T).
But, can't obtain each coefficient in the functional expression of this resistive element Rg intuitively based on prior art.
Summary of the invention
The technical problem that the present invention will solve provides a kind of MOS transistor resistance test structure; Utilize this MOS transistor resistance test structure; In the time of obtaining considering resistance to the influencing of MOS transistor characteristic more intuitively, each coefficient in the functional expression of the resistive element Rg in the model of MOS transistor.
For solving the problems of the technologies described above, MOS transistor resistance test structure of the present invention comprises m group MOS transistor;
Each group MOS transistor comprises the MOS transistor of n different channel widths;
Same group of MOS transistor has same channel length;
MOS transistor does not have different channel lengths on the same group;
The type of each MOS transistor is identical;
M, n are positive integer.
The channel length L of e group MOS transistor
e=L
Min+ e* Δ L, L
MinBe minimum channel length, Δ L is the channel length difference, and e is more than or equal to 0 integer smaller or equal to m-1.
The channel width W of f MOS transistor in same group of MOS transistor
f=W
Min+ f* Δ W, W
MinBe minimum channel width, Δ W is the channel width difference, and f is more than or equal to 0 integer smaller or equal to n-1.
Each organizes the channel length of MOS transistor can be smaller or equal to 0.5um.
The channel width of each MOS transistor can be more than or equal to 1um.
Can get n >=3.
Same group of MOS transistor can be defined in same polysilicon.
Same group of MOS transistor can form a line along channel width dimension.
The grid of each MOS transistor, source electrode and substrate connect altogether.
N in a same group MOS transistor, the width of its source and drain active area is identical.
N in a same group MOS transistor, the active area that its substrate terminal is drawn is identical apart from the spacing of source and drain active area.
N in a same group MOS transistor, its grid exit polysilicon is identical apart from the spacing of source and drain active area.
The metal of each end of each MOS transistor utilizes multiple layer metal to pile up.
The raceway groove of each MOS transistor is identical to the distance on the border, both sides of trap.
The raceway groove of each MOS transistor to the distance on the border, both sides of trap more than or equal to 10um.
The type of each MOS transistor is all the N type or is all the P type.
Said MOS transistor resistance test structure is positioned in the test chip on the silicon chip or scribe line area.
MOS transistor resistance test structure of the present invention; Can pass through to test the P type of n different channel widths that obtain each channel length or electrical quantity characteristic (the threshold voltage vt h of N type MOS transistor; Saturation current Idsat) and the actual measurement relation curve between the resistance; Utilize P type or the electrical quantity characteristic (threshold voltage vt h, saturation current Idsat) of N type MOS transistor and the actual measurement relation curve between the resistance of n different channel widths of each channel length that said test obtains, can extract the functional expression Rg=Func (W of the resistive element Rg in the model of this P type or N type MOS transistor through match; L, each coefficient in T).Utilize MOS transistor resistance test structure of the present invention; Can obtain intuitively; When considering resistance to the influencing of MOS transistor characteristic; Each coefficient in the functional expression of resistive element Rg in the model of MOS transistor, thus the concrete functional expression of resistive element Rg in the model of MOS transistor obtained, to quantize the influence of resistance to the MOS transistor device property.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further explain.
Fig. 1 is the same group of MOS transistor one embodiment sketch map of MOS transistor resistance test structure of the present invention;
Fig. 2 is the model sketch map of the MOS transistor when considering resistance to the influencing of MOS transistor characteristic.
Embodiment
MOS transistor resistance test structure of the present invention; Comprise m group MOS transistor; Each group MOS transistor comprises the MOS transistor of n different channel widths, and same group of MOS transistor has same channel length, and MOS transistor does not have different channel lengths on the same group; The type of each MOS transistor identical (be all the N type or be all the P type), m, n are positive integer;
The channel length L of e group MOS transistor
eFor: L
e=L
Min+ e* Δ L, L
MinBe minimum channel length, Δ L is the channel length difference, and e is more than or equal to 0 integer smaller or equal to m-1, and the channel length of promptly respectively organizing MOS transistor is respectively: L
0=L
Min, L
1=L
Min+ Δ L, L
2=Lmin+2 Δ L ..., L
M-1=L
Min+ (m-1) Δ L; Each organizes the channel length of MOS transistor to observe design rule degree of being, chooses short channel device, a preferred embodiment, and each organizes the channel length of MOS transistor smaller or equal to 0.5um;
N MOS transistor in same group of MOS transistor, the channel width W of f MOS transistor
fFor: W
f=W
Min+ f* Δ W, W
MinBe minimum channel width, Δ W is the channel width difference, and f is more than or equal to 0 integer smaller or equal to n-1, and the channel width that promptly belongs to same group n MOS transistor is respectively: W
0=W
Min, W
1=W
Min+ Δ W, W
2=W
Min+ 2 Δ W ..., W
N-1=W
Min+ (n-1) Δ W; The channel width of MOS transistor is chosen with elimination narrow-channel effect degree of being, a preferred embodiment, and the channel width of each MOS transistor is more than or equal to 1um;
One preferred embodiment, same group of MOS transistor is as shown in Figure 1, comprises the individual MOS transistor of n (n >=3); This n MOS transistor of same group utilizes same polysilicon to define, and has identical channel length, different channel width; N the MOS transistor that this of same group has the different channel widths of same channel length forms a line along channel width dimension; The grid of each MOS transistor, source electrode and substrate connect altogether; Said n MOS transistor in same group; The width of its source and drain active area 101 is identical; The active area 205 that its substrate terminal is drawn is identical apart from the spacing of source and drain active area 101, and its grid 201 exit polysilicons 102 are identical apart from the spacing of source and drain active area 101; Through hole 103 as much as possible is arranged on its source and drain active area 101; The metal 104 of each end of each MOS transistor utilizes multiple layer metal to pile up; To reduce connection resistances as far as possible; The raceway groove 106 of each MOS transistor (being source and drain active area 101 and the overlapping place of polysilicon) is identical and far away as far as possible to the distance on the border, both sides 100 of trap, for example more than or equal to 10um;
Each organizes the structure of MOS transistor except that channel length, and other features is all consistent; In order to influence in the face with elimination technology, each group MOS transistor utilizes same polysilicon to define.
MOS transistor resistance test structure of the present invention can be positioned in the test chip on the silicon chip or scribe line area.
MOS transistor resistance test structure of the present invention; Can pass through to test the P type of n different channel widths that obtain each channel length or electrical quantity characteristic (the threshold voltage vt h of N type MOS transistor; Saturation current Idsat) and the actual measurement relation curve between the resistance; Utilize P type or the electrical quantity characteristic (threshold voltage vt h, saturation current Idsat) of N type MOS transistor and the actual measurement relation curve between the resistance of n different channel widths of each channel length that said test obtains, can extract the functional expression Rg=Func (W of the resistive element Rg in the model of this P type or N type MOS transistor through match; L, each coefficient in T).Utilize MOS transistor resistance test structure of the present invention; Can obtain intuitively; When considering resistance to the influencing of MOS transistor characteristic; Each coefficient in the functional expression of resistive element Rg in the model of MOS transistor, thus the concrete functional expression of resistive element Rg in the model of MOS transistor obtained, to quantize the influence of resistance to the MOS transistor device property.
Claims (17)
1. a MOS transistor resistance test structure is characterized in that, comprises m group MOS transistor;
Each group MOS transistor comprises the MOS transistor of n different channel widths;
Same group of MOS transistor has same channel length;
MOS transistor does not have different channel lengths on the same group;
The type of each MOS transistor is identical;
M, n are positive integer.
2. MOS transistor resistance test structure according to claim 1 is characterized in that, the channel length L of e group MOS transistor
e=L
Min+ e* Δ L, L
MinBe minimum channel length, Δ L is the channel length difference, and e is more than or equal to 0 integer smaller or equal to m-1.
3. MOS transistor resistance test structure according to claim 1 is characterized in that, the channel width W of f MOS transistor in same group of MOS transistor
f=W
Min+ f* Δ W, W
MinBe minimum channel width, Δ W is the channel width difference, and f is more than or equal to 0 integer smaller or equal to n-1.
4. MOS transistor resistance test structure according to claim 1 is characterized in that each organizes the channel length of MOS transistor smaller or equal to 0.5um.
5. MOS transistor resistance test structure according to claim 1 is characterized in that the channel width of each MOS transistor is more than or equal to 1um.
6. MOS transistor resistance test structure according to claim 1 is characterized in that n >=3.
7. MOS transistor resistance test structure according to claim 1 is characterized in that, same group of MOS transistor is defined in same polysilicon.
8. MOS transistor resistance test structure according to claim 1 is characterized in that same group of MOS transistor forms a line along channel width dimension.
9. MOS transistor resistance test structure according to claim 1 is characterized in that the grid of each MOS transistor, source electrode and substrate connect altogether.
10. MOS transistor resistance test structure according to claim 1 is characterized in that, n MOS transistor in same group, and the width of its source and drain active area is identical.
11. MOS transistor resistance test structure according to claim 1 is characterized in that, n MOS transistor in same group, and the active area that its substrate terminal is drawn is identical apart from the spacing of source and drain active area.
12. MOS transistor resistance test structure according to claim 1 is characterized in that, n MOS transistor in same group, and its grid exit polysilicon is identical apart from the spacing of source and drain active area.
13. MOS transistor resistance test structure according to claim 1 is characterized in that, the metal of each end of each MOS transistor utilizes multiple layer metal to pile up.
14. MOS transistor resistance test structure according to claim 1 is characterized in that the raceway groove of each MOS transistor is identical to the distance on the border, both sides of trap.
15. MOS transistor resistance test structure according to claim 14 is characterized in that, the raceway groove of each MOS transistor to the distance on the border, both sides of trap more than or equal to 10um.
16. MOS transistor resistance test structure according to claim 1 is characterized in that, the type of each MOS transistor is all the N type or is all the P type.
17. MOS transistor resistance test structure according to claim 1 is characterized in that, said MOS transistor resistance test structure is positioned in the test chip on the silicon chip or scribe line area.
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|---|---|---|---|
| CN201110072999.7A CN102693959B (en) | 2011-03-25 | 2011-03-25 | Grid resistor test structure for MOS transistor |
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|---|---|---|---|
| CN201110072999.7A CN102693959B (en) | 2011-03-25 | 2011-03-25 | Grid resistor test structure for MOS transistor |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103575998A (en) * | 2013-10-25 | 2014-02-12 | 中国科学院半导体研究所 | Method for testing resistance of non-junction transistors |
| CN104764932A (en) * | 2014-01-07 | 2015-07-08 | 北大方正集团有限公司 | Measurement device and method for well resistor of MOS |
| CN105137329A (en) * | 2015-09-12 | 2015-12-09 | 上海华虹宏力半导体制造有限公司 | Method and system for checking floating of grid of MOS field effect transistor in circuit |
| CN108766957A (en) * | 2018-06-20 | 2018-11-06 | 上海华虹宏力半导体制造有限公司 | Semi-conductor test structure and semiconductor structure |
| CN112213562A (en) * | 2020-09-23 | 2021-01-12 | 龙腾半导体股份有限公司 | Method for measuring and calculating internal resistance of grid electrode of power semiconductor device |
| WO2021077389A1 (en) * | 2019-10-25 | 2021-04-29 | 江苏时代全芯存储科技股份有限公司 | Memory element array |
| WO2024036721A1 (en) * | 2022-08-17 | 2024-02-22 | 长鑫存储技术有限公司 | Contact resistance acquisition method and apparatus, electronic device, and storage medium |
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| CN101281897A (en) * | 2007-04-06 | 2008-10-08 | 中芯国际集成电路制造(上海)有限公司 | Matrix type structure for testing integrality of gate oxic horizon |
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Patent Citations (5)
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| US6518592B1 (en) * | 2000-05-01 | 2003-02-11 | Mitsubushi Denki Kabushiki Kaisha | Apparatus, method and pattern for evaluating semiconductor device characteristics |
| US20040214356A1 (en) * | 2003-04-25 | 2004-10-28 | Cheng-Tung Huang | Method of measuring a gate channel length of a metal-oxide semiconductor transistor |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103575998A (en) * | 2013-10-25 | 2014-02-12 | 中国科学院半导体研究所 | Method for testing resistance of non-junction transistors |
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| CN104764932A (en) * | 2014-01-07 | 2015-07-08 | 北大方正集团有限公司 | Measurement device and method for well resistor of MOS |
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| CN105137329A (en) * | 2015-09-12 | 2015-12-09 | 上海华虹宏力半导体制造有限公司 | Method and system for checking floating of grid of MOS field effect transistor in circuit |
| CN105137329B (en) * | 2015-09-12 | 2018-07-20 | 上海华虹宏力半导体制造有限公司 | The hanging method and system of metal-oxide-semiconductor field effect transistor grid in a kind of inspection circuit |
| CN108766957A (en) * | 2018-06-20 | 2018-11-06 | 上海华虹宏力半导体制造有限公司 | Semi-conductor test structure and semiconductor structure |
| WO2021077389A1 (en) * | 2019-10-25 | 2021-04-29 | 江苏时代全芯存储科技股份有限公司 | Memory element array |
| CN112213562A (en) * | 2020-09-23 | 2021-01-12 | 龙腾半导体股份有限公司 | Method for measuring and calculating internal resistance of grid electrode of power semiconductor device |
| WO2024036721A1 (en) * | 2022-08-17 | 2024-02-22 | 长鑫存储技术有限公司 | Contact resistance acquisition method and apparatus, electronic device, and storage medium |
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| CN102693959B (en) | 2014-12-10 |
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