WO2021077389A1

WO2021077389A1 - Memory element array

Info

Publication number: WO2021077389A1
Application number: PCT/CN2019/113228
Authority: WO
Inventors: 刘峻志; 廖昱程; 邱泓瑜; 李宜政
Original assignee: 江苏时代全芯存储科技股份有限公司; 江苏时代芯存半导体有限公司
Priority date: 2019-10-25
Filing date: 2019-10-25
Publication date: 2021-04-29
Also published as: CN111527609A; CN111527609B

Abstract

A memory element array, including a plurality of bit lines, a plurality of word lines and a plurality of transistors. The plurality of word lines intersect and are electrically insulated from the bit lines; each of the plurality of transistors includes a source/drain electrode and a gate electrode; the source/drain electrode of each transistor is electrically connected to one of the bit lines; the gate electrode is electrically connected to one of the word lines; and at least two of the gate electrodes of the transistors have different lengths. When the memory element array is tested, more memory element data can be obtained.

Description

Memory device array

Technical field

The present disclosure relates to a memory device array.

Background technique

Memory is a semiconductor device used to store data, which can be divided into non-volatile memory and volatile memory. With the vigorous development of technology, the industry's demand for memory performance has gradually increased, such as high reliability, high erase and write cycles, fast storage speed, and large capacity. Therefore, the semiconductor industry continues to develop various technologies to reduce device size and increase the device density of memory.

In the prior art, as shown in FIG. 1A, a wafer includes a plurality of standard memory product chips Cp1, Cp2, Cp4, which are separated by dicing lines S1 and S2. In order to further understand the characteristics of the memory components in the memory chip, at least one test chip (Test Chip), such as the test chip Cp3, is set in the wafer, and it includes multiple memory test arrays, such as A11, A21, Ax1 , A1y, A2y, Axy, etc.

FIG. 1B is a partial enlarged schematic diagram of the test wafer Cp3 in FIG. 1A. As shown in FIG. 1B, each of the memory test arrays A11, A12, A21, A22 includes a memory device array 10, and the memory device array 10 includes a plurality of memory devices (not shown), for example, each The memory device array 10 may include 100 memory devices. Each memory element array 10 has its own test pad for testing the characteristics of the memory elements in the memory element array 10. Taking the memory device array 10 with 100 memory devices as an example, the test pads must include at least 10 character signal pads (such as conductive pads 1A to 1L) and 10 bit signal pads (such as conductive pads 2A to 2L). ) To access 100 individual memory devices in the memory device array 10 and test their characteristics.

In the prior art, the individual memory elements in the memory element array 10 are identical to each other. Therefore, this type of memory element array can also be referred to as a single device array (single device array). However, when testing the memory cell array, only the test data of a single-designed memory device can be obtained. Therefore, how to accommodate a variety of memory devices with different design features in the limited space of the test chip Cp3 is one of the technical problems to be solved at present.

Summary of the invention

The present disclosure provides a memory device array including multiple bit lines, multiple word lines, and multiple transistors. Multiple word lines and bit lines are interlaced and electrically insulated; multiple transistors each include a source/drain and a gate; the source/drain of each transistor is electrically connected to one of the bit lines; the gate is electrically connected One of the word lines; at least two of the gates of the transistors have different lengths.

According to some embodiments of the present disclosure, at least two of the gates of the transistor have different widths.

According to some embodiments of the present disclosure, one of the bit lines further includes a phase change memory device (Phase Change Memory; PCM).

According to some embodiments of the present disclosure, at least two of the bit lines respectively further include a phase change memory device.

According to some embodiments of the present disclosure, each bit line further includes phase change memory devices.

According to some embodiments of the present disclosure, the phase change memory elements each include a heater and a phase change material layer, the phase change material layer is located above the heater, and has a cross section in contact with the heater, and at least two of the area of the cross section Available in different sizes.

According to certain embodiments of the present disclosure, at least two of the phase change material layers have different thicknesses.

According to some embodiments of the present disclosure, a wire is further included to electrically connect the two word lines.

Description of the drawings

When you read the accompanying drawings, you can fully understand all aspects of the present disclosure from the following detailed description. It is worth noting that according to industry standard practice, various features are not drawn to scale. In fact, for clear discussion, the size of various features can be increased or decreased arbitrarily.

FIG. 1A shows a top view of a memory product chip and a test chip in the prior art;

FIG. 1B is a partial enlarged schematic diagram of the memory test chip in FIG. 1A;

Figure 2A shows an array of memory cells;

FIG. 2B shows the design features of the memory cell array of FIG. 2A;

Figure 3A shows an array of memory cells;

FIG. 3B shows the design features of the memory cell array of FIG. 3A;

4A is a schematic diagram showing a memory multi-element array according to an embodiment of the present disclosure;

FIG. 4B shows the design features of the memory multi-element array of FIG. 4A;

5A is a schematic diagram showing a memory multi-element array according to an embodiment of the present disclosure;

FIG. 5B shows the design features of the memory multi-element array of FIG. 5A;

6A is a schematic diagram of a memory multi-element array according to an embodiment of the present disclosure;

FIG. 6B shows the design features of the memory multi-element array of FIG. 6A;

FIG. 7 is a schematic diagram of a memory test array according to some embodiments of the present disclosure;

FIG. 8 illustrates a schematic diagram of a memory test array according to some embodiments of the present disclosure.

【Symbol Description】

1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 1J, 1K, 1L, 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J, 2K, 2L Conductive pad

10.10A Memory element array

10’, 10A’, 10B’ memory multi-element array

11A, 11B, 11C, 11D, 11E, 11F, 11G, 11H, 11I, 11J, 11K, 11L First conductive pad

12A, 12B, 12C, 12D, 12E, 12F, 12G, 12H, 12I, 12J, 12K, 12L The first common conductive pad

13A, 13B, 13C, 13D, 13E, 13F, 13G, 13H, 13I, 13J, 13K, 13L Second conductive pad

14A, 14B, 14C, 14D, 14E, 14F, 14G, 14H, 14I, 14J, 14K, 14L Second common conductive pad

15A, 15B, 15C, 15D, 15E, 15F, 15G, 15H, 15I, 15J, 15K, 15L Third conductive pad

20, 21, 22, 23, 24, 25 Memory components

100, 200 memory test array

110 First memory array

121 First End

122 second end

130 Second memory array

141 First End

142 Second End

150 Third memory array

210, 212, 220, 230, 232, 240, 252 wire

800, 800P memory unit sub-array

900, 900P Memory multi-element sub-array

A11, A12, A21, A22, Ax1, A1y, A2y, Axy Memory test array

BL, BL1～BL10 bit lines

BL’, BL1’～BL10’ bit lines

Cp1, Cp2, Cp4 Memory product chips

Cp3 test chip

PCM, PCM1～10 phase change memory components

S1, S2 cutting road

MOS, MOS1～6, MOS6’, MOS7～11 transistors

WL1～6, WL6’, WL7～11 word lines

Detailed ways

Hereinafter, multiple implementations of the present disclosure will be disclosed with the accompanying drawings. For clear description, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the content of this disclosure. In other words, in some implementations of the present disclosure, these practical details are unnecessary. In addition, for clarity, the size or thickness of the component may be exaggerated, and the drawing is not based on the original size. In addition, for the sake of simplifying the illustration, some known and conventional structures and elements will be shown in a simple schematic manner in the illustration.

Spatial relative terms, such as "below", "below", "above", "above", etc., are used in this text to facilitate the description of the relative relationship between one element or feature and another element or feature, such as Shown in the figure. The true meaning of these relative terms in space includes other directions. For example, when the figure is turned upside down by 180 degrees, the relationship between one element and another element may change from "below" and "below" to "above" and "above". In addition, the relative narrative in space used in this article should also be interpreted in the same way.

The present disclosure discloses a memory test array and a memory element array used in the memory test array. Compared with the known single device array (single device array), the memory device array disclosed in the present disclosure has a plurality of memory devices with different design features, which can also be called a multi-device array (multi-device array). ). For example, the transistors of each memory device may have different gate lengths or different gate widths. For another example, some of the memory devices include phase change memory devices (PCM), or some of the memory devices do not include phase change memory devices. For another example, some of the memory devices may be a transistor-resistor (1T1R) structure, or some of the memory devices may be a two-transistor-resistor (2T1R) structure. Because the memory multi-element array includes multiple memory elements with different design features, when testing the memory multi-element array, more memory element data can be obtained than when testing the memory cell array.

In this article, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) will be used as an example. However, the embodiments of the present disclosure are not limited to MOSFETs, and can also be used in memory device arrays. Other kinds of transistors.

FIG. 2A shows the memory cell array 10, and FIG. 2B shows the design features of the memory cell array of FIG. 2A. The memory cell array 10 includes 10 memory element sub-arrays 800. To simplify the description, FIG. 2A only shows two memory element sub-arrays 800. The ten memory element sub-arrays 800 respectively include bit lines BL1 to BL10. To simplify the description, FIG. 2A only shows the bit lines BL1 and BL10. Taking the memory element sub-array 800 including the bit line BL1 as an example, the structure of the memory element sub-array 800 is further described. The bit line BL1 is interleaved with and electrically insulated from the ten word lines WL1 to WL10. The ten transistors MOS1 to MOS10 each include a source/drain and a gate. The source/drain of each transistor is electrically connected to one of the bit lines Furthermore, the gate of each transistor is electrically connected to one of the word lines. The equivalent circuit of a memory device 20 is composed of a single bit line, a single word line and a single transistor. Therefore, the memory device sub-array 800 includes 10 memory devices 20. The present disclosure is not limited to this. In other embodiments, the number of bit lines, word lines, and transistors can be adjusted arbitrarily.

Continuing to refer to FIG. 2A, each memory device 20 includes a transistor, and these transistors each have the same design features. In detail, these transistors all have the same gate width and/or the same gate length. As shown in FIG. 2B, the gate length of the transistors MOS1 to MOS10 is about 0.26um, and the gate width is about 0.1um.

FIG. 3A shows another memory cell array 10A, and FIG. 3B shows the design features of the memory cell array of FIG. 3A. The difference between the memory cell array 10A of FIG. 3A and the memory cell array 10 of FIG. 2A is that each bit line BL1'˜BL10' further includes a phase change memory device (PCM). In other words, the memory cell array 10A also includes 10 phase change memory elements PCM1 to PCM10. To simplify the description, only PCM1 and PCM10 are shown in FIG. 3A. Taking the memory element sub-array 800P containing the bit line BL1' as an example, the structure of the memory element sub-array 800P is further described. Compared with the memory element sub-array 800 of 2A, the bit line BL1' of the memory element sub-array 800P further includes a phase change memory element PCM1. The equivalent circuit of a memory device 21 is composed of a single bit line, a single word line, a single transistor, and a single phase change memory device. However, the present disclosure is not limited to this. In other embodiments, the number of bit lines, word lines, transistors, and PCM can be adjusted arbitrarily.

In some embodiments, the phase change memory elements PCM1 to PCM10 each include a heater and a phase change material layer (not shown). The phase change material layer is located above the heater and has a cross section in contact with the heater. The state of the phase change material layer can be changed by heating to become crystalline (Crystalline) or amorphous (Amorphous). These different states have corresponding resistance values. The phase change memory device is equivalent to a resistor. In some embodiments, the phase change material layer includes GeSbTe (GST), or other types of phase change materials may also be used.

3A, the equivalent circuit of each memory element 21 includes a phase change memory element and a transistor, and the phase change memory elements PCM1 to PCM10 each have the same design features, and the transistors MOS1 to MOS10 each have the same design feature. As shown in FIG. 3B, the area of the cross section of the heater and the phase change material layer of the phase change memory elements PCM1 to PCM10 is about 0.17×0.25 um ² and the thickness of the phase change material layer is about 0.1 um.

When testing the memory cell array 10 of FIG. 2A and the memory cell array 10A of FIG. 3A, only the test data of the memory device with a single design can be obtained. As shown in FIG. 2A, the equivalent circuit of each memory element 20 of the memory cell array 10 only includes one transistor, so the memory cell array 10 has a 1T structure. As shown in FIG. 3A, the equivalent circuit of each memory element 21 of the memory cell array 10A includes a transistor and a resistor, so the memory cell array 10A has a 1T1R structure.

In order to obtain more memory device data during the test phase, the structure design of transistor (MOS), phase change memory device (PCM), 1T structure and 1T1R structure can be changed. A memory element array containing multiple design features is called a memory multi-element array, which will be described in detail below.

4A is a schematic diagram showing a memory multi-element array according to an embodiment of the present disclosure, and FIG. 4B shows the design features of the memory multi-element array of FIG. 4A. The memory multi-element array 10' includes 10 memory element sub-arrays 900. To simplify the description, FIG. 4A only shows two memory element sub-arrays 900. The ten memory element sub-arrays 900 respectively include bit lines BL1 to BL10. To simplify the description, Fig. 4A only shows the bit lines BL1 and BL10. Taking the memory element sub-array 900 including the bit line BL1 as an example, the structure of the memory element sub-array 900 is further described. The bit line BL1 and the 12 word lines WL1 to WL11 are interleaved and electrically insulated. The 12 transistors MOS1 to MOS11 each include a source/drain and a gate. The source/drain of each transistor is electrically connected to one of the bit lines Furthermore, the gate of each transistor is electrically connected to one of the word lines. The equivalent circuit of a memory element 22 is composed of a single bit line, a single word line and a single transistor, and the equivalent circuit of a memory element 23 is composed of a single bit line, two word lines, and two The word line is composed of one wire and two transistors. Therefore, the memory device sub-array 900 includes 10 memory devices 22 and 1 memory device 23. The present disclosure is not limited to this. In other embodiments, the number of bit lines, word lines, and transistors can be adjusted arbitrarily.

Continuing to refer to FIGS. 4A and 4B, the equivalent circuit of each memory element 22 includes a transistor, and each has a different gate width. As shown in FIG. 4B, the gate length of the transistor MOS1 is about 0.26um, and the gate width is about 0.1um, the gate length of the transistor MOS2 is about 0.24um, and the gate width is about 0.1um. The transistors MOS1 to MOS5 each have the same gate length of about 0.1um, and the gate width varies from about 0.26um to about 0.32um. Compared with the single device design of FIG. 2B, the multi-element design of FIG. 4B can obtain memory device data with different gate widths when testing the memory multi-element array 10' of FIG. 4A.

Continuing to refer to FIGS. 4A and 4B, at least two of the gates of the transistors of the memory element 22 have different lengths. As shown in FIG. 4B, the gate width of the transistors MOS7 to MOS11 is about 0.26um, and the gate length varies from about 0.06um to about 0.12um. Through the multi-element design of FIG. 4B, compared with the single-element design of FIG. 2B, the memory device data with different gate lengths can be obtained when the memory multi-element array 10' of FIG. 4A is tested.

4A, the equivalent circuit of the memory device structure 22 of the memory multi-element array 10' includes one transistor (1T), the memory device structure 23 includes two transistors (2T), the word line WL6 and the word line WL6' pass The wire AA is electrically connected. Therefore, the memory device data with 1T and 2T can be obtained when the memory multi-element array 10' is tested. However, the present disclosure is not limited to this, and the wire AA can be electrically connected to any two of the word lines WL of the memory element sub-array 900. In other embodiments, the wire AA is electrically connected to WL6 and WL7, electrically connected to WL6 and WL8, or electrically connected to WL6 and WL9.

In summary, when testing the memory multi-element array 10' shown in FIG. 4A and FIG. 4B, test data of memory devices with different design features can be obtained. For example, when the test probes are electrically connected to WL1 to WL5 and connected to BL1, data of different gate widths can be obtained (1T structure). When the test probes are electrically connected to WL7 to WL11 and connected to BL1, data of different gate lengths can be obtained (1T structure). When the test probe is electrically connected to WL1, WL6, WL6' and connected to BL1, data of 2T and 1T structures can be obtained under the same gate length.

FIG. 5A is a schematic diagram showing a memory multi-element array according to an embodiment of the present disclosure, and FIG. 5B shows the design features of the memory multi-element array of FIG. 5A. The difference between the memory cell array 10A' of FIG. 5A and the memory cell array 10' of FIG. 4A is that each bit cell line BL1' to BL10' further includes a phase change memory element PCM1 to PCM10. In other words, the memory cell array 10A' further includes 10 phase change memory elements PCM1 to PCM10. To simplify the description, FIG. 5A only shows PCM1 and PCM10. In detail, compared with the memory device 22 of FIG. 4A, the equivalent circuit of the memory device 24 of FIG. 5A further includes a phase change memory device. Therefore, the memory device 24 constitutes a 1T1R architecture. Similar to FIG. 4A, the wire AA is electrically connected to the word line WL6 and the word line WL6', so that the equivalent circuit of the memory device 25 includes two transistors, forming a 2T1R structure. With this design, when testing the memory multi-element array 10A' of FIG. 5A, memory device data with 1T1R architecture (memory device 24) and 2T1R architecture (memory device 25) can be obtained.

Continuing to refer to FIG. 5A, the phase change memory devices PCM1 to PCM10 can also have different design features. In some embodiments, the phase change memory elements PCM1 to PCM10 each include a heater and a phase change material layer (not shown). The phase change material layer is located above the heater and has a cross section in contact with the heater. The area of the cross section is At least two of them have different sizes. In some embodiments, at least two of the phase change material layers have different thicknesses. In some embodiments, the phase change material layer includes GeSbTe (GST), or other types of phase change materials may also be used. As shown in FIG. 5B, the thickness of each phase change material layer of PCM1 to PCM10 varies from about 0.1 to about 0.19 um. The cross-sectional area of each heater PCM5 PCM1 to the respective phase change material layer between about 0.17x0.15um ² to about 0.17x0.40um ² changes. The cross-sectional area of each heater PCM6 PCM10 to the respective phase change material layer between about 0.18x0.35um ² to about 0.22x0.35um ² changes.

Continuing to refer to FIG. 5B, similar to FIG. 4B, the memory multi-element array 10A' shown in FIG. 5A may include different transistor designs. Therefore, the memory multi-element array 10A' shown in FIG. 5A can include different 1T1R structures.

In summary, when testing the memory multi-element array 10A' shown in FIG. 5A and FIG. 5B, test data of memory devices with different design features can be obtained. For example, when the test probes are electrically connected to WL1 to WL5 and connected to BL1', data with different gate widths in the 1T1R structure can be obtained. When the test probes are electrically connected to WL7 to WL11 and to BL1', data of different gate lengths in the 1T1R structure can be obtained. When the test probe is electrically connected to WL1, WL6, WL6' and connected to BL1', data including 2T1R and 1T1R structures can be obtained with the same gate length.

6A is a schematic diagram of a memory multi-element array according to an embodiment of the present disclosure, and FIG. 6B shows the design features of the memory device of FIG. 6A. As shown in FIG. 6A, the memory multi-element array 10B' includes the plurality of memory element sub-arrays 900 (without PCM) described in FIG. 4A and the plurality of memory element sub-arrays 900P (with PCM), these memory element sub-arrays are arranged alternately. In other words, the memory multi-element array 10B' includes some memory devices that do not include PCM and some memory devices that include PCM. In the memory element sub-array 900P shown in FIG. 6A, from left to right, the memory element sub-array 900P includes bit lines BL1', BL3', BL5', BL7', and BL9', respectively. Please refer to FIG. 5A for the structure of the memory device sub-array 900P containing these bit lines. In the memory element sub-array 900 shown in FIG. 6A, from left to right, the memory element sub-array 900 includes bit lines BL2, BL4, BL6, BL8, and BL10, respectively. Please refer to FIG. 4A for the structure of the memory device sub-array 900 containing these bit lines. With the above configuration, the memory multi-element array 10' shown in FIG. 6A includes different transistor designs, different phase change memory device (PCM) designs, and also includes 1T, 2T, 1T1R, and 2T1R structures.

It should be understood that the transistor and phase change memory device (PCM) design features shown in FIGS. 2B, 3B, 4B, 5B, and 6B are exemplary and not restrictive. The transistor and phase change memory device (PCM) The design of) can be various suitable designs.

In summary, please refer to FIG. 4A, FIG. 5A, and FIG. 6A. When testing the memory multi-element array 10B' shown in FIG. 6A, test data of memory devices with different design features can be obtained. For example, when the test probes are electrically connected to WL1 to WL5 and connected to BL2, data of transistors of different designs can be obtained in the 1T structure. When connecting WL1 to WL5 and connecting BL1, the data of 1T1R structure including transistors of different designs can be obtained, and the PCM is designed as a phase change memory device PCM1. When WL1, BL1, and BL3 are connected, the data of 1T1R architecture including PCMs of different designs can be obtained, and these PCMs are designed as phase change memory elements PCM1, PCM3. When connecting WL6, WL6', BL1 and BL3, data of 2T1R architecture including PCMs of different designs can be obtained, and these PCMs are designed as phase change memory elements PCM1 and PCM3.

It should be understood that the design concept of such a memory multi-element array can continue to change, and is not limited to the design features of the memory multi-element array shown in FIG. 4A, FIG. 5A, and FIG. 6A. The test data obtained in the test phase is also not limited to this, and any memory device data obtained based on the design features of the memory multi-element array can be obtained.

In summary, the memory multi-element array includes different memory elements, so that in the test phase, more element data can be obtained from the memory multi-element array.

Furthermore, in order to accommodate more memory test arrays in the limited space of the test chip, two adjacent memory device test arrays can share conductive pads, which will be further described below.

FIG. 7 illustrates a schematic diagram of a memory test array 100 according to some embodiments of the present disclosure. Referring to FIG. 7, the memory test array 100 includes a first memory array 110, a second memory array 130, and a plurality of first common conductive pads 12A-12L. The second memory array 130 is adjacent to the first memory array 110. In some embodiments, the plurality of first common conductive pads 12A-12L are located between the first memory array 110 and the second memory array 130.

In some embodiments, the first memory device array 110 includes a plurality of first bit lines, a plurality of first word lines, and a plurality of first transistors. The plurality of first word lines and the first bit lines are interlaced and electrically insulated; each of the plurality of first transistors includes a first source/drain and a first gate; the first source/drain of each first transistor is electrically Is connected to one of the first bit lines; the first gate is electrically connected to one of the first word lines; at least two of the first gates of the first transistor have different lengths, and the first transistor At least two of the first gates have different widths.

In some embodiments, each of the first bit lines of the first memory device array 110 includes a phase change memory device.

In some embodiments, the second memory element array 130 adjacent to the first memory element array 110 includes a plurality of second bit lines, a plurality of second word lines, and a plurality of second transistors. The plurality of second word lines and the second bit lines are interlaced and electrically insulated; each of the plurality of second transistors includes a second source/drain and a second gate; the second source/drain of each second transistor is electrically Is connected to one of the second bit lines, the second gate is electrically connected to one of the second word lines; at least two of the second gates of the second transistor have different lengths, and the second transistor At least two of the second gates have different widths.

In some embodiments, each of the second bit lines of the second memory device array 130 includes a phase change memory device.

In some embodiments, each of the plurality of first common conductive pads 12A-12L has a first end 121 and a second end 122; the first end 121 is electrically connected to the first bit line and the second end 122 is electrically connected On the second bit line, or the first terminal 121 is electrically connected to the first word line and the second terminal 122 is electrically connected to the second word line. In detail, in some embodiments, the first end 121 can be coupled to the first bit line of the first memory array 110, and the second end 122 can be coupled to the second bit of the second memory array 130. Yuan line. In other embodiments, the first terminal 121 may be coupled to the first word line of the first memory array 110, and the second terminal 122 may be coupled to the second word line of the second memory array 130. In more detail, in some embodiments, the first end 121 of the first common conductive pad 12L can be equipotentially connected to a corresponding first bit line in the first memory array 110 through the wire 210, and its first bit line The two terminals 122 can be connected to a corresponding second bit line in the second memory array 130 through the wire 220 at an equal potential. Alternatively, in other embodiments, the first end 121 of the first common conductive pad 12L may be equipotentially connected to a corresponding first word line in the first memory array 110 through the wire 210, and the second end 122 may pass through The wire 220 is equipotentially connected to a corresponding second word line in the second memory array 130.

In some embodiments, the

memory arrays

110 and 130 may be independent of the memory multi-element arrays 10', 10A', or 10B' disclosed in this disclosure, which include memory elements with different design features.

Please continue to refer to Figure 7. In some embodiments, the memory test array 100 further includes a plurality of first conductive pads 11A-11L and a plurality of second conductive pads 13A-13L. As shown in FIG. 7, each of the first conductive pads 11A-11L is coupled to the first memory array 110, and the first conductive pads 11A-11L and the first common conductive pads 12A-12L are located in the first memory array Opposite sides of 110. Each of the second conductive pads 13A-13L is coupled to the second memory array 130, and the second conductive pads 13A-13L and the first common conductive pads 12A-12L are located on opposite sides of the second memory array 130. In some embodiments, the first conductive pads 11A-11L can be coupled to the corresponding first word line in the first memory array 110, and the first common conductive pads 12A-12L are coupled in the first memory array 110 The corresponding first bit line and the corresponding second bit line in the second memory array 130, and the second conductive pads 13A-13L are coupled to the corresponding second word line in the second memory array 130. In other embodiments, the first conductive pads 11A-11L may be coupled to the corresponding first bit line in the first memory array 110, and the first common conductive pads 12A-12L are coupled in the first memory array 110 The corresponding first word line and the corresponding second word line in the second memory array 130, and the second conductive pads 13A-13L are coupled to the corresponding second bit line in the second memory array 130.

In detail, each of the first bit lines in the first memory array 110 can be connected to a corresponding one of the first conductive pads 11A-11L through the wires 212 respectively. For example, the first bit line may be equipotentially connected to the first conductive pad 11L. Each first word line of the first memory array 110 can be connected to the first end 121 of the corresponding one of the first common conductive pads 12A-12L through the wires 210 respectively. For example, the first word line is equipotentially connected to the first common conductive pad 12L.

Similarly, each second bit line in the second memory array 130 can be connected to a corresponding one of the second conductive pads 13A-13L through the wires 232 at an equipotential level. For example, the second bit line is equipotentially connected to the second conductive pad 13L. Each second word line of the second memory array 130 can be connected to the second end 122 of the corresponding one of the first common conductive pads 12A-12L through the wires 220 respectively. For example, the second word line is equipotentially connected to the first common conductive pad 12L. That is, the first common conductive pads 12A-12L can be equipotentially connected to a first word line corresponding to the first memory array 110 and a second word line corresponding to the second memory array 130 at the same time. For example, the first common conductive pad 12L is connected to the first word line of the first memory array 110 and the second word line of the second memory array 130 at the same time. In some embodiments, the memory test array 100 may also include other elements. For example, virtual shared conductive pads.

It should be understood that the numbers and sizes of the first conductive pads 11A-11L, the first common conductive pads 12A-12L, and the second conductive pads 13A-13L shown in FIG. 7 are only examples, and the present disclosure is not limited thereto. The first conductive pads 11A-11L, the first common conductive pads 12A-12L, and the second conductive pads 13A-13L can be correspondingly arranged according to the number of memory cells included in the first memory array 110 and the second memory array 130 .

FIG. 8 illustrates a schematic diagram of a memory test array 200 according to some embodiments of the present disclosure. The memory test array 200 and the elements with the same element numbers in the memory test array 100 shown in FIG. 7 may be the same or similar. Therefore, the components included in the first memory array 110, the first common conductive pads 12A-12L, and the second memory array 130 in the memory test array 200 and their connection relationships will not be described in detail below. As shown in FIG. 8, the memory test array 200 further includes a third memory array 150 and second common conductive pads 14A-14L.

The third memory array 150 is adjacent to the second memory array 130. The third memory array 150 may be the same as or similar to the first memory array 110 and the second memory array 130. That is, in some embodiments, the third memory array 150 may be the memory multi-element array 10', 10A', or 10B' disclosed in this disclosure, which includes memory elements with different design features.

As shown in FIG. 8, a plurality of second common conductive pads 14A-14L are located between the second memory array 130 and the third memory array 150, and each of the second common conductive pads 14A-14L has a first end 141 and the second end 142. In some embodiments, the first end 141 of the second common conductive pad 14A-14L can be coupled to the second bit line of the second memory array 130, and the second end 142 can be coupled to the third memory array The third bit line of 150. In other embodiments, the first terminal 141 may be coupled to the second word line of the second memory array 130, and the second terminal 142 may be coupled to the third word line of the third memory array 150.

In detail, in some embodiments, the first ends 141 of the second common conductive pads 14A-14L may be equipotentially connected to a second bit line corresponding to the second memory array 130 through the wires 230, and the first The two terminals 142 can be connected to a third bit line corresponding to the third memory array 150 via the wires 240 respectively. Alternatively, in other embodiments, the first ends 141 of the second common conductive pads 14A-14L can be connected to a second word line corresponding to the second memory array 130 via wires 230 and the second ends 142 thereof. It can be connected to a third word line corresponding to the third memory array 150 through the wires 240 respectively.

Please continue to refer to Figure 8. In some embodiments, the memory test array 200 further includes a plurality of first conductive pads 11A-11L and a plurality of third conductive pads 15A-15L. The first conductive pads 11A-11L and the first common conductive pads 12A-12L are located on opposite sides of the first memory array 110. The third conductive pads 15A-15L are coupled to the third memory array 150, and the third conductive pads 15A-15L and the second common conductive pads 14A-14L are located on opposite sides of the third memory array 150.

In some embodiments, each of the first conductive pads 11A-11L may be equipotentially connected to a corresponding first word line of the first memory array 110 through the wire 212. The first common conductive pads 12A-12L are equipotentially connected to a corresponding first bit line of the first memory array 110 through wires 210, and are equipotentially connected to a corresponding second bit line of the second memory array 130 through wires 220. Yuan line. The second common conductive pads 14A-14L are equipotentially connected to a corresponding second word line of the second memory array 130 through a wire 230, and are equipotentially connected to a corresponding third word line of the third memory array 150 through a wire 240 . Each of the third conductive pads 15A-15L is equipotentially connected to a corresponding third bit line of the third memory array 150 through a wire 252.

In other embodiments, each of the first conductive pads 11A-11L may be equipotentially connected to a corresponding first bit line of the first memory array 110 through the wire 212. The first common conductive pads 12A-12L are equipotentially connected to a corresponding first word line of the first memory array 110 through a wire 210, and are equipotentially connected to a corresponding second word line of the second memory array 130 through a wire 220 . The second common conductive pads 14A-14L are equipotentially connected to a corresponding second bit line of the second memory array 130 through the wire 230, and are equipotentially connected to a corresponding third bit of the third memory array 150 through the wire 240 Yuan line. Each third conductive pad 15A-15L is equipotentially connected to a corresponding third word line of the third memory array 150 through a wire 252.

It is worth noting that in the memory test array 200, opposite sides of the second memory array 130 are a plurality of first common conductive pads 12A-12L and a plurality of second common conductive pads 14A-14L. That is, the second bit line in the second memory array 130 can be equipotentially connected to the corresponding one of the first common conductive pads 12A-12L through the wire 220, and then further equipotentially connected to the first memory array 110 The first bit line. In addition, the second word line in the second memory array 130 can be equipotentially connected to the corresponding one of the second common conductive pads 14A-14L through the wire 230, and further equipotentially connected to the third one of the third memory array 150. Word line.

This concept of shared conductive pads can be extended and is not limited to the

memory test arrays

100 and 200 shown in FIGS. 7 and 8. In detail, a common conductive pad can be provided between two adjacent memory arrays to equipotentially connect their bit lines or equipotentially connect their word lines.

As described above, according to the embodiments of the present disclosure, the memory test array with the memory multi-element array of the present disclosure can obtain more memory device data in the test phase compared with the existing memory test array. . In addition, compared with the conventional memory test array, the memory test array with shared conductive pads of the present disclosure can effectively save the area of the memory test chip. The memory test array of the present disclosure can include a memory multi-element array and a common conductive pad at the same time, which will have the advantages described above.

Although the content of this disclosure has been disclosed in the above manner, it is not intended to limit the content of this disclosure. Anyone familiar with the art can make various changes and modifications without departing from the spirit and scope of the content of this disclosure. Therefore, the protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

A memory element array, characterized in that it comprises:

Multiple bit lines;

A plurality of word lines, interlaced with the bit lines and electrically insulated; and

A plurality of transistors, each including a source/drain and a gate, the source/drain of each transistor is electrically connected to one of the bit lines, and the gate is electrically connected to one of the word lines One,

Wherein, at least two of the gates of the transistors have different lengths.
4. The memory device array of claim 1, wherein at least two of the gates of the transistors have different widths.
4. The memory device array of claim 1, wherein one of the bit lines further comprises a phase change memory device.
4. The memory device array of claim 1, wherein at least two of the bit lines further comprise a phase change memory device.
4. The memory device array of claim 1, wherein each of the bit lines further comprises a phase change memory device.
The memory element array of claim 4 or 5, wherein the phase change memory elements each comprise a heater and a phase change material layer, the phase change material layer is located above the heater and has At least two of the areas of a cross section contacting the heater have different sizes.
7. The memory device array of claim 6, wherein at least two of the phase change material layers have different thicknesses.
4. The memory device array of claim 1, further comprising:

A wire electrically connects two of the word lines.