CN108172619B - Semiconductor device with a plurality of transistors - Google Patents
Semiconductor device with a plurality of transistors Download PDFInfo
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- CN108172619B CN108172619B CN201711454308.3A CN201711454308A CN108172619B CN 108172619 B CN108172619 B CN 108172619B CN 201711454308 A CN201711454308 A CN 201711454308A CN 108172619 B CN108172619 B CN 108172619B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 230000003071 parasitic effect Effects 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 42
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
- H01L29/7818—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
Abstract
In the technical scheme of the invention, when a negative voltage pulse is input to the second N-type ring, in a loop between the second N-type ring and the second P-type ring, because the orthographic projection of the outer edge of the N-type buried layer on the P-type substrate covers the orthographic projection of the inner edge of the second P-type ring on the P-type substrate, and the doping concentration of the N-type buried layer is greater than that of the P-type doping region, the resistance in an equivalent circuit can be reduced, more power is distributed to a parasitic diode, and the characteristic that the parasitic diode can bear higher power is utilized, so that the input end of the semiconductor device can bear higher negative surge voltage.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device.
Background
With the continuous development of science and technology, more and more electronic devices are widely applied to daily life and work of people, bring great convenience to the daily life and work of people, and become an indispensable important tool for people at present.
The main control center of electronic equipment for realizing various functions is an integrated circuit, and various types of semiconductor devices are important units constituting the integrated circuit. The surge phenomenon easily occurs in the integrated circuit, and instantaneous overvoltage exceeding the normal working voltage of the device is generated, namely, larger surge voltage is generated. The surge phenomenon is characterized by a very short generation time, typically in the order of microseconds. When a surge occurs, the magnitude of the voltage and current may be many times the normal value. The surge phenomenon occurs due to various reasons, such as lightning strike, electrostatic discharge, industrial events, and switching on and off operations on a high voltage power line.
Surge phenomena have catastrophic hazards including: the larger surge voltage exceeds the bearing capacity of the semiconductor device, and the semiconductor device is directly burnt; its cumulative hazards include: the multiple small surge accumulation effects can cause degradation in the performance of the semiconductor device, resulting in a reduction in the lifetime of the semiconductor device. In the existing semiconductor device, the capability of bearing negative surge voltage is weaker, and the application range of the semiconductor device is limited. Therefore, how to improve the capability of the semiconductor device to bear negative surge voltage is a problem to be solved urgently in the technical field of semiconductors.
Disclosure of Invention
In order to solve the above problem, the present invention provides a semiconductor device capable of withstanding a high negative surge voltage.
In order to achieve the above purpose, the invention provides the following technical scheme:
a semiconductor device, the semiconductor device comprising:
front and back structures opposing each other in the longitudinal direction;
in a plane perpendicular to the longitudinal direction, the frontal structure comprises: a functional region; a first N-type ring surrounding the functional region; a first P-type ring surrounding the first N-type ring; a second N-type ring surrounding the first P-type ring; and a second P-type ring surrounding the second N-type ring; a shallow groove isolation ring is arranged between the adjacent N-type ring and the adjacent P-type ring;
the back structure comprises a P-type substrate and an N-type buried layer positioned on the surface of one side, facing the front structure, of the P-type substrate;
in the longitudinal direction, the orthographic projection of the outer edge of the N-type buried layer on the P-type substrate covers the orthographic projection of the inner edge of the second P-type ring on the P-type substrate;
an N-type doped region is arranged between the second N-type ring and the N-type buried layer; p-type doped regions are arranged between the first P-type ring and the N-type buried layer and between the second P-type ring and the N-type buried layer; the doping concentration of the N-type buried layer is greater than that of the P-type doping region.
Preferably, in the semiconductor device, in the longitudinal direction, an orthogonal projection of the outer edge of the N-type buried layer on the P-type substrate coincides with an orthogonal projection of the outer edge of the second P-type ring on the P-type substrate, or the orthogonal projection of the outer edge of the N-type buried layer on the P-type substrate is located between an orthogonal projection of the inner edge of the second P-type ring on the P-type substrate and an orthogonal projection of the outer edge of the second P-type ring on the P-type substrate.
Preferably, in the above semiconductor device, the second P-type ring is electrically connected to a ground terminal for grounding, and the second N-type ring is connected to an input terminal for inputting a predetermined input voltage.
Preferably, in the above semiconductor device, the preset voltage includes a negative voltage pulse;
the equivalent circuit between the ground terminal and the input terminal includes: the first branch circuit and the second branch circuit are connected in parallel;
the first branch includes: a first resistor, a first parasitic diode, a second resistor and a third resistor which are sequentially connected in series between the grounding end and the input end; the first resistor is a longitudinal equivalent resistor of a P-type doped region between the second P-type ring and the N-type buried layer; the first parasitic diode is a parasitic diode between the P-type doped region and the N-type buried layer; the second resistor is a transverse resistor of the N-type buried layer in a first region, and a part of the N-type buried layer, which is just opposite to a region between the outer side of the second P-type ring and the inner side of the second N-type ring, is the first region; the third resistor is a longitudinal equivalent resistor of an N-type doped region between the second N-type ring and the N-type buried layer;
the second branch circuit includes: a fourth resistor, a fifth resistor, a second parasitic diode, a sixth resistor and a seventh resistor which are sequentially connected in series between the grounding end and the input end; the fourth resistor is a longitudinal resistor of the P-type doped region at the part below the second P-type ring; the fifth resistor is a transverse equivalent resistor of the P-type doped region; the second parasitic diode is a parasitic diode between the P-type doped region and the adjacent N-type doped region; the sixth resistor is a transverse equivalent resistor of the N-type doped region; the seventh resistor is a longitudinal resistor of the N-type doped region at the lower part of the second N-type ring.
Preferably, in the semiconductor device, the N-type buried layer and the second N-type ring are electrically connected through an N-type doped region located therebetween.
Preferably, in the semiconductor device, the P-type substrate and the second P-type ring are electrically connected through the P-type doped region and the N-type buried layer therebetween.
Preferably, in the above semiconductor device, the semiconductor device is an LDMOS device; the functional region corresponds to the central region of the N-type buried layer; the functional region includes: the source region, surround the grid region of the said source region and surround the drain region of the said grid region; the first N ring is positioned in the surface of the drain region and is connected with the drain electrode; the grid region is connected with the grid electrode; the source region is connected with the source electrode.
As can be seen from the above description, the semiconductor device according to the present invention includes: front and back structures opposing each other in the longitudinal direction; in a plane perpendicular to the longitudinal direction, the frontal structure comprises: a functional region; a first N-type ring surrounding the functional region; a first P-type ring surrounding the first N-type ring; a second N-type ring surrounding the first P-type ring; and a second P-type ring surrounding the second N-type ring; a shallow groove isolation ring is arranged between the adjacent N-type ring and the adjacent P-type ring; the back structure comprises a P-type substrate and an N-type buried layer positioned on the surface of one side, facing the front structure, of the P-type substrate; in the longitudinal direction, the orthographic projection of the outer edge of the N-type buried layer on the P-type substrate covers the orthographic projection of the inner edge of the second P-type ring on the P-type substrate; n-type doped regions are arranged between the first N-type ring and the second N-type ring and the N-type buried layer; p-type doped regions are arranged between the first P-type ring and the N-type buried layer and between the second P-type ring and the N-type buried layer; the doping concentration of the N-type buried layer is greater than that of the P-type doping region.
Therefore, when a negative voltage pulse is input to the second N-type ring, in a loop between the second N-type ring and the second P-type ring, because the orthographic projection of the outer edge of the N-type buried layer on the P-type substrate covers the orthographic projection of the inner edge of the second P-type ring on the P-type substrate, and the doping concentration of the N-type buried layer is greater than that of the P-type doping region, the resistance in an equivalent circuit can be reduced, more power is distributed to the parasitic diode, and the characteristic that the parasitic diode can bear higher power is utilized, so that the input end of the semiconductor device can bear higher negative surge voltage.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of an LDMOS structure;
fig. 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a first branch of an equivalent circuit in the semiconductor device shown in fig. 1;
fig. 4 is a schematic diagram of a second branch of the equivalent circuit in the semiconductor device of fig. 1;
fig. 5 is a schematic structural diagram of an LDMOS provided in an embodiment of the invention;
fig. 6 is an equivalent circuit diagram of a first branch circuit in the semiconductor device according to the embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background art, the conventional semiconductor device has a poor capability of withstanding negative pulse energy, and an LDMOS (laterally double-diffused metal oxide semiconductor) device is taken as an example for description.
The LDMOS has a planar structure due to the balanced characteristics of the LDMOS in both the on-resistance (Rdson) and the drain-source breakdown voltage (BVdss), is easy to be compatible with a large-scale integrated circuit, has stable performance and is easy to realize, so the LDMOS is widely applied to power switching tubes in analog chips integrated by various high-voltage and low-voltage devices.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an LDMOS, a back structure of the LDMOS includes a P-type substrate 10 and an N-type buried layer 11 located on a surface of the P-type substrate 10, and a front structure of the LDMOS includes: a first N-type ring 12 surrounding the functional region, a first P-type ring 14 surrounding the first N-type ring 12, a second N-type ring 15 surrounding the second P-type ring 14, and a second P-type ring 13 surrounding the second N-type ring 15.
Generally, the second N-type ring 15 is connected to the input terminal for inputting the predetermined input voltage VIN, the second P-type ring 13 is connected to the ground terminal, the input terminal is connected to the input terminal, and the ground terminal is connected to the ground terminal, so that a loop is formed between the second P-type ring 13 and the second N-type ring 15. In the LDMOS device shown in fig. 1, the ability to withstand negative-going pulse energy is poor.
In order to solve the above problem, an embodiment of the present invention provides a semiconductor device, where a corresponding position of an N-type buried layer with respect to a second P-type ring is set, a power distribution ratio of a parasitic diode is increased in a loop between the second N-type ring and the second P-type ring, the power distribution ratio of an equivalent resistance is reduced, and a characteristic that the parasitic diode can bear higher power is utilized, so that the semiconductor device can bear higher negative surge voltage.
The foregoing is the core concept of the present invention, and the following is a more detailed description of the present invention with reference to the accompanying drawings and detailed description so that the above objects, features and advantages of the present invention can be more clearly understood.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention, where the semiconductor device includes: a front structure and a back structure opposing each other in the longitudinal direction.
In a plane perpendicular to the longitudinal direction, the frontal structure comprises: a functional region; a first N-type ring 22 surrounding the functional region; a first P-type ring 24 surrounding the first N-type ring 22; a second N-type ring 25 surrounding the first P-type ring 24; and a second P-type ring 23 surrounding the second N-type ring 25.
The back structure comprises a P-type substrate 20 and an N-type buried layer 21 located on one side surface of the P-type substrate 20 facing the front structure.
A shallow trench isolation ring 26 is provided between the adjacent N-type ring and P-type ring, specifically, as shown in fig. 1, a shallow trench isolation ring 26 is provided between the first N-type ring 22 and the first P-type ring 24, a shallow trench isolation ring 26 is provided between the first P-type ring 24 and the second N-type ring 25, and a shallow trench isolation ring 26 is provided between the second N-type ring 25 and the second P-type ring 23.
An N-type doped region 29 is formed between the second N-type ring 25 and the N-type buried layer 21. The first P-type ring 24 and the second P-type ring 23 are P-type doped regions with the N-type buried layer 21, a P-type doped region 27 is provided between the first P-type ring 24 and the N-type buried layer 21, and a P-type doped region 28 is provided between the second P-type ring 23 and the N-type buried layer 21. The doping concentrations of the P-type doped region 27 and the P-type doped region 28 are the same. The doping concentration of the N-type buried layer 21 is greater than that of the P-type doped region.
In the longitudinal direction, the orthographic projection of the outer edge of the N-type buried layer 21 on the P-type substrate 20 covers the orthographic projection of the inner edge of the second P-type ring 23 on the P-type substrate 20, so that in the branch of the second P-type ring 23-the second P-type doped region 28-the N-type buried layer 21-the N-type doped region 29-the second N-type ring 25, the equivalent resistance is reduced, the power distribution of a parasitic diode is increased, and the power distribution of the equivalent resistance is reduced.
Optionally, in the longitudinal direction, an orthogonal projection of the outer edge of the N-type buried layer 21 on the P-type substrate 20 coincides with an orthogonal projection of the outer edge of the second P-type ring 23 on the P-type substrate 20, or the orthogonal projection of the outer edge of the N-type buried layer 21 on the P-type substrate 20 is located between an orthogonal projection of the inner edge of the second P-type ring 23 on the P-type substrate 20 and an orthogonal projection of the outer edge of the second P-type ring 23 on the P-type substrate 20, so that the equivalent resistance of the branch is minimized.
The second P-type ring 23 is electrically connected to a ground GND for grounding, and the second N-type ring 25 is connected to an input terminal VIN for inputting a predetermined input voltage. Generally, the input voltage may be a dc voltage or a negative voltage pulse. Optionally, in the embodiment of the present invention, the preset voltage includes a negative voltage pulse, and when the negative voltage pulse is input, the semiconductor device may bear a higher negative surge voltage due to the increase of the power distribution ratio of the parasitic diode.
The equivalent circuit between the ground terminal GND and the input terminal VIN includes: the first branch and the second branch are connected in parallel.
Referring to fig. 3, fig. 3 is a schematic diagram of a first branch of an equivalent circuit in the semiconductor device shown in fig. 1, the first branch including: a first resistor R1, a first parasitic diode D1, a second resistor R2 and a third resistor R3 connected in series between the ground GND and the input terminal VIN.
The first resistor R1 is a vertical equivalent resistance of the P-type doped region 28 between the second P-type ring 23 and the N-type buried layer 21. The first parasitic diode D1 is a parasitic diode between the P-type doped region 28 and the N-type buried layer 21. The second resistor R2 is a lateral resistance of the N-type buried layer 23 in the first region a, and a portion of the N-type buried layer 21 directly opposite to the region between the outer side of the second P-type ring 23 and the inner side of the second N-type ring 25 is the first region a; the third resistor R3 is a vertical equivalent resistance of the N-type doped region 29 between the second N-type ring 25 and the N-type buried layer 21. The first branch includes: the ground GND, the second P-type ring 23, the second P-type doped region 28, the buried N-type layer 21, the doped N-type region 29, the second N-type ring 25, and the input VIN.
Referring to fig. 4, fig. 4 is a schematic diagram of a second branch of an equivalent circuit in the semiconductor device shown in fig. 1, the second branch including: a fourth resistor R4, a fifth resistor R5, a second parasitic diode D2, a sixth resistor R6, and a seventh resistor R7, which are sequentially connected in series between the ground terminal GND and the input terminal VIN.
The fourth resistor R4 is a longitudinal resistor of the P-type doped region 28 below the second P-type ring 23; the fifth resistor R5 is the lateral equivalent resistance of the P-type doped region 28; the second parasitic diode D2 is a parasitic diode between the P-type doped region 28 and the adjacent N-type doped region 29; the sixth resistor R6 is the lateral equivalent resistance of the N-type doped region 29. The seventh resistor R7 is a longitudinal resistor of the N-type doped region 29 under the second N-type ring 25. The second branch includes: the ground GND, the second P-type ring 23, the portion of the P-type doped region 28 under the second P-type ring 23, the portion of the N-type doped region 29 under the second N-type ring 25, and the input VIN. It can be seen from the circuit relationship that the fourth resistor R5 is the equivalent resistance of the region from the P-doped region 28 to the N-doped region 29 directly opposite to the second P-type ring 23, and the fifth resistor R6 is the equivalent resistance of the region from the N-doped region 29 to the P-doped region 28 directly opposite to the second N-type ring 25.
Optionally, the N-type buried layer 21 and the second N-type ring 25 are electrically connected through an N-type doped region 29 therebetween. The P-type substrate 20 is electrically connected to the second P-type ring 23 via the P-type doped region 28 and the N-type buried layer 21 therebetween
The following is a detailed description of the principle that the semiconductor device according to the embodiment of the present application can withstand a higher negative surge voltage than the semiconductor device of the conventional structure shown in fig. 1:
in the branch shown in fig. 4, the equivalent resistance and the parasitic diode in the embodiment of the present application are the same as those shown in fig. 1. The second branch circuit has a larger resistance and a smaller shunt compared with the first branch circuit, so that the first branch circuit distributes more power.
In the branch shown in fig. 3, the first resistor R1, the third resistor R3 and the first parasitic diode D1 in the embodiment of the present application are the same as those shown in fig. 1, and the second resistor R2 is different. In the manner shown in fig. 1, second resistor R2 includes at least the lateral equivalent resistance of a partial region of P-type field region 28, whereas second resistor R2 includes only the lateral equivalent resistance of first region a of N-type buried layer 21 in the embodiment of the present application. The embodiment of the application changes the power distribution ratio of the equivalent resistor and the parasitic diode in the branch circuit, so that the branch circuit can bear high-power input by utilizing the parasitic diode with high-power characteristic, and further higher negative surge voltage can be input by the input single VIN.
Since the doping concentration of the N-type buried layer 21 is greater than that of the P-type doped region 28, that is, the resistivity of the N-type buried layer 21 is less than that of the P-type doped region 28. Generally, the doping concentration of the N-type buried layer 21 is two orders of magnitude higher than that of the P-type doped region 28, i.e. at least 100 times higher, and the doping concentration of the N-type buried layer 21 is much higher than that of the P-type doped region 28. The calculation formula of the equivalent resistance is as follows:
it can be seen that the resistance R is proportional to the resistivity ρ and the length L, and inversely proportional to the cross-sectional area S, and when the length L and the cross-sectional area S are constant, the second resistance R2 has a smaller resistivity in the present application compared to the method shown in fig. 1, so that the second resistance R2 is smaller compared to the method shown in fig. 1, and the resistance of the equivalent resistance in the branch is reduced. Therefore, the resistance value of the equivalent resistor is reduced, so that the power distribution ratio of the parasitic diode in the branch is increased, the power distribution ratio of the equivalent resistor is reduced, more power is distributed to the parasitic diode with the characteristic of higher power when the input power is fixed, the branch can bear the characteristic of higher power, and the semiconductor device can bear higher power.
Referring to fig. 6, fig. 6 is an equivalent circuit diagram of a first branch in the semiconductor device according to the embodiment of the present invention, in fig. 6, Rtotal is a parasitic impedance corresponding to the first parasitic diode D1, and Rtotal may be represented as:
Rtotal＝R1+R2+R3
the second P-type ring 23 is grounded, the second N-type ring 25 is connected to the input voltage VIN, and if the input voltage includes a negative surge voltage, the voltage division relationship is as follows:
-VIN＝VD1+VRtotal
wherein, VD1Is the forward voltage drop, V, of the first parasitic diode D1RtotalIs the voltage drop of the parasitic impedance, VRtotalCan be expressed as:
VRtotal＝I*Rtotal
where I is a current flowing from the ground terminal to the input terminal in the first branch, and the current voltage of the first parasitic diode D1 is in an exponential relationship, which can be expressed as:
wherein, I0Represents the reverse saturation current, V, of the first parasitic diode D1TIs the voltage equivalent of temperature and at normal temperature (T300K), VTCan be expressed as:
VT＝kT/q＝0.026V＝26mV
it can be seen that VD1Logarithmic with respect to I, VRtotalRelative to I, the slope is Rtotal, and when I is increased by the same value, V isD1The increase amplitude is less than VRtotalThe amplitude is increased. Therefore, VIN is constant, the smaller Rtotal, the larger I, and the more power the first parasitic diode D1 receives.
The semiconductor device provided by the embodiment of the invention is suitable for a power switch tube with a larger channel width-length ratio. Therefore, the layout area of the semiconductor device is large, and the sectional area of the parasitic diode is large, so that the purposes of increasing the power distribution ratio of the parasitic diode and reducing the power distribution ratio of the equivalent resistor are achieved.
Experiments show that the semiconductor device in the mode shown in FIG. 1 can only bear the pulse voltage of-60V, but the semiconductor device in the embodiment of the application can bear the pulse voltage of-100V, and can bear higher negative pulse energy compared with the mode shown in FIG. 1.
According to the embodiment of the invention, the characteristic that the parasitic diode has higher power is utilized, so that the semiconductor device can bear higher power.
When the semiconductor device is an LDMOS, the semiconductor device is as shown in fig. 5, and fig. 5 is a schematic structural diagram of an LDMOS provided in an embodiment of the present invention, at this time, the functional region corresponds to a central region of the N-type buried layer; the functional region includes: a source region surrounding a gate region of the source region; and a drain region surrounding the gate region; the first N ring 22 is positioned in the surface of the Drain region and is connected with a Drain Drain; the grid region is connected with a grid Gate; the Source region is connected with the Source. The first P-type ring 24 is connected to the Source, and both are at the same potential.
The surface of the buried N-type layer 21 has a deep P-well region 30, and the P-doped region 27 surrounds the deep P-well region 30. The surface of the deep P-well region 30 has an N-doped drain 31, and the P-doped region 27 surrounds the N-doped drain 31. A P-well region 32 is disposed in a central region of the upper surface of the N-type doped drain terminal 31, and the P-well region 32 is located in the upper surface of the N-type doped drain terminal 31. An N-type well region 33 is disposed in a central region of the upper surface of the P-well region 32, and the N-type well region 33 is located in the upper surface of the P-well region 32. The N-well 33 serves as a Source region and is connected to the Source. The Gate is located on the surface of the P-well region 32, covering a part of the P-well region 32 and a part of the N-type doped drain terminal 31.
It should be noted that the semiconductor device in the embodiment of the present application includes, but is not limited to, an LDMOS. In the technical scheme of the embodiment of the invention, only the LDMOS is taken as an example to explain that in the semiconductor device of the technical scheme of the invention, the power distribution ratio of the parasitic diode at a specific position can be increased by increasing the range of the N-type buried layer in the semiconductor device, and the parasitic diode in the multiplexing semiconductor device can bear higher power so as to increase the negative surge voltage of the semiconductor device.
As can be seen from the above description, in the semiconductor device according to the embodiment of the present application, when a negative voltage pulse is input to the second N-type ring, in a loop between the second N-type ring and the second P-type ring, since an orthographic projection of an outer edge of the N-type buried layer on the P-type substrate covers an orthographic projection of an inner edge of the second P-type ring on the P-type substrate, and a doping concentration of the N-type buried layer is greater than a doping concentration of the P-type doping region, a resistance in an equivalent circuit can be reduced, so that more power is distributed to the parasitic diode, and a characteristic that the parasitic diode can bear higher power is utilized, so that an input end of the semiconductor device can bear higher surge negative voltage.
While the foregoing description of the embodiments of the invention has been set forth in considerable detail for the purposes of making a thorough understanding of the invention, the invention may be embodied in other forms than those described and the invention may be practiced by those skilled in the art without departing from the spirit and scope of the invention, and it is not intended to be limited to the specific embodiments disclosed below.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (7)
1. A semiconductor device, characterized in that the semiconductor device comprises:
front and back structures opposing each other in the longitudinal direction;
in a plane perpendicular to the longitudinal direction, the frontal structure comprises: a functional region; a first N-type ring surrounding the functional region; a first P-type ring surrounding the first N-type ring; a second N-type ring surrounding the first P-type ring; and a second P-type ring surrounding the second N-type ring; a shallow groove isolation ring is arranged between the adjacent N-type ring and the adjacent P-type ring;
the back structure comprises a P-type substrate and an N-type buried layer positioned on the surface of one side, facing the front structure, of the P-type substrate;
in the longitudinal direction, the orthographic projection of the outer edge of the N-type buried layer on the P-type substrate covers the orthographic projection of the inner edge of the second P-type ring on the P-type substrate;
an N-type doped region is arranged between the second N-type ring and the N-type buried layer; p-type doped regions are arranged between the first P-type ring and the N-type buried layer and between the second P-type ring and the N-type buried layer; the doping concentration of the N-type buried layer is greater than that of the P-type doping region.
2. The semiconductor device according to claim 1, wherein in a longitudinal direction, an orthogonal projection of an outer edge of the N-type buried layer on the P-type substrate coincides with an orthogonal projection of an outer edge of the second P-type ring on the P-type substrate, or wherein an orthogonal projection of an outer edge of the N-type buried layer on the P-type substrate is located between an orthogonal projection of an inner edge of the second P-type ring on the P-type substrate and an orthogonal projection of an outer edge of the second P-type ring on the P-type substrate.
3. The semiconductor device according to claim 1, wherein the second P-type ring is electrically connected to a ground terminal for grounding, and wherein the second N-type ring is connected to an input terminal for inputting a predetermined input voltage.
4. The semiconductor device according to claim 3, wherein the preset voltage comprises a negative voltage pulse;
the equivalent circuit between the ground terminal and the input terminal includes: the first branch circuit and the second branch circuit are connected in parallel;
the first branch includes: a first resistor, a first parasitic diode, a second resistor and a third resistor which are sequentially connected in series between the grounding end and the input end; the first resistor is a longitudinal equivalent resistor of a P-type doped region between the second P-type ring and the N-type buried layer; the first parasitic diode is a parasitic diode between the P-type doped region and the N-type buried layer; the second resistor is a transverse resistor of the N-type buried layer in a first region, and a part of the N-type buried layer, which is just opposite to a region between the outer side of the second P-type ring and the inner side of the second N-type ring, is the first region; the third resistor is a longitudinal equivalent resistor of an N-type doped region between the second N-type ring and the N-type buried layer;
the second branch circuit includes: a fourth resistor, a fifth resistor, a second parasitic diode, a sixth resistor and a seventh resistor which are sequentially connected in series between the grounding end and the input end; the fourth resistor is a longitudinal resistor of the P-type doped region at the part below the second P-type ring; the fifth resistor is a transverse equivalent resistor of the P-type doped region; the second parasitic diode is a parasitic diode between the P-type doped region and the adjacent N-type doped region; the sixth resistor is a transverse equivalent resistor of the N-type doped region; the seventh resistor is a longitudinal resistor of the N-type doped region at the lower part of the second N-type ring.
5. The semiconductor device of claim 1, wherein the buried N-type layer is electrically connected to the second N-type ring by an N-type doped region therebetween.
6. The semiconductor device of claim 1, wherein the P-type substrate is electrically connected to the second P-type ring by a P-type doped region and an N-type buried layer therebetween.
7. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device is an LDMOS device; the functional region corresponds to the central region of the N-type buried layer; the functional region includes: the source region, surround the grid region of the said source region and surround the drain region of the said grid region; the first N ring is positioned in the surface of the drain region and is connected with the drain electrode; the grid region is connected with the grid electrode; the source region is connected with the source electrode.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288424B1 (en) * | 1998-09-23 | 2001-09-11 | U.S. Philips Corporation | Semiconductor device having LDMOS transistors and a screening layer |
| CN101931004A (en) * | 2009-06-22 | 2010-12-29 | 宏海微电子股份有限公司 | Structure of transverse diffusion metal oxide semiconductor field effect transistor |
| CN104617143A (en) * | 2015-01-05 | 2015-05-13 | 无锡友达电子有限公司 | P type transverse double-dispersion MOS pipe capable of reducing conduction resistance |
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| JP6296535B2 (en) * | 2013-12-09 | 2018-03-20 | ローム株式会社 | Diode and signal output circuit including the same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288424B1 (en) * | 1998-09-23 | 2001-09-11 | U.S. Philips Corporation | Semiconductor device having LDMOS transistors and a screening layer |
| CN101931004A (en) * | 2009-06-22 | 2010-12-29 | 宏海微电子股份有限公司 | Structure of transverse diffusion metal oxide semiconductor field effect transistor |
| CN104617143A (en) * | 2015-01-05 | 2015-05-13 | 无锡友达电子有限公司 | P type transverse double-dispersion MOS pipe capable of reducing conduction resistance |
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