CN115954343B - Gate oxide layer test structure - Google Patents
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- CN115954343B CN115954343B CN202310219503.7A CN202310219503A CN115954343B CN 115954343 B CN115954343 B CN 115954343B CN 202310219503 A CN202310219503 A CN 202310219503A CN 115954343 B CN115954343 B CN 115954343B
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Abstract
The invention provides a gate oxide layer test structure, which comprises: a substrate comprising a device region and a dummy region, the dummy region being located at an edge of the device region, a plurality of isolation structures being formed within the substrate, and an active region defined by the isolation structures; a gate oxide layer on the substrate, and a gate electrode on the gate oxide layer; the device region is connected with the gate oxide layer in the virtual region in parallel. According to the invention, the device region and the gate oxide layer in the virtual region are connected in parallel, so that the detection area of the gate oxide layer is increased, the breakdown voltage of the gate oxide layer is effectively monitored, the WAT detection capability is improved, the process problem can be better reflected, and the customer complaint is reduced.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a gate oxide layer test structure.
Background
In the process of manufacturing a semiconductor device, in order to monitor the manufacturing process and ensure the reliability of the semiconductor device, it is common practice to form a test key (test key) in the device for testing some key parameters. In CMOS processes, the gate oxide (gate oxide) is an important component of the device structure, and should be an ideal dielectric layer without defects affecting its insulating properties. However, factors such as ion diffusion intrusion, charge trapping, etc., affect the quality of the gate oxide during the fabrication process. Therefore, a reliability test is required for the gate oxide layer.
Common parameters for detecting the reliability of the gate oxide include BVox (oxide breakdown voltage ), tox (oxide thickness), etc., and the quality of the gate oxide is determined by these parameters. However, in general, factors such as particle defect, ion implantation damage, gate oxide thickness, etc. affect the performance of the above parameters, that is, the size of the parameters also affects various factors.
Before the semiconductor device is manufactured and shipped, a Wafer Acceptance Test (WAT) is performed to test the electrical properties of the test structures on the scribe lines. The gate oxide is electrically tested, for example, by a gate oxide test structure. However, some anomalies are undetectable. For example: according to the Failure Analysis (FA) result of defective products, pinholes (pin holes) are found at the gate oxide layer of the IC capacitor region, and the pre-cleaning (pre-cleaning) capability of the locked gate oxide layer is poor, namely, the defects occur at the gate oxide layer pre-cleaning station. But the defect is not detected because the defect size exceeds the detection capability of the factory.
Disclosure of Invention
The invention aims to provide a gate oxide layer test structure which can improve the WAT detection capability and can more effectively reflect the processing problem.
In order to solve the above technical problems, the present invention provides a gate oxide layer test structure, including:
a substrate comprising a device region and a dummy region, the dummy region being located at an edge of the device region, a plurality of isolation structures being formed within the substrate, and an active region defined by the isolation structures;
a gate oxide layer on the substrate, and a gate electrode on the gate oxide layer;
the device region is connected with the gate oxide layer in the virtual region in parallel.
Optionally, the gate oxide layer test structure further includes a metal interconnection structure, in the device region and the dummy region, the top of the active region is connected to a first bonding pad through the metal interconnection structure, and the top of the gate is connected to a second bonding pad through the metal interconnection structure.
Optionally, the metal interconnection structure includes an active region first metal layer, an active region second metal layer, an active region first metal plug and an active region second metal plug; in the device region and the virtual region, the top of the active region is connected with the active region first metal layer through the active region first metal plug, the active region first metal layer is connected with the active region second metal layer through the active region second metal plug, and the active region second metal layers connected with all the active regions are connected with each other and the first welding pad.
Optionally, the metal interconnection structure further includes an active region third metal layer and an active region third metal plug; the active region second metal layer is connected with the active region third metal layer through the active region third metal plug, and the active region third metal layer is connected to the first welding pad.
Optionally, the metal interconnection structure further includes a gate first metal layer and a gate first metal plug; in the device region and the dummy region, the top of the gate is connected to the gate first metal layer through the gate first metal plug, and the gate first metal layers connected to all the gates are connected to each other and to the second pad.
Optionally, the metal interconnection structure further includes a gate second metal layer, a gate third metal layer, a gate second metal plug, and a gate third metal plug; the first metal layer of the grid is connected with the second metal layer of the grid through the second metal plug of the grid, the second metal layer of the grid is connected with the third metal layer of the grid through the third metal plug of the grid, and the third metal layer of the grid is connected to the second welding pad.
Optionally, the virtual area is located at two sides of the device area; or the virtual area is positioned around the device area.
Optionally, in the virtual area, the size of the gate is smaller than the size of the active area in the first direction, and in the second direction, the size of the gate is larger than the size of the active area; the first direction is perpendicular to the second direction, and a plane formed by the first direction and the second direction is parallel to the substrate.
Optionally, in the first direction, the dimension of the active region is 2 μm±0.01 μm, and the dimension of the gate is 1.8 μm±0.006 μm; in the second direction, the size of the active region is 1 μm.+ -. 0.01 μm, and the size of the gate is 1.2 μm.+ -. 0.006 μm.
Optionally, in the first direction, a spacing between adjacent active regions is 1.4 μm±0.01 μm; in the second direction, a spacing between adjacent active regions is 1.4 μm±0.01 μm;
the edges of the active regions adjacent in the first direction are spaced apart from each other by 0 μm±0.01 μm in the second direction; the edges of the active regions adjacent in the second direction are spaced apart from each other by 0.8 μm + -0.01 μm in the first direction.
In the gate oxide layer test structure provided by the invention, the device area is connected with the gate oxide layer in the virtual area in parallel, so that the detection area of the gate oxide layer is increased, the breakdown voltage of the gate oxide layer is effectively monitored, the detection capability of WAT is improved, the process problem can be better reflected, and the customer complaint is reduced.
In addition, in the existing test structure, the virtual area and the gate oxide layer in the virtual area exist, so that only the device area and the gate oxide layer in the virtual area are connected in parallel, namely, only the existing test structure is required to be slightly modified, and the method is simple and convenient to operate.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation on the scope of the invention.
FIG. 1 is a schematic cross-sectional view of a gate oxide test structure.
Fig. 2 is a top view of fig. 1 at AA'.
Fig. 3 is a top view of fig. 1 at BB'.
Fig. 4 is a top view of fig. 1 at CC'.
Fig. 5 is a schematic diagram of a positional relationship between an active region and a gate in the virtual region shown in fig. 1.
Fig. 6 is a schematic diagram showing a connection relationship of pads when performing a breakdown voltage test on a gate oxide test structure in an embodiment.
Fig. 7 is a schematic diagram showing a connection relationship of pads when performing a breakdown voltage test on a gate oxide test structure according to another embodiment.
Fig. 8 is a schematic cross-sectional view of a gate oxide test structure according to an embodiment of the invention.
Fig. 9 is a top view of fig. 8 at AA'.
Fig. 10 is a top view of fig. 8 at BB'.
Fig. 11 is a top view of fig. 8 at CC'.
Fig. 12 is a schematic diagram of a positional relationship between an active region and a gate electrode in the virtual region shown in fig. 8.
Reference numerals:
in fig. 1 to 7:
11-isolation structures; 12-an active region; 13-gate oxide; 14-grid electrode; 15-virtual metal; a 20-metal interconnect structure; 211-an active region first metal layer; 212-an active region second metal layer; 213-an active region third metal layer; 221-gate first metal layer; 222-gate second metal layer; 223-gate third metal layer; 231-an active region first metal plug; 232-an active region second metal plug; 233-an active region third metal plug; 241-gate first metal plug; 242-gate second metal plug; 243-a gate third metal plug; 31-a first bonding pad; 32-a second bonding pad; 33-a third bonding pad; 34-fourth bond pads.
Fig. 8 to 12:
110-isolation structures; 120-active region; 130-gate oxide; 140-grid electrode; 150-virtual metal; 200-metal interconnect structure; 2110-an active region first metal layer; 2120-an active region second metal layer; 2130—an active area third metal layer; 2210-a gate first metal layer; 2220—a gate second metal layer; 2230-gate third metal layer; 2310-an active area first metal plug; 2320-an active region second metal plug; 2330-an active region third metal plug; 2410-gate first metal plug; 2420-a gate second metal plug; 2430-gate third metal plug.
Detailed Description
FIG. 1 is a schematic cross-sectional view of a gate oxide test structure. Referring to fig. 1, the gate oxide layer test structure includes a substrate, wherein the substrate includes a device region I and a dummy region II, and the dummy region II is located at an edge of the device region I. The virtual area II can be located at two sides of the device area I, can also be located at the periphery of the device area II, and can be determined by the size of the device area I and actual requirements. A plurality of isolation structures 11 and a plurality of active regions 12 defined by a plurality of the isolation structures 11 are formed within the substrate. In this embodiment, one active region 12 is defined in the device region I, and a plurality of active regions 12 are defined in the virtual region II.
A gate oxide layer 13 is formed on the substrate, and the upper surface of the gate oxide layer 13 is flush with the upper surface of the isolation structure 11. A gate electrode 14 is formed on the gate oxide layer 13. A metal interconnection structure 20 is formed on the gate oxide 13 and the gate 14, the top of the active region 12 (i.e., the bottom of the gate oxide 13) in the device region I is connected to a first pad through the metal interconnection structure 20, and the top of the gate 14 in the device region I is connected to a second pad through the metal interconnection structure 20. The gate oxide layer 13 in the dummy region II is not connected to the bonding pad, i.e. does not participate in the test, and the structures such as the gate oxide layer 13 and the gate electrode 14 are formed in the dummy region II only for maintaining the consistency of the pattern density on the substrate.
Fig. 2 is a top view of fig. 1 at AA ', fig. 3 is a top view of fig. 1 at BB ', and fig. 4 is a top view of fig. 1 at CC '. Referring to fig. 1 to 4, in the present embodiment, the metal interconnection structure 20 includes an active region first metal layer 211, an active region second metal layer 212, and an active region third metal layer 213, and an active region first metal plug 231, an active region second metal plug 232, and an active region third metal plug 233, which are connected to the active region 12. The metal interconnection structure 20 further includes a gate first metal layer 221, a gate second metal layer 222, and a gate third metal layer 223 connected to the gate 14, and a gate first metal plug 241, a gate second metal plug 242, and a gate third metal plug 243. The active region first metal layer 211 and the gate first metal layer 221 are located on the same layer, the active region second metal layer 212 and the gate second metal layer 222 are located on the same layer, and the active region third metal layer 213 and the gate third metal layer 223 are located on the same layer, which are named differently for convenience in distinguishing whether they are connected to the active region 12 or the gate 14.
The top of the active region 12 is connected to the active region first metal layer 211 through the active region first metal plug 231, the active region first metal layer 211 is connected to the active region second metal layer 212 through the active region second metal plug 232, and the active region second metal layer 212 is connected to a first pad. The active region second metal layer 212 may also be connected to the active region third metal layer 213 through the active region third metal plug 233, the active region third metal layer 213 being connected to the first pad.
The top of the gate 14 is connected to the gate first metal layer 221 through the gate first metal plug 241, and the gate first metal layer 221 is connected to a second pad. The gate first metal layer 221 may be further connected to the gate second metal layer 222 through the gate second metal plug 242, the gate second metal layer 222 is connected to the gate third metal layer 223 through the gate third metal plug 243, and the gate third metal layer 223 is connected to the second pad. It is understood that the number of layers of the metal included in the metal interconnection structure 20 is not limited to the three layers shown in fig. 1, but may be two or more layers. The metal interconnect structure 20 further has an interlayer dielectric layer formed between adjacent metal layers and between the metal layers and the gate 14, and a metal plug is disposed in the interlayer dielectric layer to communicate with the adjacent metal layers.
As shown in fig. 2 and 1, in the device region I, the gate first metal plug 241 is formed on the gate 14, and the active region first metal plug 231 is formed on the active region 12. In the dummy region II, no metal plug is formed on the gate 14 and the active region 12.
As shown in fig. 3 and fig. 1, in the device region I, the gate first metal layer 221 connected to the gate first metal plugs 241 is integral, i.e. the gate first metal layers 221 connected to the gate first metal plugs 241 are connected to each other and extend to the dummy region II, and a plurality of gate second metal plugs 242 are formed thereon to be finally connected to the second pads. A plurality of the active region second metal plugs 232 are formed on the active region first metal layer 211 connected to the active region first metal plugs 231.
As shown in fig. 4 and fig. 1, in the device region I, the active region second metal layer 212 connected to the active region second metal plugs 232 is integral, i.e. the active region second metal layers 212 connected to the active region second metal plugs 232 are connected to each other and extend into the dummy region II on the other side, and a plurality of active region third metal plugs 233 are formed thereon to be finally connected to the first pads. In the dummy region II on the other side, a plurality of gate third metal plugs 243 are formed on the gate second metal layer 222 connected to the gate second metal plugs 242 to finally connect to the second pads.
It should be noted that, in fig. 3 and 4, the dummy metal 15 is a metal frame that is connected end to end, and the purpose of the dummy metal 15 is to maintain uniformity of flatness or pattern density of the entire substrate, and the dummy metal 15 does not participate in the test.
Fig. 5 is a schematic diagram of a positional relationship between an active region and a gate in the virtual region shown in fig. 1. Referring to fig. 5, in the virtual area II, the dimensions of the active areas 12 are kept uniform, the dimensions of the gates 14 are also kept uniform, and the distances between adjacent active areas 12 are also kept uniform, i.e., the active areas 12 are regularly arranged in the virtual area II. In this embodiment, the dimension L1 of the active region 12 in the horizontal direction is 2 μm±0.01 μm, and the dimension L2 of the gate 14 in the horizontal direction is 2.2 μm±0.006 μm, i.e., the dimension of the gate 14 in the horizontal direction is larger than the dimension of the active region 12. The dimension L3 of the active region 12 in the vertical direction is 1 μm±0.01 μm, and the dimension L4 of the gate 14 in the vertical direction is 1.2 μm±0.006 μm, i.e., the dimension of the gate 14 in the vertical direction is also larger than the dimension of the active region 12. The horizontal direction and the vertical direction are the horizontal direction and the vertical direction in fig. 5 respectively, the horizontal direction is perpendicular to the vertical direction, a plane formed by the horizontal direction and the vertical direction is parallel to the substrate, and the horizontal direction is consistent with the horizontal direction in fig. 1. In the horizontal direction, the pitch L5 between adjacent active regions 12 is 1.4 μm±0.01 μm; in the vertical direction, the pitch L6 between adjacent active regions 12 is 1.4 μm±0.01 μm. And, a spacing L7 of edges of two of the active regions 12 adjacent in the horizontal direction in the vertical direction is 0±0.01 μm, and a spacing L8 of edges of two of the active regions 12 adjacent in the vertical direction in the horizontal direction is 0.8 μm±0.01 μm.
In this embodiment, the breakdown voltage of the gate oxide layer 13 may be tested by applying different voltages to the first pad and the second pad. Fig. 6 is a schematic diagram showing a connection relationship of pads when performing a breakdown voltage test on a gate oxide test structure in an embodiment. Referring to fig. 6, the first bonding pad 31 is finally connected to the active region 12 through a plurality of the third metal plugs 233, and the second bonding pad 32 is finally connected to the gate 14 through a plurality of the third metal plugs 243. A high voltage (V) can be applied to the first pad 31 High ) A low voltage (V is applied to the second pad 32 Low ) To measure the breakdown voltage of the gate oxide 13. At this time, the area of the gate oxide layer 13 is the area between the first bonding pad 31 and the second bonding pad 32, and referring to the dimension shown in fig. 5, the area of the gate oxide layer 13 may be 3150 μm 2 。
Fig. 7 is a schematic diagram showing a connection relationship of pads when performing a breakdown voltage test on a gate oxide test structure according to another embodiment. Referring to fig. 7, the first bonding pad 31 is finally connected to the active region 12 in each test structure through a plurality of the third metal plugs 233, the fourth bonding pad 34 is connected to the gate 14 in each test structure through a plurality of the third metal plugs 243, that is, the second bonding pad 32 is not connected to the third bonding pad 33, the first bonding pad 31 is connected to the active region 12 of three test structures, and the fourth bonding pad 34 is connected to the gates 14 of three test structures, thereby connecting the gate oxide layers 13 of three test structures in parallel. A high voltage (V) can be applied to the first pad 31 High ) A low voltage (V is applied to the fourth pad 34 Low ) Come and go measurementThe breakdown voltage of the gate oxide 13 is measured. At this time, the area of the gate oxide layer 13 is the area between the first pad 31 and the fourth pad 34, and referring to the size shown in fig. 5, the area of the gate oxide layer 13 may be 8100 μm 2 。
Fig. 6 is a diagram of testing the gate oxide of one test structure, and fig. 7 is a diagram of testing three test structures after the gate oxide is connected in parallel. Of course not limited to only three test structures. It should be noted that, in fig. 6 and fig. 7, only the gate oxide layer in the device region I is tested, and the gate oxide layer in the dummy region II does not participate in the test.
After the semiconductor device is manufactured, the test structure is tested, i.e., wafer Acceptance Testing (WAT), before shipping. Under the condition that the WAT test result is normal, according to the Failure Analysis (FA) result of defective products, pinholes (pin holes) are found at the gate oxide layer of the IC capacitor region, and the pre-cleaning capability of the locking gate oxide layer is poor, namely, defects occur at the pre-cleaning station of the gate oxide layer, but are not detected because the defect size exceeds the detection capability of a factory.
The inventors compared WAT test results of the problem wafer (Issue wafer) with the normal wafer (OK wafer) to find: with the connection shown in fig. 6, the difference in WAT test results for the two wafers is not obvious, whereas with the connection shown in fig. 7, the difference in WAT test results for the two wafers is obvious, and the alarm rate (alarm rate) is increased to about 2%. The inventor considers through research analysis that: the larger the area of the gate oxide layer detected when the test structure is detected, the more defects can be detected, so that the process problem can be more effectively detected.
The inventor has further studied and proposed a gate oxide layer test structure, comprising:
a substrate comprising a device region and a dummy region, the dummy region being located at an edge of the device region, a plurality of isolation structures being formed within the substrate, and an active region defined by the isolation structures;
a gate oxide layer on the substrate, and a gate electrode on the gate oxide layer;
the device region is connected with the gate oxide layer in the virtual region in parallel.
In the gate oxide layer test structure provided by the invention, the device area is connected with the gate oxide layer in the virtual area in parallel, so that the detection area of the gate oxide layer is increased, the breakdown voltage of the gate oxide layer is effectively monitored, the detection capability of WAT is improved, the process problem can be better reflected, and the customer complaint is reduced.
In addition, because the virtual area and the gate oxide layer in the virtual area exist in the existing test structure, only the device area and the gate oxide layer in the virtual area are connected in parallel, namely only the existing test structure is required to be slightly modified, and the method is simple and convenient to operate
The invention will be described in further detail with reference to the drawings and the specific embodiments thereof in order to make the objects, advantages and features of the invention more apparent. It should be noted that the drawings are in a very simplified form and are not drawn to scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.
As used in this disclosure, the singular forms "a," "an," and "the" include plural referents, the term "or" are generally used in the sense of comprising "and/or" and the term "several" are generally used in the sense of comprising "at least one," the term "at least two" are generally used in the sense of comprising "two or more," and the term "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying any relative importance or number of features indicated. Thus, a feature defining "a first", "a second", and "a third" may include one or at least two of the feature, either explicitly or implicitly, unless the context clearly dictates otherwise.
Fig. 8 is a schematic cross-sectional view of a gate oxide test structure according to an embodiment of the invention.
As shown in fig. 8, the gate oxide layer test structure includes:
a substrate comprising a device region I and a dummy region II, the dummy region II being located at an edge of the device region I, a plurality of isolation structures 110 being formed in the substrate, and an active region 120 defined by the isolation structures 110;
a gate oxide layer 130 on the substrate, and a gate electrode 140 on the gate oxide layer 130;
wherein the device region I is connected in parallel with the gate oxide layer 130 in the dummy region II.
In the gate oxide layer test structure provided by the invention, the device region I is connected with the gate oxide layer 130 in the virtual region II in parallel, so that the detection area of the gate oxide layer 130 is increased, the breakdown voltage of the gate oxide layer 130 is more effectively monitored, the detection capability of WAT is improved, the process problem can be better reflected, and the customer complaint is reduced.
The virtual area II can be located at two sides of the device area I or around the device area II, and can be determined by the size of the device area I and the actual requirement or the actual process condition. In this embodiment, the dummy region II is located at two sides of the device region I. In this embodiment, the device region I defines one active region 120 therein, the virtual region II defines a plurality of active regions 120 therein, and the plurality of active regions 120 in the virtual region II are regularly arranged. The gate oxide layer 130 covers the active region 120, and an upper surface of the gate oxide layer 130 may be flush with an upper surface of the isolation structure 110.
The gate oxide test structure further includes a metal interconnection structure 200, in the device region I and the dummy region II, the top of the active region 120 is connected to the first pad through the metal interconnection structure 200, and the top of the gate 140 is connected to the second pad through the metal interconnection structure 200. Between the first bonding pad and the second bonding pad, the device region I is connected in parallel with the gate oxide layer 130 in the dummy region II, so that the detection area of the gate oxide layer 130 can be increased.
Fig. 9 is a top view of fig. 8 at AA ', fig. 10 is a top view of fig. 8 at BB ', and fig. 11 is a top view of fig. 8 at CC '. Referring to fig. 8 to 11, the metal interconnection structure 200 includes an active region first metal layer 2110, an active region second metal layer 2120, an active region third metal layer 2130, an active region first metal plug 2310, an active region second metal plug 2320, and an active region third metal plug 2330, which are connected to the active region 120. The metal interconnect structure 200 further includes a gate first metal layer 2210, a gate second metal layer 2220, and a gate third metal layer 2230, and a gate first metal plug 2410, a gate second metal plug 2420, and a gate third metal plug 2430 connected to the gate 140. The active region first metal layer 2110 and the gate first metal layer 2210 are located on the same layer, the active region second metal layer 2120 and the gate second metal layer 2220 are located on the same layer, and the active region third metal layer 2130 and the gate third metal layer 2230 are located on the same layer, which are named differently for convenience of distinguishing whether they are connected to the active region 120 or the gate 140.
The top of the active region 120 is connected to the active region first metal layer 2110 through the active region first metal plug 2310, the active region first metal layer 2110 is connected to the active region second metal layer 2120 through the active region second metal plug 2320, and the plurality of active region second metal layers 2120 connected to all the active region 120 are connected to each other and to a first pad. In this implementation, the active region second metal layer 2120 may be connected to the active region third metal layer 2130 through the active region third metal plug 2330, and the active region third metal layer 2130 is connected to the first pad. I.e., all of the active regions 120 in the device region I and the dummy region II are connected to the active region first metal layer 2110 through the active region first metal plugs 2310 corresponding thereto, and finally connected to first pads. Equivalent to connecting the bottoms of all the gate oxide layers 130 to the first pads.
The top of the gate electrode 140 is connected to the gate first metal layer 2210 through the gate first metal plug 2410, and the plurality of gate first metal layers 2210 connected to all the gate electrodes 140 are connected to each other and to a second pad. In this embodiment, the gate first metal layer 2210 may be further connected to the gate second metal layer 2220 through the gate second metal plug 2420, the gate second metal layer 2220 is connected to the gate third metal layer 2230 through the gate third metal plug 2430, and the gate third metal layer 2230 is connected to the second pad. That is, all the gates 140 in the device region I and the dummy region II are connected to the gate first metal layer 2210 through the gate first metal plugs 2410 corresponding thereto, and finally connected to the second pads. Since the resistance of the gate electrode 140 is small, it is equivalent to connecting the top of the gate oxide 130 to the second pad.
It is understood that the number of layers of the metal included in the metal interconnection structure 200 is not limited to the three layers shown in fig. 8, but may be two or more layers. The connection manner of the active region 120 to the first pad and the connection manner of the gate 140 to the second pad are not limited to the connection manner described above, and may be performed by other connection manners known to those skilled in the art. The metal interconnection structure 200 further includes an interlayer dielectric layer formed between adjacent metal layers and between the metal layers and the gate 140, and a metal plug is located in the interlayer dielectric layer to connect adjacent metal layers.
As shown in fig. 9 and 8, in the device region I, the gate first metal plug 2410 is formed on the gate 140, and the active region first metal plug 2310 is formed on the active region 120. In the dummy region II, the gate first metal plug 2410 is also formed on the gate 140, and the active region first metal plug 2310 is also formed on the active region 120, and the gate first metal plug 2410 and the active region first metal plug 2310 in the dummy region II are not shown in fig. 9 due to the size, as can be seen in fig. 12.
As shown in fig. 10 and 8, in the device region I and the dummy region II, the gate first metal layer 2210 connected to the gate first metal plug 2410 is integral, i.e., the gate first metal layers 2210 connected to the gate first metal plugs 2410 are connected to each other and extend to the dummy region II, and the gate second metal plugs 2420 are formed thereon to be finally connected to the second pads. A plurality of the active region second metal plugs 2320 are formed on the active region first metal layer 2110 connected to the active region first metal plug 2310. I.e., the device region I and the dummy region II, all of the gates 140 are connected at the gate first metal layer 2210 and finally connected to the second pad.
As shown in fig. 11 and 8, in the device region I and the dummy region II, the active region second metal layer 2120 connected to the active region second metal plug 2320 is integral, i.e., the active region second metal layers 2120 connected to the active region second metal plugs 2320 are connected to each other and extend into the dummy region II on the other side, and a plurality of active region third metal plugs 2330 are formed thereon to be finally connected to the first pads. I.e., the device region I and the dummy region II, all of the active regions 120 are finally connected at the active region second metal layer 2120 and finally connected to the first pad. In the dummy region II on the other side, a plurality of gate third metal plugs 2430 are formed on the gate second metal layer 2220 connected to the gate second metal plugs 2420 to be finally connected to the second pads.
It should be noted that, in fig. 10, the dummy metal 150 is a metal frame that is connected end to end, and the purpose of the dummy metal 150 is to maintain uniformity of flatness or pattern density of the entire substrate, and the dummy metal 150 does not participate in the test.
In the test structure shown in fig. 1 to 4, the dummy region II and the gate oxide layer 130 in the dummy region II are present, which only functions to maintain uniformity of pattern density on the substrate, whereas in fig. 8 to 11, the gate oxide layer 130 in the dummy region II is connected in parallel with the gate oxide layer 130 in the device region I, which increases the area of the gate oxide layer 130 to be tested, and only the gate electrode 140 in the dummy region II and the active region 120 need to be connected to different metal layers through metal plugs, so that only minor modification of the test structure shown in fig. 1 to 4 is required, which is simple in method and convenient to operate.
Fig. 12 is a schematic diagram of a positional relationship between an active region and a gate electrode in the virtual region shown in fig. 8. Referring to fig. 12, in the virtual area II, the dimensions of the active areas 120 are kept uniform, the dimensions of the gates 140 are also kept uniform, and the distances between adjacent active areas 120 are also kept uniform, i.e., the active areas 120 are regularly arranged in the virtual area II. In this embodiment, the horizontal direction in fig. 12 is set as a first direction, the vertical direction in fig. 12 is set as a second direction, the first direction is perpendicular to the second direction, a plane formed by the first direction and the second direction is parallel to the substrate, and the first direction is consistent with the horizontal direction in fig. 8. The size of the gate 140 is smaller than the size of the active region 120 in the first direction, and the size of the gate 140 is larger than the size of the active region 120 in the second direction.
Illustratively, the dimension L1 of the active region 120 is 2 μm+ -0.01 μm in the first direction, and the dimension L2 of the gate 140 is 1.8 μm+ -0.006 μm, i.e., the dimension of the gate 140 is smaller than the dimension of the active region 120 in the first direction. Compared to the size of the active region and the gate electrode shown in fig. 5, the size of the gate electrode 140 is reduced from 2.2 μm to 1.8 μm in the first direction, and the size of the gate electrode 140 is reduced in the first direction to expose the gate oxide layer 130 at the bottom of the gate electrode 140, so that a via hole exposing the active region 120 can be formed in the exposed gate oxide layer 130 to form the active region first metal plug 2310 connected to the active region first metal layer 2110, so that the active region 120 is connected to the active region first metal layer 2110.
In the second direction, the dimension L3 of the active region 120 is 1 μm±0.01 μm, and the dimension L4 of the gate 140 is 1.2 μm±0.006 μm, i.e., the dimension of the gate 140 is larger than the dimension of the active region 120 in the second direction. In the second direction, the dimensions of the active region 120 and the gate 140 are unchanged from those of the active region and the gate shown in fig. 5.
In the first direction, a pitch L5 between adjacent active regions 120 is 1.4 μm±0.01 μm; in the second direction, the spacing L6 between adjacent active regions 120 is 1.4 μm±0.01 μm. The interval L7 of the edges of the active regions 120 adjacent in the first direction in the second direction is 0±0.01 μm, and the interval L8 of the edges of the active regions 120 adjacent in the second direction in the first direction is 0.8 μm±0.01 μm. With the active regions 120 aligned in the first direction as one row, edges of the active regions 120 of the same row (edges in the second direction) are aligned, and the active regions 120 of the second row are moved to the left by 0.8 μm with respect to the active regions 120 of the first row, but not limited thereto, and may be moved to the right by a certain distance. Alternatively, it may be: with the active regions 120 aligned in the second direction as one column, the edges of the active regions 120 of the same column (edges in the first direction) are aligned, and the active regions 120 of the second column are moved up by 0.8 μm with respect to the active regions 120 of the first column, but may be moved down by a certain distance. The invention is not limited in this regard.
According to the above dimensions, after the gate oxide layers 130 are connected in parallel, the area of the gate oxide layer 130 can be increased by 4700 μm 2 Therefore, the breakdown voltage of the gate oxide layer 130 can be monitored more effectively, and the detection capability of WAT is improved.
In summary, in the gate oxide test structure provided by the invention, the device region and the gate oxide in the virtual region are connected in parallel, so that the detection area of the gate oxide is increased, the breakdown voltage of the gate oxide is more effectively monitored, the detection capability of WAT is improved, the process problem can be better reflected, and the customer complaint is reduced.
In addition, in the existing test structure, the virtual area and the gate oxide layer in the virtual area exist, so that only the device area and the gate oxide layer in the virtual area are connected in parallel, namely, only the existing test structure is required to be slightly modified, and the method is simple and convenient to operate.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.
Claims (9)
1. A gate oxide test structure, comprising:
a substrate comprising a device region and a dummy region, the dummy region being located at an edge of the device region, a plurality of isolation structures being formed within the substrate, and an active region defined by the isolation structures;
a gate oxide layer on the substrate, and a gate electrode on the gate oxide layer; the device region is connected with the gate oxide layer in the virtual region in parallel;
and the top of the grid electrode is connected to a second welding pad through the metal interconnection structure.
2. The gate oxide test structure of claim 1, wherein the metal interconnect structure comprises an active region first metal layer, an active region second metal layer, an active region first metal plug, and an active region second metal plug; in the device region and the virtual region, the top of the active region is connected with the active region first metal layer through the active region first metal plug, the active region first metal layer is connected with the active region second metal layer through the active region second metal plug, and the active region second metal layers connected with all the active regions are connected with each other and the first welding pad.
3. The gate oxide test structure of claim 2, wherein the metal interconnect structure further comprises an active region third metal layer and an active region third metal plug; the active region second metal layer is connected with the active region third metal layer through the active region third metal plug, and the active region third metal layer is connected to the first welding pad.
4. The gate oxide test structure of claim 1, wherein the metal interconnect structure comprises a gate first metal layer and a gate first metal plug; in the device region and the dummy region, the top of the gate is connected to the gate first metal layer through the gate first metal plug, and the gate first metal layers connected to all the gates are connected to each other and to the second pad.
5. The gate oxide test structure of claim 4, wherein the metal interconnect structure further comprises a gate second metal layer, a gate third metal layer, a gate second metal plug, and a gate third metal plug; the first metal layer of the grid is connected with the second metal layer of the grid through the second metal plug of the grid, the second metal layer of the grid is connected with the third metal layer of the grid through the third metal plug of the grid, and the third metal layer of the grid is connected to the second welding pad.
6. The gate oxide test structure of claim 1, wherein the dummy region is located on both sides of the device region; or the virtual area is positioned around the device area.
7. The gate oxide test structure of claim 1, wherein in the virtual area, a size of the gate is smaller than a size of the active area in a first direction and a size of the gate is larger than a size of the active area in a second direction; the first direction is perpendicular to the second direction, and a plane formed by the first direction and the second direction is parallel to the substrate.
8. The gate oxide test structure of claim 7, wherein in the first direction, the dimension of the active region is 2 μm ± 0.01 μm and the dimension of the gate is 1.8 μm ± 0.006 μm; in the second direction, the size of the active region is 1 μm.+ -. 0.01 μm, and the size of the gate is 1.2 μm.+ -. 0.006 μm.
9. The gate oxide test structure of claim 8, wherein a pitch between adjacent ones of the active regions in the first direction is 1.4 μm ± 0.01 μm; in the second direction, a spacing between adjacent active regions is 1.4 μm±0.01 μm;
the edges of the active regions adjacent in the first direction are spaced apart from each other by 0 μm±0.01 μm in the second direction; the edges of the active regions adjacent in the second direction are spaced apart from each other by 0.8 μm + -0.01 μm in the first direction.
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| US6841832B1 (en) * | 2001-12-19 | 2005-01-11 | Advanced Micro Devices, Inc. | Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance |
| CN101281897B (en) * | 2007-04-06 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | Matrix type structure for testing integrality of gate oxic horizon |
| CN103094253B (en) * | 2011-11-07 | 2015-08-19 | 无锡华润上华科技有限公司 | A kind of grid oxide layer test structure |
| CN102522386B (en) * | 2011-12-02 | 2014-06-11 | 北京大学 | Gate-oxidizing-layer interface-trap density-testing structure and testing method |
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