CN113284818A - Method for monitoring breakdown voltage of grid oxide layer - Google Patents
Method for monitoring breakdown voltage of grid oxide layer Download PDFInfo
- Publication number
- CN113284818A CN113284818A CN202110552647.5A CN202110552647A CN113284818A CN 113284818 A CN113284818 A CN 113284818A CN 202110552647 A CN202110552647 A CN 202110552647A CN 113284818 A CN113284818 A CN 113284818A
- Authority
- CN
- China
- Prior art keywords
- oxide layer
- active region
- breakdown voltage
- shallow trench
- trench isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015556 catabolic process Effects 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000012544 monitoring process Methods 0.000 title claims abstract description 28
- 238000002955 isolation Methods 0.000 claims abstract description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 37
- 229920005591 polysilicon Polymers 0.000 claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 238000012360 testing method Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a method for monitoring the breakdown voltage of a grid oxide layer, which is used for monitoring the breakdown voltage of the grid oxide layer of a semiconductor structure and comprises the following steps: forming a semiconductor structure, the semiconductor structure comprising: the active area, the shallow trench isolation structure, the grid oxide layer and the polysilicon grid, wherein the shallow trench isolation structure is formed in the active area, the shallow trench isolation structure divides the upper half part of the active area into a plurality of blocky structures, the grid oxide layer covers the active area and the shallow trench isolation structure, and the polysilicon grid covers part of the grid oxide layer; forming a first contact window connected with a source region at the edge of the grid oxide layer, and forming a second contact window connected with a polysilicon grid on the surface of the polysilicon; and testing the voltage between the first contact window and the second contact window to be used as the breakdown voltage of the grid oxide layer. In the method for monitoring the breakdown voltage of the gate oxide layer, the breakdown voltage of the gate oxide layer can be monitored, and the breakdown voltage of the gate oxide layer can be monitored at one time.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for monitoring breakdown voltage of a grid oxide layer.
Background
The prior art semiconductor structure is as shown in fig. 1 and fig. 2, the active region 110 includes a first active region 111 and a second active region 112, the first active region 111 is a rectangular frame structure, a plurality of second active regions 112 are formed in the frame, and the plurality of second active regions 112 are all spaced apart from each other. Shallow trench isolation structures 120 are formed between the second active regions 112, and the shallow trench isolation structures 120 are strip-shaped, that is, the second active regions 112 are divided into a plurality of strip-shaped by the shallow trench isolation structures 120. The extending direction of the shallow trench isolation structure 120 is parallel to the extending direction of the second active region 112, for example, the first direction extends. The polysilicon gate 130 is formed on the active region 110 and the shallow trench isolation structure 120, and an extending direction of the polysilicon gate 130 is perpendicular to an extending direction of the second active region 112, so that the polysilicon gate 130 does not completely cover the second active region 112 and the first active region 111 in the first direction, and the polysilicon gate 130 covers the first active region in the second direction, that is, the polysilicon gate does not cover a boundary of the first active region 111 in the first direction, and the polysilicon gate 130 covers a boundary of the first active region 111 in the second direction. Gate oxide layers are also formed between the polysilicon gate 130 and the second active region 112 and between the shallow trench isolation structures 130. And forming a first contact window on the polysilicon gate, forming a second contact window on the first active region which is not covered by the polysilicon gate, and testing the breakdown voltage of the gate oxide layer by testing the voltage between the first contact window and the second contact window. However, in the case where the first direction is a lateral direction and the second direction is a longitudinal direction, and the second direction is a longitudinal direction and the second direction is a lateral direction, the breakdown voltage of the gate oxide layer needs to be tested separately, and therefore, the test needs to be performed twice.
Disclosure of Invention
The invention aims to provide a method for monitoring the breakdown voltage of a grid oxide layer, which can monitor the breakdown voltage of the grid oxide layer and can complete the monitoring of the breakdown voltage of the grid oxide layer at one time.
In order to achieve the above object, the present invention provides a method for monitoring a breakdown voltage of a gate oxide layer of a semiconductor structure, comprising:
forming a semiconductor structure, the semiconductor structure comprising: the transistor comprises an active area, a shallow trench isolation structure, a grid oxide layer and a polysilicon grid, wherein the shallow trench isolation structure is formed in the active area and divides the upper half part of the active area into a plurality of blocky structures;
forming a first contact window connected with the active region at the edge of the grid oxide layer, and forming a second contact window connected with the polysilicon grid on the surface of the polysilicon;
and testing the voltage between the first contact window and the second contact window to be used as the breakdown voltage of the grid oxide layer.
Optionally, in the method for monitoring the breakdown voltage of the gate oxide layer, the semiconductor structure further includes a substrate, the active region is formed in the substrate, and the gate oxide layer is formed on the surface of the substrate.
Optionally, in the method for monitoring the breakdown voltage of the gate oxide layer, the method for forming the semiconductor structure includes:
providing a substrate;
forming an active region in the substrate;
etching the active region to form a plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are divided into a plurality of rows and a plurality of columns, and the shallow trench isolation structures divide the surface of the active region into a plurality of rows and a plurality of columns;
forming a grid oxide layer on the surfaces of the shallow trench isolation structure and the active region;
and forming a polysilicon gate on the surface of the gate oxide layer.
Optionally, in the method for monitoring the breakdown voltage of the gate oxide layer, the doping depth of the active region is 0 to 2500 nm.
Optionally, in the method for monitoring the breakdown voltage of the gate oxide layer, the depth of the shallow trench isolation structure is 100nm to 600 nm.
Optionally, in the method for monitoring the breakdown voltage of the gate oxide layer, the active region includes a first active region and a second active region, the first active region is in a shape of a plurality of dots, the plurality of dot-shaped second active regions form an array, the first active region forms a frame structure, and the second active region is located in the frame structure.
Optionally, in the method for monitoring the breakdown voltage of the gate oxide layer, the first contact window is located above the first active region.
Optionally, in the method for monitoring the breakdown voltage of the gate oxide layer, the polysilicon gate covers the shallow trench isolation structure and the gate oxide layer above the second active region.
Optionally, in the method for monitoring the breakdown voltage of the gate oxide layer, the second active region forms a 9 by 9 array.
Optionally, in the method for monitoring the breakdown voltage of the gate oxide layer, the cross section of the second active region is square.
According to the method for monitoring the breakdown voltage of the gate oxide layer, the breakdown voltage of the gate oxide layer can be monitored, and the breakdown voltage of the gate oxide layer can be monitored at one time.
Drawings
FIGS. 1 and 2 are schematic diagrams of a prior art semiconductor structure;
FIG. 3 is a flow chart of a method of monitoring breakdown voltage of a gate oxide layer according to an embodiment of the present invention;
FIGS. 4-5 are schematic diagrams of semiconductor structures according to embodiments of the invention;
FIG. 6 is a top view of a semiconductor structure of an embodiment of the invention;
in the figure: 110-active area, 111-first active area, 112-second active area, 130-polysilicon gate, 210-substrate, 220-active area, 221-first active area, 222-second active area, 230-shallow trench isolation structure, 240-gate oxide layer, 250-polysilicon gate, 260-first contact window and 270-second contact window.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Referring to fig. 3, the present invention provides a method for monitoring a breakdown voltage of a gate oxide layer of a semiconductor structure, including:
s11: forming a semiconductor structure, the semiconductor structure comprising: the transistor comprises an active area, a shallow trench isolation structure, a grid oxide layer and a polysilicon grid, wherein the shallow trench isolation structure is formed in the active area and divides the upper half part of the active area into a plurality of blocky structures;
s12: forming a first contact window connected with the active region at the edge of the grid oxide layer, and forming a second contact window connected with the polysilicon grid on the surface of the polysilicon;
s13: and testing the voltage between the first contact window and the second contact window to be used as the breakdown voltage of the grid oxide layer.
Specifically, referring to fig. 4 to 6, a substrate 210 is provided, where the substrate 210 may be a silicon substrate, ions are implanted into the substrate 210 to form an active region 220, the doping depth of the active region is 0nm to 2500nm, the active region in the middle region is partially etched to form a plurality of shallow trenches, and the etching depth is smaller than the depth of the active region, that is, the bottom of the active region is not etched. And filling oxide into the shallow trench to form a shallow trench isolation structure 230, wherein the depth of the shallow trench isolation structure 230 is 100 nm-600 nm. The shallow trench isolation structures 220 divide the upper half of the active area into a plurality of block structures. As can be seen from the top view, if the active regions are divided into the first active region 221 and the second active region 222, the first active region 221 is an outer frame structure, the second active region 222 is located in the frame, the second active region 222 is a plurality of dot-shaped structures, and the second active regions 222 are separated by the shallow trench isolation structures 230, and the second active regions 222 are adjacent to the shallow trench isolation structures 230. The plurality of second active regions 222 may be formed in any form, and embodiments of the present invention may be formed in an array form, and the present invention forms a 3 by 3 array form, but of course, in other embodiments of the present invention, the second active regions may not be in an array form, and may be in a relatively scattered form, and if in an array form, may be in other numbers of arrays. The cross section of the second active region of the present invention is square, and in other embodiments of the present invention, the cross section may have other shapes. Each of the second active regions 222 is not adjacent, nor is the first active region 221 and the second active region 222 adjacent. The width of first active area 221 is 0.5um ~ 6um, and the length and the width of second active area are 0.5 ~ 6um, and the length and the width of active area are 5um ~ 60 um.
Next, a gate oxide layer 240 is formed on the active region 220 and the shallow trench isolation structure 230, that is, the gate oxide layer 240 is formed on the first active region 221, the second active region 222 and the shallow trench isolation structure 230, and the gate oxide layer 240 completely covers the first active region 221, the second active region 222 and the shallow trench isolation structure 230. The material of the gate oxide layer 240 may be an oxide.
Next, a polysilicon gate 250 is formed on the surface of the gate oxide layer 240, and the polysilicon gate 250 covers a portion of the gate oxide layer 240. in the embodiment of the invention, the polysilicon gate 250 covers the gate oxide layer 240 located on the second active region 222 and the shallow trench isolation structure 230. The gate oxide layer 230 on the first active region 221 is not covered.
Next, a first contact window 260(CT) is formed on the gate oxide layer 240 not covered by the polysilicon gate 250, i.e., on the first active region 221, and the first contact window 260 is connected to the first active region 221 through the gate oxide layer 240. A second contact 270(CT) is formed on the polysilicon gate 250, and the second contact 270 is connected to the polysilicon gate 250. The method of forming the first contact 260 and the second contact 270 is prior art. The method for forming the first contact window 260 includes forming a sacrificial layer on the uncovered gate oxide layer, etching the sacrificial layer and the gate oxide layer to form a through hole, filling metal into the through hole, and finally removing the sacrificial layer to form the first contact window. The method for forming the second contact window includes forming a sacrificial layer on the surface of the polysilicon gate, etching the sacrificial layer to form a through hole, filling metal into the through hole, and removing the sacrificial layer to form the second contact window 270. The number of the first contact holes 260 and the number of the second contact holes 270 are plural, and in the embodiment of the present invention, the number of the first contact holes 260 and the number of the second contact holes 270 are 3. The first direction position of the contact window on the active region is located in the middle of the outer ring frame of the active region, and the distance from the right side boundary of the contact window on the polycrystalline silicon grid to the right side boundary of the polycrystalline silicon grid is equal to the distance from the left side boundary of the contact window on the active region to the leftmost active region frame; the first contact window and the second contact window are both in the shape of a cuboid or a cube, namely the cross section can be a square or a rectangle, the side length is 0.3 um-3 um, the number of the first contact window 260 and the second contact window 270 is determined according to the size and the whole size of a single contact window, and the number of the first contact window and the second contact window is 6. Therefore, the gate oxide layers on 9 squares can be measured, the first contact window 260 forms a lower plate, and the second contact window 270 forms an upper plate, so that the breakdown voltage between measurements can be measured at the same time, and the breakdown voltages of the gate oxide layers in the X direction and the Y direction can be measured, so that the breakdown voltage of the gate oxide layers can be monitored at one time.
In summary, in the method for monitoring the breakdown voltage of the gate oxide layer provided in the embodiments of the present invention, the breakdown voltage of the gate oxide layer can be monitored, and the monitoring of the breakdown voltage of the gate oxide layer can be completed at one time.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method for monitoring a breakdown voltage of a gate oxide layer of a semiconductor structure, comprising:
forming a semiconductor structure, the semiconductor structure comprising: the transistor comprises an active area, a shallow trench isolation structure, a grid oxide layer and a polysilicon grid, wherein the shallow trench isolation structure is formed in the active area and divides the upper half part of the active area into a plurality of blocky structures;
forming a first contact window connected with the active region at the edge of the grid oxide layer, and forming a second contact window connected with the polysilicon grid on the surface of the polysilicon;
and testing the voltage between the first contact window and the second contact window to be used as the breakdown voltage of the grid oxide layer.
2. The method of monitoring breakdown voltage of a gate oxide layer of claim 1, wherein the semiconductor structure further comprises a substrate, the active region is formed within the substrate, and the gate oxide layer is formed on the substrate surface.
3. The method of monitoring breakdown voltage of a gate oxide layer of claim 2, wherein the method of forming a semiconductor structure comprises:
providing a substrate;
forming an active region in the substrate;
etching the active region to form a plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are divided into a plurality of rows and a plurality of columns, and the shallow trench isolation structures divide the surface of the active region into a plurality of rows and a plurality of columns;
forming a grid oxide layer on the surfaces of the shallow trench isolation structure and the active region;
and forming a polysilicon gate on the surface of the gate oxide layer.
4. The method of claim 1, wherein the active region has a doping depth of 0 to 2500 nm.
5. The method of claim 1, wherein the depth of the shallow trench isolation structure is 100nm to 600 nm.
6. The method of claim 1, wherein the active region comprises a first active region and a second active region, the first active region is in the shape of a plurality of dots, the plurality of dots of the second active region are in the shape of an array, the first active region forms a frame structure, and the second active region is located within the frame structure.
7. The method of claim 6, wherein the first contact window is over the first active region.
8. The method of claim 6, wherein the polysilicon gate covers a shallow trench isolation structure and the gate oxide over the second active region.
9. The method of monitoring breakdown voltage of a gate oxide layer of claim 6, wherein the second active region forms a 9 by 9 array.
10. The method of monitoring breakdown voltage of a gate oxide layer of claim 6, wherein the second active region has a square cross-section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110552647.5A CN113284818A (en) | 2021-05-20 | 2021-05-20 | Method for monitoring breakdown voltage of grid oxide layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110552647.5A CN113284818A (en) | 2021-05-20 | 2021-05-20 | Method for monitoring breakdown voltage of grid oxide layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113284818A true CN113284818A (en) | 2021-08-20 |
Family
ID=77280400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110552647.5A Pending CN113284818A (en) | 2021-05-20 | 2021-05-20 | Method for monitoring breakdown voltage of grid oxide layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113284818A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115954343A (en) * | 2023-03-09 | 2023-04-11 | 合肥晶合集成电路股份有限公司 | Gate oxide test structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030089960A1 (en) * | 2001-11-13 | 2003-05-15 | United Microelectronics Corp. | Asymmetric high-voltage metal-oxide-semiconductor device |
| KR100734302B1 (en) * | 2006-01-12 | 2007-07-02 | 삼성전자주식회사 | Semiconductor integrated circuit device for increasing integration density and fabrication method thereof |
| CN102931170A (en) * | 2011-08-08 | 2013-02-13 | 中芯国际集成电路制造(上海)有限公司 | Detecting structure, forming method and detecting method |
-
2021
- 2021-05-20 CN CN202110552647.5A patent/CN113284818A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030089960A1 (en) * | 2001-11-13 | 2003-05-15 | United Microelectronics Corp. | Asymmetric high-voltage metal-oxide-semiconductor device |
| KR100734302B1 (en) * | 2006-01-12 | 2007-07-02 | 삼성전자주식회사 | Semiconductor integrated circuit device for increasing integration density and fabrication method thereof |
| CN102931170A (en) * | 2011-08-08 | 2013-02-13 | 中芯国际集成电路制造(上海)有限公司 | Detecting structure, forming method and detecting method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115954343A (en) * | 2023-03-09 | 2023-04-11 | 合肥晶合集成电路股份有限公司 | Gate oxide test structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5638645B2 (en) | Sensing transistor integrated with high voltage vertical transistor | |
| CN107564962B (en) | Groove type MOSFET and preparation method thereof | |
| US10026812B2 (en) | Semiconductor device and method of manufacturing the same | |
| JP5562363B2 (en) | Transistor | |
| JP5772987B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP5637571B2 (en) | Gate metal routing of transistors with grid layout | |
| US8120100B2 (en) | Overlapping trench gate semiconductor device | |
| US20080197397A1 (en) | Checkerboarded high-voltage vertical transistor layout | |
| DE102013114842A1 (en) | Semiconductor device and method of manufacturing a semiconductor device | |
| CN105092324B (en) | A kind of measuring method of FinFET fin piece doping concentration distribution and measurement sample preparation methods | |
| DE102008023474A1 (en) | Semiconductor device with super-junction structure and method for its production | |
| KR20130100655A (en) | Methods of extracting fin heights and overlap capacitance and structures for performing the same | |
| CN112563285A (en) | Vertical semiconductor device | |
| CN108400166A (en) | The power transistor with terminal groove in terminal reduces surface field region | |
| CN113284818A (en) | Method for monitoring breakdown voltage of grid oxide layer | |
| CN112563319A (en) | Semiconductor device with a plurality of semiconductor chips | |
| KR20090069359A (en) | Test pattern of semiconductor device and manufacturing method thereof | |
| CN104584218A (en) | Semiconductor device with JFET width defined by trench isolation | |
| CN113782584B (en) | Superjunction device | |
| KR101213893B1 (en) | Vertical type semiconductor and method of the same | |
| CN216749888U (en) | Test structure of wafer | |
| CN107195682B (en) | Super junction device and manufacturing method thereof | |
| CN208738257U (en) | Power semiconductor | |
| US10217857B2 (en) | Super junction MOSFET and method of manufacturing the same | |
| CN216719941U (en) | Test structure of wafer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210820 |
|
| RJ01 | Rejection of invention patent application after publication |