CN216719941U

CN216719941U - Test structure of wafer

Info

Publication number: CN216719941U
Application number: CN202220300478.6U
Authority: CN
Inventors: 于江勇; 张小麟; 代佳; 张欣慰; 周源; 罗胡瑞
Original assignee: Beijing Yandong Microelectronic Technology Co ltd
Current assignee: Beijing Yandong Microelectronic Technology Co ltd
Priority date: 2022-02-15
Filing date: 2022-02-15
Publication date: 2022-06-10
Anticipated expiration: 2032-02-15

Abstract

The present disclosure provides a test structure of a wafer, including a first insulating layer located on a surface of a semiconductor layer; the first dummy gate and the second dummy gate are positioned on the surface of the first insulating layer, the first dummy gate and the second dummy gate are arranged at intervals along a first direction and extend along a second direction to form two polar plates of the capacitor to be tested, and the first direction, the second direction and the thickness direction of the semiconductor layer are vertical to each other; the first pseudo side wall and the second pseudo side wall are positioned above the semiconductor layer, the first pseudo side wall is positioned on the periphery of the first pseudo gate, the second pseudo side wall is positioned on the periphery of the second pseudo gate, and the first pseudo side wall and the second pseudo side wall positioned between the first pseudo gate and the second pseudo gate form part of medium of the capacitor to be tested; a first test electrode and a second test electrode, the first dummy gate being electrically connected to the first test electrode, the second dummy gate being electrically connected to the second test electrode. The test structure obtains the width of the pseudo side wall according to the electrical test result, so that the width of the side wall in the semiconductor device is monitored, and the test efficiency and accuracy are improved.

Description

Test structure of wafer

Technical Field

The present disclosure relates to the field of semiconductor device manufacturing, and more particularly, to a test structure for a wafer.

Background

Hot carrier effects occur near the drain as the feature size of CMOS (Complementary Metal Oxide Semiconductor) devices is scaled down to submicron and below. The hot carrier effect can be improved by using a Lightly Doped Drain (LDD) process; after the LDD process is performed, a sidewall is generally formed on the sidewall of the gate to prevent the source-drain heavily doped impurities from being implanted next to the gate, so that a lightly doped region with a certain width is formed between the drain and the conductive channel, which can reduce the electric field near the drain and achieve the purpose of weakening the hot carrier effect. However, the formed side wall can affect the saturation current and the on-resistance of the device, and the width of the side wall can also affect the yield and the consistency of the product.

Currently, only destructive means such as Focused Ion Beam (FIB) can be used to monitor the width of the sidewall. Specifically, a semiconductor device to be monitored is cut off by physical means such as focused ion beam bombardment, and then the width of the side wall is manually measured. The method not only needs to damage the wafer and consumes a large amount of material cost and time cost, so that each batch of products cannot be monitored during the batch production of the products, but also only monitors a limited number of wafers in the monitored batch, each wafer can only monitor a limited number of positions, the data volume is small, and the consistency of the side wall width and the reliability of the process cannot be comprehensively reflected. In addition, the current monitoring means needs to be observed by naked eyes and then manually measured, and is influenced by human factors, so that the error of a measuring result is large.

Therefore, it is desirable to provide a wafer test structure suitable for monitoring the width and uniformity of the sidewall in the production of a product batch.

SUMMERY OF THE UTILITY MODEL

In view of this, the present disclosure provides a test structure of a wafer, which obtains a width of a pseudo side wall according to an electrical test result, so as to monitor a width of a side wall in a semiconductor device, and improve efficiency and accuracy of a test.

According to a test structure of a wafer provided by an embodiment of the present disclosure, the wafer includes a plurality of semiconductor devices, wherein at least one semiconductor device includes a gate and a sidewall located at a periphery of the gate, the test structure includes a first test unit, and the first test unit includes:

a first insulating layer on the surface of the semiconductor layer;

the first dummy gate and the second dummy gate are arranged on the surface of the first insulating layer at intervals along a first direction and extend along a second direction to form two polar plates of the capacitor to be tested, wherein the first direction, the second direction and the thickness direction of the semiconductor layer are vertical to each other;

the first pseudo side wall and the second pseudo side wall are positioned above the semiconductor layer, the first pseudo side wall is positioned on the periphery of the first pseudo gate, the second pseudo side wall is positioned on the periphery of the second pseudo gate, and the first pseudo side wall and the second pseudo side wall between the first pseudo gate and the second pseudo gate form part of medium of the capacitor to be tested; and

a first test electrode and a second test electrode, wherein the first dummy is electrically connected to the first test electrode and the second dummy is electrically connected to the second test electrode.

Further, the first test unit further comprises:

the first doping region is positioned in the semiconductor layer and comprises a heavily doped region positioned between the first pseudo side wall and the second pseudo side wall, the heavily doped region comprises two contact regions which are arranged in a spaced mode along the second direction, and the cross section of the heavily doped region positioned between the two contact regions is rectangular; and

and the third test electrode and the fourth test electrode are respectively electrically connected to the two contact regions of the heavily doped region.

Further, the first doping region further comprises a lightly doped region, and the lightly doped region is located at the bottom of the portion, facing each other, of the first pseudo side wall and the second pseudo side wall.

Further, the aforementioned test structure further comprises a second test unit separated from the first test unit, the second test unit comprising:

a second doped region in the semiconductor layer; and

a fifth test electrode and a sixth test electrode electrically connected to the second doped region, respectively,

the square resistance of the second doping area is the same as that of the heavily doped area.

Furthermore, the first pseudo side wall and the second pseudo side wall are located on the surface of the first insulating layer.

Further, the first insulating layer is an oxide layer.

Furthermore, the first test unit comprises a first area and a second area surrounding the first area, the thickness of the oxide layer positioned in the first area is less than that of the oxide layer positioned in the second area,

wherein the oxide layer over at least the first doped region is located in the first region.

Further, along the first direction, the adjacent positions of the first region and the second region are respectively positioned below the first dummy gate and below the second dummy gate.

Furthermore, the first test unit also comprises a second insulating layer which is positioned on the semiconductor layer and covers the first pseudo gate, the second pseudo gate, the first pseudo side wall and the second pseudo side wall,

the first test electrode, the second test electrode, the third test electrode and the fourth test electrode are all located on the surface of the second insulating layer.

Further, the first test unit further includes:

a plurality of leads on the surface of the second insulating layer; and

a plurality of conductive plugs penetrating the second insulating layer;

and the first dummy gate and the second dummy gate are electrically connected to the first test electrode and the second test electrode respectively through corresponding conductive plugs and leads.

According to the test structure of the wafer, the first dummy gate and the second dummy gate are arranged in the first test unit to form a polar plate of a capacitor to be tested, the dummy side walls are arranged on the peripheries of the two dummy gates, and the dummy side walls between the two dummy gates form part of media of the capacitor to be tested; the pseudo side wall width is obtained by measuring the capacitance value of the capacitor to be tested, so that the side wall width of the semiconductor device is monitored, the testing efficiency and accuracy are improved, and the testing cost is reduced.

Furthermore, a heavily doped region is arranged in the semiconductor layer between the first pseudo side wall and the second pseudo side wall, the width of the pseudo side wall is obtained based on the resistance value of the heavily doped region, and the width of the pseudo side wall obtained according to the capacitance value is combined, so that the accuracy of the test can be further improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present application and are not limiting on the present application.

Fig. 1 shows a schematic diagram of a distribution of test structures on a wafer according to an embodiment of the present disclosure.

Fig. 2 shows a top view of a first test unit in a first embodiment of the present disclosure.

Fig. 3 shows a cross-sectional view taken along line AA in fig. 2.

FIG. 4 shows a top view of a first test unit in a second embodiment of the present disclosure.

Fig. 5 shows a cross-sectional view taken along line AA in fig. 4.

Fig. 6 shows a cross-sectional view taken along line BB in fig. 4.

Fig. 7 shows a top view of a portion of the heavily doped region in fig. 6.

FIG. 8 illustrates a top view of a second test cell of the test structure of an embodiment of the present disclosure.

Detailed Description

The present disclosure will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, one layer or region may be "under" or "beneath" another layer or region.

The present disclosure may be presented in various forms, some examples of which are described below.

Fig. 1 shows a schematic diagram of test structures distributed on a wafer according to an embodiment of the present disclosure.

As shown in fig. 1, a wafer 10 includes a plurality of dies 300 and a test structure, the plurality of dies 300 are arranged in rows and columns in an array, and a scribe lane 11 is an area between adjacent dies 300, wherein at least one of the dies 300 includes a semiconductor device (hereinafter referred to as a "device") having a gate and a sidewall. In the present embodiment, the test structure includes the first test unit 100, and the test structure may be distributed in the scribe line 11 or the non-functional region 12 of the wafer 10. In other embodiments, some or all of the test structures described above may also be disposed at the location of the die 300, i.e., some areas for disposing the die 300 are disposed with test structures, although these areas may also be considered non-functional areas.

Fig. 2 shows a top view of a first test unit in a first embodiment of the present disclosure, and fig. 3 shows a cross-sectional view taken along line AA in fig. 2. Here, for the sake of clarity, only the structure of the conductive portion of the first test unit 100 is shown in fig. 2, and the structure of the insulating portion is not shown.

As shown in fig. 2 and 3, the first testing unit 100 of the present embodiment includes: the testing structure includes a first insulating layer 110, a first dummy gate 121, a second dummy gate 122, first dummy spacers 141, second dummy spacers 142, a second insulating layer 160, a plurality of conductive plugs 170, a plurality of leads 180, a first testing electrode 191, and a second testing electrode 192.

The semiconductor layer 101 may be selected according to the actual structure of the device, and specifically may be a substrate, or a stacked substrate and an epitaxial layer, and the like, where the substrate may be, for example, a silicon substrate, a silicon carbide substrate, and the like, and the epitaxial layer may be homoepitaxy or heteroepitaxy. The first insulating layer 110 is located on the semiconductor layer 101, and the material of the first insulating layer 110 may specifically correspond to the material of a gate dielectric layer in the device, such as silicon oxide. In this embodiment, the first insulating layer 110 serves to electrically isolate the semiconductor layer 101 from the first and

second dummy gates

121 and 122, respectively, and thus the material of the first insulating layer 110 may be an insulating material such as silicon nitride or glass phosphate.

The first dummy gate 121 and the second dummy gate 122 are located on the surface of the first insulating layer 110, and along the X-axis direction (first direction), the first dummy gate 121 and the second dummy gate 122 are arranged in parallel and spaced apart from each other, and both extend along the Y-axis direction (second direction), forming a long strip shape. Wherein the X-axis direction, the Y-axis direction, and the thickness direction of the semiconductor layer 101 are perpendicular to each other. The sizes of the first dummy gate 121 and the second dummy gate 122 may be specifically consistent with the size of a gate in a device, especially consistent with the size of a gate surrounded by a side wall of a gate to be tested; the material of the first dummy gate 121 and the second dummy gate 122 may specifically correspond to the gate material in the device, such as polysilicon.

The first dummy spacers 141 are disposed on the first insulating layer 110 and cover the side surfaces of the first dummy gates 121. The second dummy spacers 142 are disposed on the first insulating layer 110 and cover the side surfaces of the second dummy gates 122. The first dummy spacers 141 and the second dummy spacers 142 may be specifically selected from a material used for a gate spacer of a semiconductor device, such as silicon nitride. In this embodiment, the first dummy spacer 141 completely surrounds the first dummy gate 121, and the second dummy spacer 142 completely surrounds the second dummy gate 122, so as to keep the same as the actual condition of the device; in other embodiments, each dummy sidewall may also partially surround the corresponding dummy gate, as long as it is ensured that the side surfaces of at least two dummy gates facing each other are covered by the dummy sidewalls.

Of course, the shape and arrangement of the first dummy gate 121 and the second dummy gate 122 may also be set in other ways, as long as it is ensured that the first dummy gate 121 and the second dummy gate 122 can form two capacitor plates of the capacitor to be measured, and an occupied space for accommodating the first dummy sidewall 141 and the second dummy sidewall 142 is reserved between the two capacitor plates. In addition, since the main function of the first insulating layer 110 is to electrically isolate the semiconductor layer 101 from the first dummy gate 121 and the second dummy gate 122, the first insulating layer 110 may also correspond to the positions of the first dummy gate 121 and the second dummy gate 122, and does not limit whether the first dummy sidewall 141 and the second dummy sidewall 142 are located on the first insulating layer 110.

The second insulating layer 160 is located on the first insulating layer 110 and covers the first dummy gate 121, the second dummy gate 122, the first dummy sidewall 141 and the second dummy sidewall 142; a portion of the conductive plug 170 is electrically connected to the first dummy gate 121 through the second insulating layer 160, and another portion of the conductive plug 170 is electrically connected to the second dummy gate 122 through the second insulating layer 160. A plurality of wires 180, a first test electrode 191, and a second test electrode 192 are positioned on the second insulating layer 160, wherein the first dummy gate 121 is connected to the first test electrode 191 through the corresponding conductive plug 170 and wire 180, and the second dummy gate 122 is connected to the second test electrode 192 through the corresponding conductive plug 170 and wire 180.

Of course, the lead 180 may be omitted, so that the first test electrode 191 and the second test electrode 192 are directly electrically connected to the corresponding conductive plugs 170, that is, one end of the conductive plug 170 is electrically connected to the first dummy gate 121, and the other end is directly electrically connected to the first test electrode 191; the same applies to the connection of the second test electrode 192 and the second dummy gate 122.

The manufacturing process steps corresponding to the first test unit 100 of this embodiment may be compatible with the manufacturing process of the devices on the wafer, and no additional process is required. For example, the first insulating layer 110 in this embodiment is formed on the semiconductor layer 101 in synchronization with the formation of the gate oxide layer (i.e., the gate dielectric layer) of the device. When forming a polysilicon gate of a device, polysilicon is deposited on the surface of the first insulating layer 110 synchronously, and a polysilicon strip is formed by photolithography and etching to obtain a first dummy gate 121 and a second dummy gate 122. And forming a side wall on the side surface of the polysilicon gate, and simultaneously forming a pseudo side wall on the side surface of the polysilicon strip. Then, an insulating layer is deposited, the contact hole is etched by photolithography, and the contact hole is filled with Ti/TiN/W to form the conductive plug 170. And depositing a first layer of metal, and photoetching and etching. The above steps are repeated to form a plurality of layers of metal, and finally, a test electrode and a PAD (PAD) in the device are formed. Optionally, an insulating protection layer is deposited above the top metal layer, and photolithography and etching are performed to form a test electrode and a PAD (PAD area) in the device.

In the present embodiment, the widths of the first dummy sidewall 141 and the second dummy sidewall 142 are obtained by using the electrical parameter of the capacitor, wherein the thicknesses of the first dummy sidewall 141 and the second dummy sidewall 142 are equal to each other, which is considered as W₀. Specifically, the first dummy gate 121 and the second dummy gate 122 may be regarded as two electrode plates of a capacitor to be measured, and the first dummy sidewall 141 and the second dummy sidewall 142 between the two dummy gates constitute a part of a dielectric between the two electrode plates. And connecting the first test electrode 191 and the second test electrode 192 into the CV tester to measure the capacitance C between the two polar plates.

In actual batch production, one or more wafers can be selected from each batch of wafers for testing, representative test structures are selected from the wafers to be tested for testing, at least one test structure is generally selected from the middle part, the upper part, the lower part, the left part and the right part of each wafer for testing, a plurality of capacitance values are obtained through testing, and if the plurality of capacitance values are all in a tolerance range, the consistency of the side wall width of the semiconductor device of the wafer can be judged to meet the requirement; and if the capacitance values of all the wafers to be tested in the whole batch of wafers are within the tolerance range, judging that the consistency of the width of the side wall of the semiconductor device in the batch of wafers meets the requirement.

Furthermore, the dummy spacer with different widths W can be pre-fabricated₀Multiple test structures, specific pseudo side wall width W₀Can be obtained by physical measurement method such as FIB, etc., and is measured by CV testerThe corresponding capacitance C is measured and substituted into equation (1) to obtain the corresponding dielectric constant epsilon.

Wherein S is a relative area between the first dummy sidewall 141 and the second dummy sidewall 142, which is a known design value, d is a distance between two electrode plates, and is considered to be equal to a width W between the first dummy gate 121 and the second dummy gate 122_{General assembly}K is a constant for electrostatic force, a known design value.

Analysis of W from a large number of values₀Relation with epsilon and modeling: w₀＝f(ε)。

In the subsequent testing step, only the ac signal with a specific voltage and a specific frequency is applied between the first testing electrode 191 and the second testing electrode 192, the capacitance C between the first pseudo side wall 141 and the second pseudo side wall 142 is measured, the corresponding dielectric constant e is obtained according to equation (1), and the dielectric constant e is substituted into the model W₀In f (epsilon), W is calculated₀The width W of the first dummy sidewall 141 and the second dummy sidewall 142 can be determined according to the above₀The width and consistency of the side wall of the device at each position of the wafer 10 are monitored, so that the state of the production line is monitored, and the yield of the product is improved.

Fig. 4 shows a top view of a first test unit in a second embodiment, fig. 5 shows a cross-sectional view taken along line AA in fig. 4, and fig. 6 shows a cross-sectional view taken along line BB in fig. 5. In which only a partial structure of the first test unit 100 is shown in fig. 4 for clarity.

As shown in fig. 4 to 6, the first test unit 100 of the present embodiment includes: the testing structure includes a first insulating layer 110, a first dummy gate 121, a second dummy gate 122, a first dummy sidewall 141, a second dummy sidewall 142, a second insulating layer 160, a plurality of conductive plugs 170, a first doping region, a plurality of wires 180, a first testing electrode 191, a second testing electrode 192, a third testing electrode 193, and a fourth testing electrode 194. The structure of the first testing unit 100 of the present embodiment will be described in detail below, wherein the same parts as those of the first embodiment will not be described again.

Unlike the first embodiment, the first testing unit 100 of the present embodiment further includes a first doped region, the first doped region is located in the semiconductor layer 101, and a surface of the first doped region is coplanar with a surface of the semiconductor layer 101. The first doped region includes a lightly doped region 130 and a heavily doped region 150 connected to each other.

The lightly doped region 130 is located in the semiconductor layer 101 between the first dummy gate 121 and the second dummy gate 122, specifically below the dummy sidewalls, for example, below portions of the two dummy sidewalls facing each other. The lightly doped region 130 and the heavily doped region 150 have the same doping type, and the doping concentration of the lightly doped region 130 is less than that of the heavily doped region 150. The lightly doped region 130 in this embodiment is formed to keep the LDD process in synchronization with the device fabrication process on the wafer, so the lightly doped region 130 can be omitted.

The overall shape of the heavily doped region 150 is not limited herein, but it is required to ensure that at least a part of the heavily doped region 150 is located between the first dummy sidewall 141 and the second dummy sidewall 142, and the heavily doped region 150 is provided with two contact regions along the Y-axis direction, wherein the heavily doped region 150 located between the two contact regions is rectangular on the surface of the semiconductor layer 101.

In the semiconductor field, a contact region is a region of a semiconductor region for making ohmic contact with the bottom of a conductive plug. In this embodiment, the contact region can be regarded as the adjacent position of the two conductive plugs 170 and the heavily doped region 150 in fig. 7, so that the region for determining the relevant parameters such as the resistance of the heavily doped region 150 is based on the region defined by the two contact regions. Hereinafter, for convenience and accurate description, the heavily doped region 150 of the rectangular portion between the two contact regions is referred to as a rectangular heavily doped region 150 a. The width W of the rectangular heavily doped region 150a along the X-axis direction₂The spacing distance between the first dummy sidewall 141 and the second dummy sidewall 142; the length L of the rectangular heavily doped region 150a along the Y-axis direction₂Is the separation distance between the two contact areas.

The partial conductive plugs 170 pass through the second insulating layer 160 and the first insulating layer 110 to connect two ends (two contact regions) of the rectangular heavily doped region 150a, respectively. The third test electrode 193 and the fourth test electrode 194 are both located on the second insulating layer 160, wherein one end of the rectangular heavily doped region 150a is connected to the third test electrode 193 through the corresponding conductive plug 170 and the lead 180, and the other end of the rectangular heavily doped region 150a is connected to the fourth test electrode 194 through the corresponding conductive plug 170 and the lead 180.

In the embodiment, the first test unit 100 includes a first region a1 and a second region a2 surrounding the first region a1, wherein the first insulating layer 110 in the first region a1 is a thin oxide layer, and the first insulating layer 110 in the second region a2 is a thick oxide layer, the thickness of the thin oxide layer is less than that of the thick oxide layer, and the thick oxide layer blocks the doped impurities from entering the semiconductor layer 101. The first insulating layer 110 shown in fig. 4 is a thin oxide layer. The adjoining positions of the first and second regions a1 and a2 are located below the first and

second dummy gates

121 and 122, respectively, in the X-axis direction.

The manufacturing process steps corresponding to the first test unit 100 of this embodiment may be compatible with the manufacturing process of the devices on the wafer, and no additional process is required. For example, a thick oxygen layer is grown on the substrate 101 by a thermal oxidation process in synchronization with the device. The thin oxygen layers in this embodiment are formed simultaneously when forming the gate oxide layer (i.e., the gate dielectric layer) of the device. When forming a polysilicon gate of a device, polysilicon is deposited on the surface of the first insulating layer 110 synchronously, and a polysilicon strip is formed by photolithography and etching to obtain a first dummy gate 121 and a second dummy gate 122. Simultaneously with the LDD process of the device, the same process implantation is performed to the region between the polysilicon strips to form lightly doped regions 130. And forming a side wall on the side surface of the polysilicon gate, and simultaneously forming a pseudo side wall on the side surface of the polysilicon strip. And performing source-drain implantation on the device, and simultaneously performing implantation with the same process on the region between the adjacent pseudo side walls to form a heavily doped region 150. Then, an insulating layer is deposited, the contact hole is etched by photolithography, and the contact hole is filled with Ti/TiN/W to form the conductive plug 170. And depositing a first layer of metal, and photoetching and etching. The above steps are repeated to form a plurality of layers of metal, and finally, a test electrode and a PAD (PAD) in the device are formed. Optionally, an insulating protection layer is deposited over the top metal layer and is subjected to photolithography and etching to form a test electrode and a PAD (PAD) in the device.

In this embodiment, the widths W of the first dummy sidewall 141 and the second dummy sidewall 142 are obtained by using the capacitor₀In addition, the widths W of the first dummy spacer 141 and the second dummy spacer 142 can be obtained by using the resistor₀. Specifically, a voltage V is applied across the rectangular heavily doped region 150a through the third and

fourth test electrodes

193 and 194 in the first test unit 100₂And measuring the current I flowing through the third and

fourth test electrodes

193 and 194₂And the resistance R of the rectangular heavily doped region 150a is obtained according to equation (2).

R＝V₂/I₂ (2)

Further, since the resistance R of the rectangular heavily doped region 150a can also be obtained according to equation (3),

wherein Rs2 is the sheet resistance of heavily doped region 150, W₂Is the width, L, of rectangular heavily doped region 150a₂Is the length of the rectangular heavily doped region 150a, wherein the length L of the rectangular heavily doped region 150a₂Is a known design value. The sheet resistance Rs2 of the heavily doped region 150 can be obtained by, for example, simulating a manufacturing process of the heavily doped region 150 on an additional wafer in advance and testing, or obtaining the sheet resistance Rs2 according to conditions such as the doping ion concentration of the heavily doped region 150.

Further, as shown in fig. 5, the width W of the rectangular heavily doped region 150a₂Can be obtained by equation (4).

W₂＝W_{General assembly}-2W₀ (4)

Wherein, W_{General assembly}Is the width between the first dummy gate 121 and the second dummy gate 122, and is a known design value, W₀The widths of the first dummy spacers 141 and the second dummy spacers 142.

Further, substituting equation (4) into equation (3) finally obtains equation (5):

i.e. the width W of the first dummy spacer 141 and the second dummy spacer 142₀Can be obtained by calculation of equation (5).

Therefore, the width W of the first dummy spacer 141 and the second dummy spacer 142 can be obtained₀And (specifically, the average width) the width and uniformity of the sidewall of the device at each position of the wafer 10 are monitored, so that the monitoring of the production line state and the improvement of the product yield are facilitated.

The widths W of the first dummy sidewall 141 and the second dummy sidewall 142 are obtained by using the electrical parameter of resistance₀In the embodiment of the present disclosure, since the sheet resistance Rs2 of the heavily doped region 150 is obtained through a pre-simulation test, the process may fluctuate during the actual manufacturing process, and in order to more accurately obtain the sheet resistance Rs2 of the heavily doped region 150, a second test unit 200 separated from the first test unit 100 may be further added to the test structure of the embodiment of the present disclosure, as shown in fig. 8. In which only a partial structure of the second test unit 200 is shown in fig. 8 for clarity.

The second testing unit 200 includes a second doped region 250 in the semiconductor layer 101, a conductive plug 270 penetrating the second insulating layer 160 and connected to two ends of the second doped region 250, a lead 280 on the second insulating layer 160, a fifth testing electrode 291, and a sixth testing electrode 292, wherein one end of the second doped region 250 is connected to the fifth testing electrode 291 through the corresponding conductive plug 270 and the lead 280, and the other end of the second doped region 250 is connected to the sixth testing electrode 292 through the corresponding conductive plug 270 and the lead 280.

The heavily doped region 150 in the first test unit 100 and the second doped region 250 in the second test unit 200 have the same sheet resistance, and the two regions can be manufactured by the same process, that is, the process parameters such as doping energy and dosage are the same; in the implementation, the heavily doped region 150 and the second doped region 250 are formed simultaneously to ensure that the sheet resistance Rs1 of the second doped region 250 is the same as the sheet resistance Rs2 of the heavily doped region 150 in the first test cell 100. Of course, the second doped region 250 has a rectangular shape for ease of testing and calculation. In the manufacturing steps corresponding to the second testing unit 200 of this embodiment, the manufacturing process may also be compatible with the existing device manufacturing process, and details are not repeated here.

The width W of the first dummy spacer 141 and the second dummy spacer 142 is obtained by using the resistor₀In this embodiment, a voltage V can be applied to both ends of the second doped region 250 through the fifth and

sixth test electrodes

291 and 292 of the second test unit 200₁And measuring the current I flowing through the fifth and

sixth test electrodes

291 and 292₁The sheet resistance Rs1 of the second doped region 250 is obtained according to equation (6).

Wherein, W₁Is the width, L, of the second doped region 250₁Both are known design values for the length of the second doped region 250.

Since the sheet resistance Rs1 of the second doped region 250 is the same as the sheet resistance Rs2 of the heavily doped region in the first test cell 100, Rs2 in equation (5) can be replaced by Rs1, so as to obtain the widths W of the first dummy sidewall 141 and the second dummy sidewall 142₀And the effective and accurate monitoring of the width of the side wall in the device is realized.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims

1. A test structure of a wafer, the wafer includes a plurality of semiconductor devices, wherein at least one semiconductor device includes a gate and a sidewall that is located at the periphery of the gate, characterized in that, the test structure includes a first test unit, the first test unit includes:

a first insulating layer on the surface of the semiconductor layer;

the first dummy gate and the second dummy gate are arranged on the surface of the first insulating layer at intervals along a first direction and extend along a second direction to form two polar plates of a capacitor to be tested, wherein the first direction, the second direction and the thickness direction of the semiconductor layer are vertical to each other;

the first pseudo side wall and the second pseudo side wall are positioned above the semiconductor layer, the first pseudo side wall is positioned at the periphery of the first pseudo gate, the second pseudo side wall is positioned at the periphery of the second pseudo gate, and the first pseudo side wall and the second pseudo side wall positioned between the first pseudo gate and the second pseudo gate form part of a medium of the capacitor to be tested; and

2. The test structure of claim 1, wherein the first test unit further comprises:

the first doped region is positioned in the semiconductor layer and comprises a heavily doped region positioned between the first pseudo side wall and the second pseudo side wall, the heavily doped region comprises two contact regions which are arranged in a second direction in a separated mode, and the cross section of the heavily doped region positioned between the two contact regions is rectangular; and

3. The test structure of claim 2, wherein the first doped region further comprises a lightly doped region, and the lightly doped region is located at a bottom of a portion where the first dummy sidewall and the second dummy sidewall face each other.

4. The test structure of claim 2 or 3, further comprising a second test unit separate from the first test unit, the second test unit comprising:

a second doped region in the semiconductor layer; and

wherein the square resistance of the second doped region is the same as the square resistance of the heavily doped region.

5. The test structure according to claim 2 or 3, wherein the first pseudo side wall and the second pseudo side wall are located on the surface of the first insulating layer.

6. The test structure of claim 5, wherein the first insulating layer is an oxide layer.

7. The test structure of claim 6, wherein the first test cell comprises a first region and a second region surrounding the first region, a thickness of the oxide layer at the first region being less than a thickness of the oxide layer at the second region,

8. The test structure of claim 7, wherein along the first direction, the first region and the second region are adjacent to each other at positions below the first dummy gate and below the second dummy gate, respectively.

9. The test structure of claim 2 or 3, wherein the first test unit further comprises a second insulating layer disposed on the semiconductor layer and covering the first dummy gate, the second dummy gate, the first dummy sidewall spacers, and the second dummy sidewall spacers,

10. The test structure of claim 9, wherein the first test unit further comprises:

a plurality of leads on a surface of the second insulating layer; and

a plurality of conductive plugs penetrating the second insulating layer;

wherein the first dummy gate and the second dummy gate are each electrically connected to the first test electrode and the second test electrode through a corresponding conductive plug and lead.