CN219575638U - Test structure and wafer for shielded gate MOSFET - Google Patents

Abstract

The utility model discloses a test structure and a wafer for a shielded gate MOSFET, wherein the test structure and the shielded gate MOSFET are positioned in the same wafer, and the test structure comprises: at least one trench; the first polysilicon layer and the second polysilicon layer are positioned in the groove, and the oxide layer is used for isolating the first polysilicon layer and the second polysilicon layer; the first conductive column is electrically connected with the first polysilicon layer; the second conductive column is electrically connected with the second polysilicon layer; the first polysilicon layer is an analog structure of a shielding gate in the shielding gate type MOSFET, and the second polysilicon layer is an analog structure of a channel gate in the shielding gate type MOSFET; the first polysilicon layer, the oxide layer and the second polysilicon layer form a capacitor structure. According to the test structure, through the capacitor structure formed by the first polysilicon layer, the oxide layer and the second polysilicon layer, the oxide layer can be monitored, so that the reliability and the production efficiency of the shielded gate MOSFET are improved, and the production cost is reduced.

Description

Test structure and wafer for shielded gate MOSFET

Technical Field

The utility model relates to the technical field of semiconductors, in particular to a test structure and a wafer for a shielded gate MOSFET.

Background

MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-Oxide-semiconductor field effect transistors) are widely used as an important component in integrated circuits in various fields such as power supply and load driving. The shielded gate type MOSFET (Shield Gate Trench MOSFET, SGT MOSFET) is developed from the traditional trench type MOSFET, the advantages of low on-resistance Rds (on) of the traditional trench type MOSFET are maintained in the middle-low voltage field, and the advantages of faster switching speed, lower switching loss and the like are widely applied.

The shielded gate MOSFET includes a shielded gate and a trench gate within the trench. The shielded gate type MOSFET can be further classified into different types according to the relative positional relationship between the shielded gate and the trench gate, such as an upper and lower split gate structure and a left and right split gate structure. In a shielded gate MOSFET with a typical vertical split gate structure, a trench gate is located above the shielded gate and is separated from the shielded gate by a dielectric layer (IPO).

The existing manufacturing process of the shielded gate MOSFET can generally comprise the following steps: s1, forming a groove on an epitaxial wafer, growing a dielectric layer such as an oxide layer on the side wall of the groove and the surface of an epitaxial layer, filling polysilicon in the groove, covering the oxide layer on the surface of the epitaxial layer with the polysilicon layer, and carrying out planarization treatment on the polysilicon; s2, under the premise of protecting the source region, partially etching the polysilicon positioned in the gate region to enable the polysilicon on the surface of the epitaxial layer to be completely etched, wherein the surface of the polysilicon in the groove is lower than the top of the groove; s3, partially corroding the oxide layer in the groove of the gate region, and only reserving the oxide layer below and beside the polysilicon in the groove; s4, forming a dielectric layer such as an oxide layer on the top of the polysilicon and on the side wall of the groove, wherein the oxide layer formed on the top of the polysilicon in the groove of the gate region is IPO, and the oxide layer on the side wall of the groove of the gate region is used as a gate oxide layer; s5, growing polysilicon again to enable the groove in the gate region to be completely filled with polysilicon, and growing a layer of polysilicon on the surface of the epitaxial layer and the surface of the source region; s6, carrying out planarization treatment (such as Chemical Mechanical Polishing (CMP) or polysilicon back etching) on the polysilicon; and S7, growing an interlayer dielectric layer (ILD), carrying out contact hole photoetching and etching, and respectively leading out gate polysilicon and source polysilicon, wherein the source polysilicon and a device source are interconnected through metal. Since the source polysilicon and the gate polysilicon need to be led out respectively, the isolation quality of the IPO layer, which is the isolation structure between the source polysilicon and the gate polysilicon, is a key to be monitored in the device manufacturing process.

Therefore, it is necessary to design a test structure of a shielded gate MOSFET to monitor the process of the IPO layer.

Disclosure of Invention

In view of the foregoing, it is an object of the present utility model to provide a test structure for a shielded gate MOSFET to monitor an IPO layer. The utility model also aims to provide a wafer which comprises the test structure and a die of the shielded gate MOSFET.

According to an aspect of the present utility model, there is provided a test structure for a shielded gate MOSFET in the same wafer as the shielded gate MOSFET, the test structure comprising:

at least one trench;

the first polysilicon layer and the second polysilicon layer are positioned in the groove, and the oxide layer is used for isolating the first polysilicon layer and the second polysilicon layer;

the first conductive column is electrically connected with the first polysilicon layer;

the second conductive column is electrically connected with the second polysilicon layer;

the first polysilicon layer is an analog structure of a shielding gate in the shielding gate type MOSFET, and the second polysilicon layer is an analog structure of a channel gate in the shielding gate type MOSFET; the first polysilicon layer, the oxide layer and the second polysilicon layer form a capacitor structure.

Optionally, the bottom end and part of the side of the second polysilicon layer is surrounded by the first polysilicon layer.

Optionally, the top end of the first polysilicon layer is flush with the top end of the second polysilicon layer.

Optionally, the method further comprises: a first electrode electrically connected to the first conductive post; and the second electrode is electrically connected with the second conductive column.

Optionally, the test structure is located in a scribe line of the wafer; alternatively, the test structure is located in an inactive area of the die core area.

Optionally, the wafer includes a substrate and an epitaxial layer on the substrate, and the trench is in a stacked structure formed by the substrate and the epitaxial layer.

Optionally, the method further comprises: the insulating layer is positioned between the first polysilicon layer and the laminated structure.

Optionally, the oxide layer surrounds the second polysilicon layer and is located in the stacked structure.

Optionally, the trench of the test structure is the same depth as the trench in the shielded gate MOSFET.

According to another aspect of the present utility model there is provided a wafer comprising scribe lines between a die area and an adjacent die area, the die area comprising a shielded gate MOSFET, the wafer further comprising a test structure as previously described located in the scribe lines or in inactive areas in the die area.

The utility model provides a test structure for a shielded gate MOSFET, wherein a first polysilicon layer, an oxide layer and a second polysilicon layer form a capacitor, the two polysilicon layers are respectively used as an upper polar plate and a lower polar plate of the capacitor, and the oxide layer is used as an interlayer dielectric layer of the capacitor. And by measuring the electrical connection relation between the two electrode leading-out ends of the capacitor and periodically monitoring the capacitance value between the two electrode leading-out ends, whether the quality of the oxide layer fluctuates or not can be judged.

Specifically, if the manufacturing process of the shielded gate MOSFET, particularly the forming process of the IPO is stable, the corresponding test structures in the shielded gate MOSFET of any time and different batches should be the same or within an allowable range because the corresponding test structures are the same, so that the quality of the oxide layer in the shielded gate MOSFET can be indirectly monitored by monitoring whether the capacitance value of the test structure changes.

Furthermore, the test means based on the test structure is simple and feasible, and the result is accurate. And because the test structure and the groove of the shielding grid type MOSFET device are formed synchronously, the manufacturing process of the shielding grid type MOSFET is not increased, the reliability and the production efficiency of the shielding grid type MOSFET are improved, and the production cost is reduced.

The wafer provided by the utility model comprises the shielding grid type MOSFET and the test structure for the shielding grid type MOSFET, so that the quality of the IPO layer of the shielding grid type MOSFET can be monitored in the wafer processing process, and the processing quality of the wafer can be ensured.

Drawings

The above and other objects, features and advantages of the present utility model will become more apparent from the following description of embodiments of the present utility model with reference to the accompanying drawings, in which:

FIGS. 1a to 1g show cross-sectional views of stages in a prior art method of manufacturing a typical shielded gate MOSFET;

fig. 2 is a cross-sectional perspective view showing a test structure for a shielded gate MOSFET according to an embodiment of the present utility model;

FIG. 3 is a diagram showing the positional relationship between a test structure and a shielded gate MOSFET device in a wafer according to an embodiment of the present utility model;

fig. 4A-10B show cross-sectional views of various steps of the synchronous formation of a test structure and a shielded gate MOSFET, wherein a and B in the reference numerals respectively represent cross-sectional views of different orientations at the same time.

Detailed Description

The utility model will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.

It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "under" the other layer, another region. If, for the purposes of describing a situation directly overlying another layer, another region, the expression "directly overlying … …" or "overlying … … and adjoining" will be used herein.

Fig. 1a to 1g show cross-sectional views of stages in a manufacturing method of a typical shielded gate MOSFET in the prior art. As shown in fig. 1a to 1g, the manufacturing method of the shielded gate type MOSFET includes the following steps.

Step S10: forming an epitaxial layer 102 on a substrate 101, forming a source region 103 and a trench 120 in the epitaxial layer 102, respectively, as shown in fig. 1 a; or the source region 103 and the trench 120 are formed on an epitaxial wafer, respectively, wherein the epitaxial wafer includes a stacked structure composed of a substrate 101 and an epitaxial layer 102 stacked.

Step S20: an insulating layer 121 is formed on the inner wall of the trench 120 and the surface of the epitaxial layer 102, and the insulating layer 121 forms a cavity 151 along the inner wall of the trench, as shown in fig. 1 b.

Step S30: the cavity 151 is filled with a first polysilicon layer 122. As shown in fig. 1c, the first polysilicon layer 122 also covers the surface of the epitaxial layer 102.

Step S40: the insulating layer 121 and the first polysilicon layer 122 on the surface of the epitaxial layer 102 are removed, and the insulating layer 121 and the first polysilicon layer 122 located on the inner wall of the trench 120 remain, as shown in fig. 1 d.

Step S50: the insulating layer 121 and the first polysilicon layer 122 in the trench 120 are etched back such that the remaining insulating layer 121 and the first polysilicon layer 122 are lower than the notch of the trench 120, and an Oxide (IPO) 123 is formed in the trench 120 above the remaining insulating layer 121 and the first polysilicon layer 122, and the Oxide 123 forms a cavity 152 along the trench sidewall and the top of the remaining insulating layer 121 and the first polysilicon layer 122 after the etching back, as shown in fig. 1 e. In this embodiment, the first polysilicon layer 122 remaining after the etch back acts as a shield gate in a shielded gate MOSFET.

Step S60: the cavity 152 is filled with the second polysilicon layer 124 as shown in fig. 1 f. In this embodiment, the second polysilicon layer 124 in the cavity 152 acts as a channel gate in a shielded gate MOSFET.

Step S70: a dielectric layer 131 and a conductive layer 132 are sequentially formed on the surface of the epitaxial layer 102, and the conductive layer 132 includes a plurality of metal plugs, where the metal plugs penetrate through the dielectric layer 131 and are correspondingly electrically connected to the second polysilicon layer 124 and the source region 103, as shown in fig. 1 g.

Since the source electrode and the gate electrode need to be led out respectively, the isolation quality of an isolation structure between the source electrode and the gate electrode polysilicon (the second polysilicon layer), namely the isolation quality of an oxide layer (an IPO layer), is a key of the device, and the quality of the oxide layer needs to be monitored, but a test structure for monitoring the processing quality of the IPO layer is lacking in the current stage. Therefore, the embodiment of the utility model provides a test structure for a shielded gate MOSFET. The following describes in further detail the specific embodiments of the present utility model with reference to the drawings and examples.

FIG. 2 illustrates a cross-sectional perspective view of a test structure according to an embodiment of the present utility model. Fig. 3 is a diagram showing a test structure versus shielded gate MOSFET device according to an embodiment of the utility model.

As shown in fig. 2 and 3, the wafer 10 includes a Die region 11 and Scribe lines (or referred to as Scribe lanes) 12, wherein the Die region 11 is formed with a plurality of shielded gate MOSFETs, that is, die regions 11 are used to form dies (Die) of the shielded gate MOSFETs, all of the dies are arranged in an array, such as the Die regions 11 are arranged in rows and columns; adjacent die regions 11 are separated by scribe lines 12. In the die region 11, a plurality of shield gate extraction regions of the shield gate MOSFET are included, for example, at edge portions of the die region 11, and a functional region, for example, at a center portion of the die region 11, in which grooves at the shield gate extraction regions and grooves at the functional region communicate and form an "L" shape. In order to ensure the reliability of the shielded gate MOSFET, the embodiment of the utility model synchronously forms a test structure in the scribing groove 12 in the process of preparing the shielded gate MOSFET, and monitors the position which is easy to fail in the process by combining an electrical test means. Of course, in other embodiments, the test structure may occupy a die area, such as a die area including a first die area for forming a die of a shielded gate MOSFET and a second die area as an inactive area for forming the test structure. As shown in fig. 2, the test structure 200 for a shielded gate MOSFET includes at least one trench structure, a first conductive pillar 251 and a second conductive pillar 241.

The trench structure includes a trench 220 in the epitaxial layer 202, a first polysilicon layer 222 and a second polysilicon layer 224 in the trench 220, and an oxide layer 223 isolating the first polysilicon layer 222 and the second polysilicon layer 224. The longitudinal cross section (along the plane in which the Y and Z directions in the drawing) of the first polysilicon layer 222 is in an "L" shape, the second polysilicon layer 224 is located above the side of the first polysilicon layer 222, the bottom end and part of the side of the second polysilicon layer 224 are surrounded by the first polysilicon layer 222, and both the first polysilicon layer 222 and the second polysilicon layer 224 have at least part of their surfaces exposed to the surface of the epitaxial layer 202 and are substantially flush with the surface of the epitaxial layer 202. In this embodiment, an oxide layer 223 is also located between the second polysilicon layer 224 and the epitaxial layer 202 for separating the second polysilicon layer 224 from the epitaxial layer 202.

The first conductive pillars 251 are in contact with and electrically connected to the first polysilicon layer 222 in the trench structure. In other words, the first polysilicon layer 222 is led out through the first conductive pillars 251. The second conductive pillar 241 is in contact with and electrically connected to the second polysilicon layer 224 in the trench structure. In other words, the second polysilicon layer 224 is led out through the second conductive pillar 241. Wherein the first conductive pillars 251 are not in direct contact with the second conductive pillars 241.

In the present test structure, the first polysilicon layer 222 is an analog structure of a shield gate in a shield gate MOSFET; the second polysilicon layer 224 is an analog structure of the channel gate in a shielded gate MOSFET.

In this embodiment, the first polysilicon layer 222, the oxide layer 223, and the second polysilicon layer 224 in each trench structure in the test structure 200 together form a capacitor structure, the two polysilicon layers respectively serve as the upper and lower plates of the capacitor, and the oxide layer 223 serves as the dielectric layer of the capacitor. The quality of the oxide layer 223 in the shielded gate MOSFET can be determined by measuring the electrical connection between the two terminals (two conductive posts) of the capacitor and periodically measuring the capacitance between the two terminals.

Specifically, if the manufacturing process of the shielded gate MOSFET is stable, the test result of the same device in any time and any batch should be within the approximate tolerance range because the corresponding test structures are the same; otherwise, when the capacitance value changes and the change amplitude exceeds the process tolerance, the fluctuation of the quality of the oxide layer can be judged. In view of this, the quality of the oxide layer (IPO layer) in the shielded gate MOSFET can be indirectly monitored by monitoring whether the capacitance value of the test structure 200 changes.

Therefore, the test method based on the test structure is simple and feasible, and the result is accurate. And the test structure is formed synchronously with the trench structure of the shielded gate MOSFET device, so that the manufacturing process of the shielded gate MOSFET is not increased, the reliability and the production efficiency of the shielded gate MOSFET can be improved, and the production cost is saved.

With further reference to fig. 2, the test structure 200 provided in this embodiment may further include: an insulating layer 221 is disposed in the trench structure for isolating the first polysilicon layer 222 from the epitaxial layer 202.

Further, a dielectric layer 231 may be further disposed on the surface of the epitaxial layer 202, and the first conductive pillars 251 and the second conductive pillars 241 respectively penetrate through the dielectric layer 231 and are electrically connected to the corresponding polysilicon layers.

Further, as shown in fig. 2, in order to facilitate electrical testing, a first electrode 252 and a second electrode 242 may be formed on the surface of the dielectric layer 231, the first electrode 252 being in contact with and electrically connected to the first conductive pillar 251, and the second electrode 242 being in contact with and electrically connected to the second conductive pillar 241.

For convenience of description, in this embodiment, the end of each of the first polysilicon layer and the second polysilicon layer, which is close to the bottom of the trench, is referred to as the bottom end, and the end of each of the first polysilicon layer and the second polysilicon layer, which is far from the bottom of the trench (i.e., close to the notch of the trench), is referred to as the top end. Similarly, along the depth direction of the trench, the direction toward the bottom of the trench is referred to as "below", the direction toward the top of the trench (trench slot) is referred to as "above", and the Z direction in fig. 2 is referred to as "above".

In the thickness direction (the Z direction in fig. 2 and the opposite direction thereof), the wafer includes a substrate 201, and an epitaxial layer 202 on the surface of the substrate 201, and the substrate 201 and the epitaxial layer 202 are in a stacked structure. The trench structure is located in the stacked structure. Further, in the present embodiment, the trench 220 extends from the surface of the epitaxial layer 202 into the epitaxial layer 202, i.e., the bottom of the trench 220 is located in the epitaxial layer 202.

Further, the plurality of trenches 220 in the test structure are equal in depth and the same as the trenches in the shielded gate MOSFET, and are formed, for example, in the same process. In other embodiments, the trench 220 extends from the surface of the epitaxial layer 202 through the epitaxial layer 202, and the bottom of the trench 220 is located at the interface between the epitaxial layer 202 and the substrate 201. Alternatively, the trench 220 extends from the surface of the epitaxial layer 202 through the epitaxial layer 202 and into the substrate 201, i.e., the bottom of the trench 220 is located within the substrate 201.

Fig. 4A-10B illustrate cross-sectional views of various steps in the simultaneous formation of a test structure and a shielded gate MOSFET device. Wherein letter a in the picture numbers indicates a sectional view along a broken line AA in fig. 2, and letter B indicates a sectional view along a broken line BB in fig. 2. The different numbers for the same structure indicate that the structure is located in different areas (die area and scribe line). Specifically, each of the sectional views shown in fig. 4A to 10B in the present utility model is, for example, a sectional view at a region C in fig. 2.

The shielded gate MOSFET comprises a trench gate structure positioned in the functional area and a trench gate structure positioned in the shielded gate lead-out area. The trench gate structure positioned in the functional region comprises a trench, a trench gate and a shielding gate positioned in the trench, and an insulating medium layer positioned between the trench gate and the inner wall of the trench, between the shielding gate and the inner wall of the trench and between the trench gate and the shielding gate. The trench gate structure positioned in the shielding gate lead-out area comprises a trench, a polysilicon gate positioned in the trench and an insulating medium layer positioned between the polysilicon gate and the inner wall of the trench, wherein the polysilicon gate is used for leading out the shielding gate electrode of the functional area. The shielded gate type MOSFET is mainly classified into an up-down split gate type MOSFET and a left-right split gate type MOSFET according to the relative positional relationship of the trench gate and the shielded gate. The present embodiment will be described with respect to a test structure corresponding to a vertical split gate MOSFET.

As described above, the test structure 200 may be disposed in the scribe line 12 of the wafer 10, or may occupy the die area 11. The test structure 200 is located in the scribe line 12 will be described below as an example.

Step S11: trenches 220 are formed in the epitaxial layer 202 over the dicing-grooved substrate 201, as shown in fig. 4A.

In this embodiment, step S11 is performed simultaneously with the step of forming the trench 120 in the epitaxial layer 102 above the substrate 101 in the die area.

Step S21: an insulating layer 221 is formed on the sidewalls of the trench 220 of the scribe line and the surface of the epitaxial layer 202 as shown in fig. 5A.

In this step, the insulating layer 221 forms a cavity along the inner wall of the trench 220.

In this embodiment, step S21 is performed simultaneously with the step of forming the insulating layer 121 on the inner walls of the trench 120 and the surface of the epitaxial layer 102 in the die region.

Step S31: the cavity of the scribe line is filled with a first polysilicon layer 222 as shown in fig. 6A.

In this embodiment, the first polysilicon layer 222 not only fills the cavity formed by the insulating layer 221 along the sidewalls of the trench 220, but also overlies the insulating layer 221 on the surface of the epitaxial layer 202.

In this embodiment, step S31 is performed simultaneously with the step of filling the first polysilicon layer 122 in the cavity of the die area.

Step S41: removing the first polysilicon layer 222 and the insulating layer 221 over the surface of the epitaxial layer 202 of the scribe line, as shown in fig. 7A; partially etching back the insulating layer 221 and the first polysilicon layer 222 in the scribe line trench 220; and forming an oxide layer 223 in the groove formed by the scribe line etch back, as shown in fig. 8A and 8B.

In this embodiment, in the step of partially etching back the insulating layer 221 and the first polysilicon layer 222 in the scribe line trench 220, the insulating layer 221 and the first polysilicon layer 222 that do not need to be etched back may be protected with photoresist or other mask to obtain the etching back result as shown in fig. 8B. As shown in fig. 8B, the remaining first polysilicon layer 222 is etched back to have an L-shaped longitudinal cross section, that is, after the etching back, a portion of the upper surface of the first polysilicon layer 222 is flush with the notch of the trench 220, and another portion of the upper surface is lower than the notch of the trench 220, thereby forming a groove.

Further, the oxide layer 223 covers the groove surface formed by the etch back.

In this embodiment, step S41 is performed simultaneously with the steps of removing the first polysilicon layer 122 and the insulating layer 121 on the surface of the epitaxial layer 102 in the die area, etching back the first polysilicon layer 122 and the insulating layer 121 in the die area trench 120, and forming the oxide layer 123 in the recess formed by the etching back in the die area trench 120.

Step S51: the second polysilicon layer 224 is filled in the grooves formed by the scribe line etchback, as shown in fig. 9A and 9B.

In this step, referring to fig. 9B, the second polysilicon layer 224 fills the recess formed when the first polysilicon layer 222 is etched back, and the first polysilicon layer 222 and the second polysilicon layer 224 are isolated by the oxide layer 223.

In this embodiment, step S51 is performed simultaneously with the step of filling the second polysilicon layer 124 in the recess formed by the etch back in the die area trench 120.

Further, in the die region, the first polysilicon layer 122 is located at a lower portion in the trench 120, the second polysilicon layer 124 is located at an upper portion of the trench 120, the first polysilicon layer 122 is isolated from the second polysilicon layer 124 by the oxide layer 123, and at the same time, the upper surface of the trench 120 exposes only the second polysilicon layer 124, and the upper surface of the first polysilicon layer 122 is located below the oxide layer 123. However, in the scribe line, the first polysilicon layer 222 and the second polysilicon layer 224 are simultaneously exposed at the notch of the trench 220, as shown in fig. 9B, that is, a portion of the upper surface of the first polysilicon layer 222 is exposed at the notch of the trench 220, another portion of the upper surface is covered by the oxide layer 223 and the second polysilicon layer 224, and the upper surface of the second polysilicon layer 224 is exposed at the notch of the trench 220.

Step S61: depositing a dielectric layer 231 on the surface of the epitaxial layer 202 of the scribe line; forming a via hole in the dielectric layer 231 of the scribe line; and depositing a conductive material in the via hole of the scribe line and patterning the conductive material layer, as shown in fig. 10A and 10B.

In this embodiment, when forming the via hole in the dielectric layer 231 of the scribe line, the via hole includes a first via hole exposing the upper surface of the first polysilicon layer 222 and a second via hole exposing the upper surface of the second polysilicon layer 224, so that the conductive material filled in the first via hole forms the first conductive pillar 251 in the subsequent step of depositing the conductive material, and the first conductive pillar 251 is in electrical contact with the first polysilicon layer 222; the conductive material filled in the second via hole forms a second conductive pillar 241, and the second conductive pillar 241 is in electrical contact with the second polysilicon layer 224. Further, the conductive material also covers the surface of the dielectric layer 231, and a through groove is formed by photolithography and etching, so that the conductive material covering the surface of the dielectric layer 231 is divided into two parts, one part is electrically connected to only the first conductive post 251 as the first electrode 252, and the other part is electrically connected to only the second conductive post 241 as the second electrode 242.

Therefore, in the test structure 200, the first electrode 252 is electrically connected to the first polysilicon layer 222 via the first conductive pillar 251, the second electrode 242 is electrically connected to the second polysilicon layer 224 via the second conductive pillar 241, and the first polysilicon layer 222 and the second polysilicon layer 224 are separated by the oxide layer 223, which can be respectively regarded as upper and lower plates of the capacitor, i.e. the test structure 200 is formed as a capacitor structure. In the present test structure, voltage data of the capacitor structure may be tested by the first electrode 252 and the second electrode 242, and further quality stability of the oxide layer 223 may be determined according to the voltage data.

In this embodiment, step S61 is performed simultaneously with the steps of depositing a dielectric layer 131 on the surface of the epitaxial layer 102 in the die area, forming a via hole in the dielectric layer 131 in the die area, depositing a conductive material in the via hole in the die area, and forming the source region 103 and the conductive post 141 of the second polysilicon layer 124 and the electrode 142.

In addition, the test structure may be located in an available area, i.e., an inactive area, in the die area of the wafer, where no semiconductor structure is formed, for example, so as to facilitate subsequent testing without affecting the shielded gate MOSFET device.

The embodiment of the utility model also provides a wafer, referring to fig. 3, the wafer 10 includes a plurality of die areas 11 and scribe lines 12, wherein the die areas 11 are formed with a plurality of shielded gate MOSFETs, and the plurality of die areas 11 are arranged in an array; adjacent die regions 11 are separated by scribe lines 12, and test structures 200 are formed in scribe lines 12.

In other embodiments, the test structure 200 may also occupy a die area 11, such as the die area 11 comprising a first die area for forming a die for shielding a gate MOSFET and a second die area as an inactive area for forming the test structure.

The utility model provides a test structure for a shielded gate MOSFET, which adopts a first polysilicon layer, an oxide layer and a second polysilicon layer to form a capacitor, wherein the two polysilicon layers are respectively used as an upper polar plate and a lower polar plate of the capacitor, and the oxide layer is used as a dielectric layer of the capacitor. By measuring the electrical connection relation between the two electrode leading-out ends of the capacitor and periodically monitoring the capacitance value between the two electrode leading-out ends, whether the IPO quality in the shielded gate MOSFET fluctuates or not can be judged.

Specifically, if the manufacturing process of the shielded gate MOSFET is stable, in the shielded gate MOSFET of any time and different batches, because the corresponding manufactured test structures are the same, the test values should be the same or within the allowable tolerance range of the process, so that the quality of the IPO layer in the shielded gate MOSFET can be indirectly monitored by monitoring whether the capacitance value of the test structure changes.

Furthermore, the test method based on the test structure is simple and feasible, and the result is accurate. The test structure and the trench gate structure of the shielded gate MOSFET are formed synchronously, the manufacturing process of the shielded gate MOSFET is not increased, the reliability and the production efficiency of the shielded gate MOSFET are improved, and the production cost is reduced.

In the description of the present embodiment, the terms "first", "second" are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

Embodiments in accordance with the present utility model, as described above, are not intended to be exhaustive or to limit the utility model to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the utility model and the practical application, to thereby enable others skilled in the art to best utilize the utility model and various modifications as are suited to the particular use contemplated. The utility model is limited only by the claims and the full scope and equivalents thereof.

Claims (10)

1. A test structure for a shielded gate MOSFET in the same wafer as the shielded gate MOSFET, the test structure comprising:

at least one trench;

a first polysilicon layer and a second polysilicon layer in the trench, and an oxide layer isolating the first polysilicon layer and the second polysilicon layer;

the first conductive column is electrically connected with the first polysilicon layer;

the second conductive column is electrically connected with the second polysilicon layer;

the first polysilicon layer is an analog structure of a shielding gate in the shielding gate type MOSFET, and the second polysilicon layer is an analog structure of a channel gate in the shielding gate type MOSFET; the first polysilicon layer, the oxide layer and the second polysilicon layer form a capacitor structure.

2. The test structure of claim 1, wherein a bottom end and a portion of a side of the second polysilicon layer are surrounded by the first polysilicon layer.

3. The test structure of claim 2, wherein a top end of the first polysilicon layer is flush with a top end of the second polysilicon layer.

4. The test structure of claim 1, further comprising:

a first electrode electrically connected to the first conductive post;

and the second electrode is electrically connected with the second conductive column.

5. The test structure of any of claims 1-4, wherein the test structure is located in a scribe line of the wafer; alternatively, the test structure is located in an inactive area of the die core area.

6. The test structure of any of claims 1-4, wherein the wafer comprises a substrate and an epitaxial layer on the substrate, the trench being in a stacked structure formed by the substrate and the epitaxial layer.

7. The test structure of claim 6, further comprising: and the insulating layer is positioned between the first polysilicon layer and the laminated structure.

8. The test structure of claim 7, wherein the oxide layer surrounds the second polysilicon layer and is located in the stacked structure.

9. The test structure of claim 1, wherein the trench of the test structure is of equal depth as the trench in the shielded gate MOSFET.

10. A wafer comprising scribe lines between a die area and an adjacent die area, the die area comprising a shielded gate MOSFET, further comprising the test structure of any of claims 1-9, the test structure being located in the scribe line or in an inactive area in the die area.