CN216749888U - Test structure of wafer - Google Patents

Abstract

The disclosure provides a test structure of a wafer, which includes a first dummy gate and a second dummy gate on a semiconductor layer and arranged at an interval along a first direction; the first pseudo side wall is positioned at the periphery of the first pseudo gate; the second pseudo side wall is positioned at the periphery of the second pseudo gate, and at least part of the first pseudo side wall is arranged opposite to the second pseudo side wall; the first doping region is positioned in the semiconductor layer and comprises a heavily doped region positioned between the first pseudo side wall and the second pseudo side wall, the heavily doped region comprises two separated contact regions arranged along the second direction, and the cross section of the heavily doped region positioned between the two contact regions is rectangular; and a first test electrode and a second test electrode electrically connected to two contact regions of the heavily doped region, respectively, wherein the first direction, the second direction and a thickness direction of the semiconductor layer are perpendicular to each other. The test structure obtains the width of the pseudo side wall according to the electrical test result, so that the width of the side wall in the semiconductor device is monitored, and the test efficiency and accuracy are improved.

Description

Test structure of wafer

Technical Field

The present disclosure relates to the field of semiconductor device manufacturing, and more particularly, to a test structure for a wafer.

Background

Hot carrier effects occur near the drain as the feature size of CMOS (Complementary Metal Oxide Semiconductor) devices is scaled down to submicron and below. The hot carrier effect can be improved by using a Lightly Doped Drain (LDD) process; after the LDD process is performed, a sidewall is generally formed on the sidewall of the gate to prevent the source-drain heavily doped impurities from being implanted next to the gate, so that a lightly doped region with a certain width is formed between the drain and the conductive channel, which can reduce the electric field near the drain and achieve the purpose of weakening the hot carrier effect. However, the formed side wall can affect the saturation current and the on-resistance of the device, and the width of the side wall can also affect the yield and the consistency of the product.

At present, in order to monitor the width of the sidewall, only destructive means such as Focused Ion Beam (FIB) and the like can be used, and generally, a semiconductor device to be monitored is cut off by physical means such as Focused Ion beam bombardment and the like, and then the width of the sidewall is manually measured. The method not only needs to damage the wafer and consumes a large amount of material cost and time cost, so that each batch of products cannot be monitored during the batch production of the products, but also only monitors a limited number of wafers in the monitored batch, each wafer can only monitor a limited number of positions, the data volume is small, and the consistency of the side wall width cannot be comprehensively reflected. In addition, the current monitoring means needs to be observed by naked eyes and then manually measured, and is influenced by human factors, so that the error of a measuring result is large.

Therefore, it is desirable to provide a wafer test structure suitable for monitoring the width and uniformity of the sidewall in the production of a product batch.

SUMMERY OF THE UTILITY MODEL

In view of this, the present disclosure provides a test structure of a wafer, which obtains a width of a pseudo side wall according to an electrical test result, so as to monitor a width of a side wall in a semiconductor device, and improve efficiency and accuracy of a test.

According to a test structure of a wafer provided by an embodiment of the present disclosure, the wafer includes a plurality of semiconductor devices, wherein at least one semiconductor device includes a gate and a sidewall located at a periphery of the gate, the test structure includes a first test unit, and the first test unit includes:

the first dummy gate and the second dummy gate are positioned on the semiconductor layer and are arranged at intervals along a first direction;

the first pseudo side wall and the second pseudo side wall are positioned on the semiconductor layer, the first pseudo side wall is positioned on the periphery of the first pseudo gate, the second pseudo side wall is positioned on the periphery of the second pseudo gate, and at least part of the first pseudo side wall and the second pseudo side wall are arranged oppositely;

the first doping region is positioned in the semiconductor layer and comprises a heavily doped region positioned between the first pseudo side wall and the second pseudo side wall, the heavily doped region comprises two separated contact regions arranged along the second direction, and the cross section of the heavily doped region positioned between the two contact regions is rectangular; and

a first test electrode and a second test electrode electrically connected to two contact regions of the heavily doped region, respectively,

wherein the first direction, the second direction and the thickness direction of the semiconductor layer are perpendicular to each other.

Furthermore, the first test unit further comprises a first insulating layer located on the surface of the semiconductor layer, and the first dummy gate and the second dummy gate are located on the surface of the first insulating layer.

Further, the first doping region also comprises a lightly doped region positioned between the first dummy gate and the second dummy gate, and the lightly doped region is contacted with the heavily doped region.

Furthermore, the first pseudo side wall and the second pseudo side wall are located on the surface of the first insulating layer.

Further, the first insulating layer is an oxide layer.

Furthermore, the first test unit comprises a first area and a second area surrounding the first area, the thickness of the oxide layer positioned in the first area is less than that of the oxide layer positioned in the second area,

wherein the oxide layer above at least the first doped region is located in the first region.

Further, along the first direction, the adjacent positions of the first region and the second region are respectively positioned below the first dummy gate and below the second dummy gate.

Furthermore, the first test unit also comprises a second insulating layer which covers the first pseudo gate, the second pseudo gate, the first pseudo side wall and the second pseudo side wall,

the first test electrode and the second test electrode are both positioned on the surface of the second insulating layer.

Further, the first test unit further includes:

a plurality of conductive plugs penetrating the second insulating layer; and

a plurality of leads on the surface of the second insulating layer;

the first test electrode and the second test electrode are electrically connected to two contact regions of the heavily doped region through corresponding leads and conductive plugs respectively.

Further, a second test unit is included that is separate from the first test unit, the second test unit including:

a second doped region in the semiconductor layer; and

a third test electrode and a fourth test electrode electrically connected to the second doped region, respectively,

the square resistance of the second doping area is the same as that of the heavily doped area.

According to the test structure of the wafer, the first pseudo gate, the second pseudo gate and the pseudo side wall located on the periphery of the pseudo gate are arranged in the first test unit, and the width of the pseudo side wall is obtained by measuring the resistance value of the rectangular heavily doped region located between the pseudo side walls, so that the width of the side wall in a semiconductor device is monitored, the test efficiency and accuracy are improved, and the test cost is reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present application and are not limiting on the present application.

Fig. 1 shows a schematic diagram of test structures distributed on a wafer according to an embodiment of the present disclosure.

Fig. 2 shows a top view of a first test unit of a first embodiment of the present disclosure.

Fig. 3 shows a cross-sectional view taken along line AA in fig. 2.

Fig. 4 shows a cross-sectional view taken along line BB in fig. 2.

Fig. 5 shows a top view of a portion of the heavily doped region in fig. 2.

FIG. 6 illustrates a top view of a second test cell in a test structure of an embodiment of the disclosure.

Fig. 7 shows a top view of a first test unit of a second embodiment of the present disclosure.

Fig. 8 shows a cross-sectional view taken along line AA in fig. 7.

Fig. 9 shows a cross-sectional view taken along line BB in fig. 7.

Detailed Description

The present disclosure will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

The present disclosure may be presented in various forms, some examples of which are described below.

Fig. 1 shows a schematic diagram of test structures distributed on a wafer according to an embodiment of the present disclosure.

As shown in fig. 1, a wafer 10 includes a plurality of dies 300 and a test structure, the plurality of dies 300 are arranged in rows and columns in an array, and a scribe lane 11 is an area between adjacent dies 300, wherein at least one of the dies 300 includes a semiconductor device (hereinafter referred to as a "device") having a gate and a sidewall. In the present embodiment, the test structure includes the first test unit 100, and the test structure may be distributed in the scribe line 11 or the non-functional region 12 of the wafer 10. In other embodiments, some or all of the test structures described above may also be disposed at the location of the die 300, i.e., some areas for disposing the die 300 are disposed with test structures, although these areas may also be considered non-functional areas.

Fig. 2 shows a top view of a first test unit of a first embodiment of the present disclosure, fig. 3 shows a cross-sectional view taken along line AA in fig. 2, and fig. 4 shows a cross-sectional view taken along line BB in fig. 2. In which only a partial structure of the first test unit 100 is shown in fig. 2 for the sake of clarity.

As shown in fig. 2 to 4, the first test unit 100 of the present embodiment includes: the first dummy gate 121, the second dummy gate 122, the first dummy sidewall 141, the second dummy sidewall 142, the second insulating layer 160, the first doped region, the plurality of conductive plugs 170, the plurality of leads 180, a test electrode 193 (a first test electrode), and a test electrode 194 (a second test electrode).

The semiconductor layer 101 may be selected according to the actual structure of the device, and may specifically be a substrate, or a stacked substrate and an epitaxial layer, where the substrate may be, for example, a silicon substrate, a silicon carbide substrate, and the like, and the epitaxial layer may be homoepitaxy or heteroepitaxy.

The first dummy gate 121 and the second dummy gate 122 are disposed on the semiconductor layer 101, and along the X-axis direction (first direction), the first dummy gate 121 and the second dummy gate 122 are spaced apart and arranged in parallel, and both extend along the Y-axis direction (second direction), forming a long stripe shape. Wherein the X-axis direction, the Y-axis direction, and the thickness direction of the semiconductor layer 101 are perpendicular to each other. The sizes of the first dummy gate 121 and the second dummy gate 122 may be specifically consistent with the size of a gate in a device, and especially consistent with the size of a gate corresponding to a sidewall to be measured. The materials of the first dummy gate 121 and the second dummy gate 122 include, but are not limited to, polysilicon, and may specifically correspond to the gate materials in the device.

The first dummy spacers 141 are disposed on the semiconductor layer 101 and cover the side surfaces of the first dummy gate 121. The second dummy spacers 142 are disposed on the semiconductor layer 101 and cover the side surfaces of the second dummy gates 122. The first dummy spacers 141 and the second dummy spacers 142 may be specifically selected from a material used for a gate spacer of a semiconductor device, such as silicon nitride. In this embodiment, the first dummy spacer 141 completely surrounds the side surface of the first dummy gate 121, and the second dummy spacer 142 completely surrounds the side surface of the second dummy gate 122. In other embodiments, the dummy spacers may also partially surround the dummy gates, as long as the dummy spacers are ensured to cover at least two sides of the dummy gates facing each other.

The first doped region is located in the semiconductor layer 101, and specifically, a surface of the first doped region is coplanar with a surface of the semiconductor layer 101. In this embodiment, the first doped region is the heavily doped region 150, the overall shape of the heavily doped region 150 is not limited herein, but it is required to ensure that at least a part of the heavily doped region 150 is located between the first pseudo sidewall 141 and the second pseudo sidewall 142, and the heavily doped region 150 is provided with two contact regions along the Y-axis direction, wherein, on the surface of the semiconductor layer 101, the heavily doped region 150 located between the two contact regions is rectangular.

In the semiconductor field, a contact region is a region of a semiconductor region for making ohmic contact with the bottom of a conductive plug. In this embodiment, the contact region can be regarded as the adjacent position of the two conductive plugs 170 and the heavily doped region 150 in fig. 5, so that the region for determining the relevant parameters such as the resistance of the heavily doped region 150 is based on the region defined by the two contact regions. Hereinafter, for convenience and accurate description, the heavily doped region 150 of the rectangular portion between the two contact regions is referred to as a rectangular heavily doped region 150 a. The width W of the rectangular heavily doped region 150a along the X-axis direction₁Is the first dummy sidewall 141 andthe spacing distance between the second dummy sidewalls 142; the length L of the rectangular heavily doped region 150a along the Y-axis direction₁Is the separation distance between the two contact areas.

The second insulating layer 160 is located on the semiconductor layer 101 and covers the first dummy gate 121, the second dummy gate 122, the first dummy sidewall 141 and the second dummy sidewall 142; the conductive plugs 170 are connected to both ends (both contact regions) of the rectangular heavily doped region 150a through the second insulating layer 160, respectively, in the Y-axis direction. A plurality of lead lines 180 and test electrodes 193 and 194 are positioned on the second insulating layer 160, wherein one end of the rectangular heavily doped region 150a is connected to the test electrode 193 through the corresponding conductive plugs 170 and lead lines 180, and the other end of the rectangular heavily doped region 150a is connected to the test electrode 194 through the corresponding conductive plugs 170 and lead lines 180.

The manufacturing process steps corresponding to the first test unit 100 of this embodiment may be compatible with the manufacturing process of the devices on the wafer, and no additional process is required. For example, in synchronization with the device, when a polysilicon gate of the device is formed, polysilicon is deposited on the surface of the semiconductor layer 101 in synchronization, and a polysilicon strip is formed by photolithography and etching, so as to obtain the first dummy gate 121 and the second dummy gate 122. And forming a side wall on the side surface of the polysilicon gate, and simultaneously forming a pseudo side wall on the side surface of the polysilicon strip. And performing source-drain implantation on the device, and simultaneously performing implantation with the same process on the region between the adjacent pseudo side walls to form a heavily doped region 150. Then, an insulating layer is deposited, the contact hole is etched by photolithography, and the contact hole is filled with Ti/TiN/W to form the conductive plug 170. And depositing a first layer of metal, and photoetching and etching. The above steps are repeated to form a plurality of layers of metal, and finally, a test electrode and a PAD (PAD) in the device are formed. Optionally, an insulating protection layer is deposited over the top metal layer and is subjected to photolithography and etching to form a test electrode and a PAD (PAD) in the device.

In the present embodiment, the widths W of the first dummy sidewall 141 and the second dummy sidewall 142 are obtained by using resistors₀. Specifically, a voltage V is applied across the rectangular heavily doped region 150a through the test electrodes 193, 194 in the first test unit 100₁And measuring the current I flowing through the test electrodes 193 and 194₁And the resistance R of the rectangular heavily doped region 150a is obtained according to equation (1).

R＝V₁/I₁ (1)

Further, the resistance R due to the rectangular heavily doped region 150a can also be obtained according to equation (2).

Wherein Rs1 is the sheet resistance of heavily doped region 150, W₁Is the width, L, of rectangular heavily doped region 150a₁Is the length of the rectangular heavily doped region 150a, wherein the length L of the rectangular heavily doped region 150a₁Is a known design value. The sheet resistance Rs1 of the heavily doped region 150 can be obtained by, for example, simulating a manufacturing process of the heavily doped region 150 on an additional wafer in advance and testing, and is determined according to parameters such as the concentration of doped ions.

Further, as shown in fig. 3, the width W of the rectangular heavily doped region 150a₁Can be obtained by equation (3).

W₁＝W_{General assembly}-2W₀ (3)

Wherein, W_{General assembly}Is the width between the first dummy gate 121 and the second dummy gate 122, and is a known design value, W₀The widths of the first dummy spacers 141 and the second dummy spacers 142.

Further, substituting equation (3) into equation (2) finally obtains equation (4):

i.e. the width W of the first dummy spacer 141 and the second dummy spacer 142₀Can be obtained by calculation of equation (4).

Therefore, the width W of the first dummy spacer 141 and the second dummy spacer 142 can be obtained₀The width and consistency of the side walls of the devices at each position of the wafer 10 are monitored, so that the state of the production line is monitored, and the yield of the product is improved.

Since the sheet resistance Rs1 of the heavily doped region 150 is obtained through a pre-simulation test, the process may fluctuate during the actual manufacturing process, and in order to more accurately obtain the sheet resistance Rs1 of the heavily doped region 150, a second test unit 200 separated from the first test unit 100 may be further added to the test structure of the embodiment of the present disclosure, as shown in fig. 6. Wherein only a partial structure of the second test unit 200 is shown in fig. 6 for clarity.

The second test unit 200 includes a second doped region 250 in the semiconductor layer 101, a conductive plug 270 penetrating the second insulating layer 160 and connected to two ends of the second doped region 250, a lead 280 on the second insulating layer 160, a test electrode 291 (third test electrode), and a test electrode 292 (fourth test electrode), wherein one end of the second doped region 250 is connected to the test electrode 291 through the corresponding conductive plug 270 and lead 280, and the other end of the second doped region 250 is connected to the test electrode 292 through the corresponding conductive plug 270 and lead 280.

The heavily doped region 150 in the first test unit 100 and the second doped region 250 in the second test unit 200 have the same sheet resistance, and the two regions can be manufactured by the same process, that is, the process parameters such as doping energy and dosage are the same; in the implementation, the heavily doped region 150 is formed simultaneously with the second doped region 250, so that the sheet resistance Rs2 of the second doped region 250 is the same as the sheet resistance Rs1 of the heavily doped region 150 in the first test cell 100. Of course, the second doped region 250 has a rectangular shape for ease of testing and calculation. In the manufacturing steps corresponding to the second testing unit 200 of this embodiment, the manufacturing process may also be compatible with the existing device manufacturing process, and details are not repeated here.

Specifically, a voltage V may be applied across the second doped region 250 through the test electrodes 291, 292 in the second test cell 200₂And measuring the current I flowing through the test electrodes 291, 292₂The sheet resistance Rs2 of the second doped region 250 is obtained according to equation (5).

Wherein, W₂Is the width, L, of the second doped region 250₂Which is the separation distance between two conductive plugs 270, both are known design values.

Since the sheet resistance Rs2 of the second doped region 250 is the same as the sheet resistance Rs1 of the heavily doped region in the first test cell 100, Rs1 in equation (4) may be replaced with Rs 2.

Fig. 7 shows a top view of a first test unit of a second embodiment of the present disclosure, fig. 8 shows a cross-sectional view taken along line AA in fig. 7, and fig. 9 shows a cross-sectional view taken along line BB in fig. 7. In which only a partial structure of the first test unit 100 is shown in fig. 7 for the sake of clarity.

As shown in fig. 7 to 9, the first test unit 100 of the present embodiment includes: the first insulating layer 110, the first dummy gate 121, the second dummy gate 122, the first dummy sidewall 141, the second dummy sidewall 142, the first doped region, the plurality of conductive plugs 170, the plurality of leads 180, the test electrode 193, and the test electrode 194. The structure of the first testing unit 100 of the present embodiment will be described in detail below, wherein the same parts as those of the first embodiment will not be described again.

The first insulating layer 110 is located on the semiconductor layer 101, and the first dummy gate 121, the second dummy gate 122, the first dummy sidewall 141, the second dummy sidewall 142, and the second insulating layer 160 are all located on the surface of the first insulating layer 110. In this embodiment, the material of the first insulating layer 110 may be specifically the same as the material of the gate dielectric layer in the device, such as silicon oxide. In other embodiments, the first insulating layer 110 is used to electrically isolate the semiconductor layer 101 from the first and second dummy gates 121 and 122, respectively, and thus the material of the first insulating layer 110 may also be an insulating material such as silicon nitride or glass phosphate.

In this embodiment, the first doped region includes a lightly doped region 130 and a heavily doped region 150, and the lightly doped region 130 is located in the semiconductor layer 101 between the first dummy gate 121 and the second dummy gate 122 and connected to the heavily doped region 150; specifically, the lightly doped region 130 is located below a portion of the two dummy sidewalls facing each other. The lightly doped region 130 and the heavily doped region 150 have the same doping type, and the doping concentration of the lightly doped region 130 is less than that of the heavily doped region 150.

It should be noted that the lightly doped region 130 in this embodiment is formed in order to keep synchronization with the device manufacturing process on the wafer, so the lightly doped region 130 can be omitted, and in the case of the lightly doped region 130, the first insulating layer 110 can prevent the lightly doped region 130 from being in direct contact with the first dummy gate 121 and the second dummy gate 122 and further being electrically connected to the heavily doped region 150.

In the embodiment, the first test unit 100 includes a first region a1 and a second region a2 surrounding the first region a1, wherein the first insulating layer 110 in the first region a1 is a thin oxide layer, and the first insulating layer 110 in the second region a2 is a thick oxide layer, the thickness of the thin oxide layer is less than that of the thick oxide layer, and the thick oxide layer blocks the doped impurities from entering the semiconductor layer 101. The first insulating layer 110 shown in fig. 7 is a thin oxide layer. The adjoining positions of the first and second regions a1 and a2 are located below the first and second dummy gates 121 and 122, respectively, in the X-axis direction.

The manufacturing process steps corresponding to the first test unit 100 of this embodiment may be compatible with the manufacturing process of the devices on the wafer, and no additional process is required. For example, a thick oxygen layer is grown on the substrate 101 by a thermal oxidation process in synchronization with the device. The thin oxygen layers in this embodiment are formed simultaneously when forming the gate oxide layer (i.e., the gate dielectric layer) of the device. When forming a polysilicon gate of a device, polysilicon is deposited on the surface of the first insulating layer 110 synchronously, and a polysilicon strip is formed by photolithography and etching to obtain a first dummy gate 121 and a second dummy gate 122. Simultaneously with the LDD process of the device, the same process implantation is performed to the regions between the polysilicon strips to obtain lightly doped regions 130. And forming a side wall on the side surface of the polysilicon gate, and simultaneously forming a pseudo side wall on the side surface of the polysilicon strip. And performing source-drain implantation on the device, and simultaneously performing implantation with the same process on the region between the adjacent pseudo side walls to form a heavily doped region 150. And then depositing an insulating layer, carrying out photoetching and etching on the contact hole, and filling the contact hole by using Ti/TiN/W to form the conductive plug. And depositing a first layer of metal, and photoetching and etching. The above steps are repeated to form a plurality of layers of metal, and finally, a test electrode and a PAD (PAD) in the device are formed. Optionally, an insulating protection layer is deposited over the top metal layer and is subjected to photolithography and etching to form a test electrode and a PAD (PAD) in the device.

In the present embodiment, the widths W of the first dummy sidewall 141 and the second dummy sidewall 142 are obtained by using resistors₀For the specific steps, reference may be made to the first embodiment, which is not described herein again.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (10)

1. A test structure of a wafer, the wafer includes a plurality of semiconductor devices, wherein at least one semiconductor device includes a gate and a sidewall that is located at the periphery of the gate, characterized in that, the test structure includes a first test unit, the first test unit includes:

the first dummy gate and the second dummy gate are positioned on the semiconductor layer and are arranged at intervals along a first direction;

the first pseudo side wall is positioned on the periphery of the first pseudo gate, the second pseudo side wall is positioned on the periphery of the second pseudo gate, and at least part of the first pseudo side wall and the second pseudo side wall are arranged oppositely;

the first doping region is positioned in the semiconductor layer and comprises a heavily doped region positioned between the first pseudo side wall and the second pseudo side wall, the heavily doped region comprises two separated contact regions arranged along a second direction, and the cross section of the heavily doped region positioned between the two contact regions is rectangular; and

a first test electrode and a second test electrode electrically connected to two contact regions of the heavily doped region, respectively,

wherein the first direction, the second direction, and a thickness direction of the semiconductor layer are perpendicular to each other.

2. The test structure of claim 1, wherein the first test unit further comprises a first insulating layer on a surface of the semiconductor layer, and the first dummy gate and the second dummy gate are on a surface of the first insulating layer.

3. The test structure of claim 2, wherein the first doped region further comprises a lightly doped region between the first dummy gate and the second dummy gate, the lightly doped region being in contact with the heavily doped region.

4. The test structure of claim 2, wherein the first and second dummy spacers are located on a surface of the first insulating layer.

5. The test structure of claim 2, wherein the first insulating layer is an oxide layer.

6. The test structure of claim 5, wherein the first test cell comprises a first region and a second region surrounding the first region, a thickness of the oxide layer at the first region being less than a thickness of the oxide layer at the second region,

wherein at least the oxide layer over the first doped region is located in the first region.

7. The test structure of claim 6, wherein along the first direction, the first region and the second region are adjacent to each other at positions below the first dummy gate and below the second dummy gate, respectively.

8. The test structure of any one of claims 1 to 7, wherein the first test unit further comprises a second insulating layer covering the first dummy gate, the second dummy gate, the first dummy sidewall spacers, and the second dummy sidewall spacers,

the first test electrode and the second test electrode are both positioned on the surface of the second insulating layer.

9. The test structure of claim 8, wherein the first test unit further comprises:

a plurality of conductive plugs penetrating the second insulating layer; and

a plurality of leads on a surface of the second insulating layer;

the first test electrode and the second test electrode are electrically connected to the two contact regions of the heavily doped region through corresponding leads and conductive plugs respectively.

10. The test structure of any of claims 1-7, further comprising a second test unit separate from the first test unit, the second test unit comprising:

a second doped region in the semiconductor layer; and

a third test electrode and a fourth test electrode electrically connected to the second doped region, respectively,

wherein the square resistance of the second doped region is the same as the square resistance of the heavily doped region.

Images