CN218849422U - Electrical detection structure for monitoring Fin residues in FinFET process - Google Patents
Electrical detection structure for monitoring Fin residues in FinFET process Download PDFInfo
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Abstract
The utility model relates to an electricity that monitors Fin in FinFET technology detects structure, including basement and at least one detecting element, detecting element sets up in the basement; the detection unit comprises a plurality of Fins to be detected, a plurality of grids and a first connection structure. Through setting up a plurality of detecting element on the basement, can realize detecting when a plurality of samples, reduce the detection cost, detect the electric leakage current size of two etching areas on Fin top through electricity and carry out short-term test, simultaneously, judge the validity of two kinds of etching processes through electric leakage current's size, realize the purpose of guiding FinFET production technology improvement with high efficiency.
Description
Technical Field
The utility model belongs to the semiconductor manufacturing yield promotes the field, especially relates to a control Fin remaining electricity in FinFET technology and detects structure.
Background
With the continuous development of large-scale integrated circuit process technology, the integration level of the circuit is continuously improved, and after the process technology node is smaller than 28nm, the traditional planar MOS device tends to be gradually replaced by a three-dimensional fin field effect transistor (FinFET) due to rapid performance degradation. Compared with a planar transistor, a FinFET generally includes a semiconductor substrate, an oxide layer, and a gate structure, where the oxide layer covers a surface of the semiconductor substrate and a portion of a sidewall of the protruding structure, and a portion of the protruding structure that exceeds the oxide layer becomes a Fin (Fin) of the FinFET, the gate structure spans the Fin and covers a top and a sidewall of the Fin, and the gate structure includes a gate dielectric layer and a gate electrode on the gate dielectric layer. For the Fin-FET, the top of the Fin and the parts of the side walls of the two sides, which are contacted with the gate structure, are all channel regions, namely, the Fin is provided with a plurality of gates, so that the driving current is increased, and the device performance is improved.
A very critical step in the FinFET process is the preparation of Fin, which is usually prepared by using self-aligned dual patterning (SADP) and self-aligned quad patterning (SAQP) processes to increase the integration density and the uniformity of the dimensions of the semiconductor device, and the Fin prepared by the process can be uniformly distributed on the wafer. And after the Fin is prepared, preparing an inactive area by using an etching technology of the Fin to realize the isolation from the active area. The etching of Fin is mainly divided into two types, one is used for directly etching Fin, and the other is used for etching Spacer (side wall), and the height of Fin after etching is directly related to the electrical isolation of an active region and the work of a circuit positioned above a passive region. In the advanced process, two etching methods are often used simultaneously to obtain fine microstructures. In the whole FinFET process production, the Fin etching process needs to be monitored, the accuracy of process production is determined by detecting the height of residual Fin, and the purpose of improving the yield of chips is achieved by adjusting the production process.
Currently, the detection of the remaining Fin is mainly performed by optical means such as a Scanning Electron Microscope (SEM) and an Optical Critical Dimension (OCD), and such an optical detection scheme usually takes a long time and is costly, and the amount of the detected sample is limited.
Therefore, an electrical detection structure capable of detecting the height of the residual Fin more quickly and conveniently and meeting the requirement of multi-sample detection is needed to be found for determining the accuracy of process production so as to achieve the aim of accurately and efficiently guiding the improvement of the FinFET production process.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned deficiencies of the prior art, in whole or in part, it is an object of the present invention to: the electrical detection structure for monitoring Fin residues in the FinFET process is provided, a plurality of detection units are arranged on a substrate, so that a plurality of samples can be detected simultaneously, the detection cost is reduced, the magnitude of leakage current of two etching areas at the top end of Fin is quickly detected by electrical detection to obtain an intuitive detection result, the problem of leakage current of Fin residues in the Fin etching process in the production process of the FinFET process is monitored, the effectiveness of two Fin etching processes can be distinguished, and the yield of products is improved.
In order to achieve the above purpose, the utility model provides the following technical scheme: an electrical detection structure for monitoring Fin residues in a FinFET process comprises a substrate and a first detection unit arranged on the substrate, wherein a first leading-out structure is further arranged on the substrate and used for being electrically connected with an external circuit; the first detection unit comprises a plurality of Fins to be detected, a plurality of grids, a second lead-out structure and a first connection structure; forming an etching area in the top end area of the Fin to be tested; the first connecting structure is arranged on the etching area and is electrically connected with the grid electrode closest to the etching area; the etching area is electrically connected with the grid electrode closest to the first connecting structure through the first connecting structure; and the grid electrode connected with the first connecting structure is electrically connected with the second leading-out structure. The technical scheme has the advantages that the first detection unit is arranged on the substrate, and the first connection structure and the grid electrode are arranged in the first detection unit to detect the etching area at the top end of the Fin, so that the electric leakage problem caused by Fin residue can be efficiently and directly monitored; simultaneously the utility model provides a simple structure and easily operation.
The detection device comprises a substrate and a second detection unit arranged on the substrate, wherein a first leading-out structure is arranged on the substrate and is used for being electrically connected with an external circuit; the second detection unit comprises a plurality of Fins to be detected, a plurality of grids, a second lead-out structure, a second connection structure, a third connection structure and a fourth connection structure; forming an etching area in the top end area of the Fin to be tested; the second connecting structure is arranged on the etching area and is electrically connected with the fourth connecting structure through the third connecting structure; the etching area is electrically connected with the fourth connecting structure through the second connecting structure and the third connecting structure; the fourth connecting structure is electrically connected with the second leading-out structure.
The etching area is formed by Fin direct etching; the etching area is formed by a Spacer etching process. Adopt two kinds of etching processes of Fin direct etching and Spacer etching to carry out the sculpture to Fin, two kinds of etching methods use simultaneously in order to obtain meticulous microstructure, simultaneously so as to realize the utility model discloses a to the detection of the leakage current in two different etching areas, can distinguish the validity of two kinds of Fin etching processes.
The electrical detection structure further comprises a third detection unit, wherein the third detection unit comprises a plurality of Fins to be detected, a plurality of grids, a second lead-out structure, a first connection structure and a second connection structure; forming an etching area in the top end area of the Fin to be tested; the first connecting structure is arranged on the Fin etching area or the Spacer etching area and is electrically connected with the grid electrode closest to the first connecting structure; the second connecting structure is arranged on the Fin etching area or the Spacer etching area, is electrically connected with the grid electrode through the first connecting structure, and is electrically connected with the second leading-out structure through the grid electrode connected with the first connecting structure. The technical scheme has the beneficial effects that besides the capability of simultaneously detecting leakage current of the Fin etching area and the Spacer etching area, the connection place of the first connecting structure and the second connecting structure in the third detection unit is subjected to Fin direct etching and Spacer etching two etching processes, the etching depth is deeper, and the measured leakage current can better reflect the leakage problem caused by incomplete Fin etching.
The electrical detection structure further comprises a second detection unit. The technical scheme has the beneficial effects that the first detection unit, the second detection unit and the third detection unit are arranged on the substrate simultaneously, so that the simultaneous detection of different detection units is realized, the detection of the electric leakage conditions of a plurality of etching areas is realized, and the effectiveness of two etching processes is determined by detecting the electric leakage current of the etching areas formed by the two etching processes simultaneously, so that the etching processes can be adjusted in time, and the efficiency is improved.
The electrical detection structure further comprises a third detection unit. Through set up second detecting element and third detecting element simultaneously on the basement, realize utilizing different detecting element to detect simultaneously, realize the detection to a plurality of etching district electric leakage condition, raise the efficiency.
The first connecting structure is a through hole, and the second connecting structure is a through hole.
The fourth connecting structure is located on the M1 metal layer.
The first connecting structure is located on the metal M0 layer.
The second connecting structure is located on the metal M0 layer.
The number of the first connecting structures is multiple; the second connecting structure is multiple. The leakage current of a plurality of etching area positions can be measured by arranging a plurality of first connecting structures and/or second connecting structures, and the detection efficiency is improved.
The electricity detection structure further comprises a voltage source and/or a current source, one end of the voltage source or the current source is electrically connected with the substrate through the first leading-out structure, the other end of the voltage source or the current source is electrically connected with the second leading-out structure, and voltage or current is applied to the detection unit through the second leading-out structure. One end of a voltage source or a current source is electrically connected with the second leading-out structure, and the voltage source or the current source applies voltage or power to the detection unit through the second leading-out structure; the other end is electrically connected to the substrate through the first lead-out structure. Measuring the leakage current amount from the etching region formed by two different processes to the test end, and recording as I 1 、I 2 . When the leakage current is less than 10 -7 When A is in the range, the leakage current is considered to be small, and when the leakage current is more than 10 -7 When A is in, recognizeThe leakage current is large. Leakage current I 2 Less than 10 -7 A and I 1 Greater than 10 -7 A, explaining that the Fin etching process has problems, the Fin etching process needs to be adjusted; on the contrary, when the leakage current I 2 Characterization of smaller leakage current 1 When the characteristic leakage current is large, the Spacer etching process is problematic, and needs to be adjusted. When leakage current I 1 、I 2 Are all greater than 10 -7 A, indicating that the Fin and Spacer etching processes have problems and needing to be adjusted; when leakage current I 1 、I 2 Are all less than 10 -7 And A, indicating that the Fin and Spacer etching processes have no problem and can intuitively reflect the detection result.
Compared with the prior art, the utility model discloses following beneficial effect has at least: through being provided with a plurality of detecting element on the basement, can realize detecting when a plurality of etched areas, reduce the detection cost, can be simply, audio-visually detect the size of the leakage current that Fin of corresponding etched area remained and lead to through adopting this disclosed detection structure to judge the validity of two kinds of etching process through the size of comparison Fin etched area and Spacer etched area leakage current, realize guiding the purpose that FinFET production technology improves with high efficiency.
Drawings
In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required to be used in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings may be obtained based on these drawings without inventive efforts.
Fig. 1 is a schematic plan view of a first embodiment of the present invention.
Fig. 2 is a schematic plan view of a second embodiment of the present invention.
Fig. 3 is a schematic plan view of a third embodiment of the present invention.
Fig. 4 is a schematic plan view of one of the four embodiments of the present invention.
Fig. 5 is a schematic plan view of another embodiment of the present invention.
Reference numerals are as follows: 1-Fin;101-Fin etching area; 102-Spacer etching area; 2-a grid; 3-a first connecting structure; 4-a second connecting structure; 5-a third connecting structure; 6-a fourth connecting structure; 7-a second lead-out structure.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely below, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Example one
As shown in fig. 1, in the present embodiment, an electrical detection structure for monitoring Fin residues in a FinFET process is provided, and the electrical detection structure includes a substrate and a first detection unit, where the first detection unit is disposed on the substrate. The first detection unit comprises a plurality of Fin1 to be detected, a plurality of grid electrodes 2, a second leading-out structure 7 and a first connecting structure 3. And a plurality of Fin1 to be tested are arranged on the substrate in parallel. As shown in fig. 1, the top of the Fin1 to be measured has two different etching regions, a Fin etching region 101 formed by directly etching Fin, and a Spacer etching region 102 formed by a Spacer etching process. In this embodiment, the plurality of gates 2 are arranged in parallel, vertically and cover the plurality of fins 1 to be tested, the first connection structure 3 is a through hole disposed on the Spacer etching region 102 and communicated with the gate 2 closest to the through hole, and the gate 2 is communicated with the second lead-out structure 7.
In this embodiment, the first detection unit further includes a voltage source, one end of the voltage source is connected to the first lead-out structure (not shown) through a substrate pin (not shown), the other end of the voltage source is connected to the second lead-out structure 7, the second lead-out structure 7 is electrically connected to the gate 2, the first connection structure 3 is electrically connected to the gate 2, and a current passes through the second lead-out structure 7 and the gate 2 to apply a voltage to the corresponding etching region through the first connection structure 3.
Example two
In this embodiment, an electrical detection structure for monitoring Fin residues in a FinFET process is provided, as shown in fig. 2, a second detection unit includes a plurality of fins 1 to be detected, a plurality of gates 2, a second lead-out structure 7, a second connection structure 4, a third connection structure 5, and a fourth connection structure 6; and a plurality of Fin1 to be tested are arranged on the substrate in parallel. The top end of Fin1 to be measured is provided with two different etching areas, a Fin etching area 101 and a Spacer etching area 102. In this embodiment, the gate 2 is vertical and covers a plurality of fins 1 to be tested, a second connection structure 4 is a through hole in the Fin etching region 101 of the Fin1 to be tested, a third connection structure 5 is further disposed on the second connection structure 4, the fourth connection structure 6 is electrically connected to the second connection structure 4 through the third connection structure 5, and the fourth connection structure 6 is connected to a second lead-out structure (not shown in the figure).
In this embodiment, the second detection unit further includes a voltage source, one end of the voltage source is connected to the first lead-out structure through a substrate pin (not shown in the figure), the other end of the voltage source is connected to the second lead-out structure 7, the second lead-out structure 7 is electrically connected to the fourth connection structure 6, the second connection structure 4 is electrically connected to the fourth connection structure 6 through the third connection structure 5, and a current passes through the second lead-out structure 7, passes through the fourth connection structure 6 and the third connection structure 5, and applies a voltage to the corresponding Fin etching region to be tested through the second connection structure 4.
EXAMPLE III
In this embodiment, an electrical detection structure for monitoring Fin residues in a FinFET process is provided, as shown in fig. 3, the third detection unit includes a plurality of to-be-detected fins 1, a plurality of gates 2, a second lead-out structure 7, a first connection structure 3, and a second connection structure 4, where the plurality of to-be-detected fins 1 are arranged in parallel on a substrate. The top end of Fin1 to be detected is provided with two different etching areas, a Fin etching area 101 formed by direct etching of Fin, and a Spacer etching area 102 formed by a Spacer etching process. In this embodiment, the plurality of gates 2 are arranged in parallel, vertically cover the plurality of fins 1 to be tested, two second connection structures 4 are respectively disposed on the left and right sides of the Fin etching region 101 of the Fin1 to be tested, and the two second connection structures 4 are distributed on two sides of one gate 2 disposed on the Fin1 to be tested. The Fin etching region 101 is further provided with first connecting structures 3 as through holes, the two first connecting structures 3 are distributed on the upper side and the lower side of the Fin etching region 101, the first connecting structures 3 are communicated with a certain grid 2, one end of each first connecting structure 3 is communicated with the second connecting structure 4 on the left side of the Fin etching region 101, and the other end of each first connecting structure 3 is communicated with the second connecting structure 4 on the right side of the Fin etching region 101.
In this embodiment, the second connection structure 4 is a through hole and is made of a metal material, so as to increase the flowing speed of the current between the second connection structure 4 and the Fin1 to be tested. Of course, in other embodiments, the connection of the external circuit to two different etched regions may be accomplished by one first connection structure 3 and one second connection structure 4 in each detection cell.
In a better way of this embodiment, the first connecting structure 3 is disposed on the Spacer etching region 102 of the Fin1 to be measured, and the Spacer etching region 102 is communicated with the gate 2 closest thereto through the first connecting structure 3, so as to realize that the current flows to the Spacer etching region 102.
In addition, in the embodiment, the first connection structure 3 and the second connection structure 4 are both disposed on the metal M0 layer, which is easy to manufacture and is beneficial to realizing rapid current flow.
In this embodiment, the third detection unit further includes a voltage source, one end of the voltage source is connected to the first lead-out structure through a substrate pin (not shown in the figure), the other end of the voltage source is connected to the second lead-out structure 7, the second lead-out structure 7 is electrically connected to the gate 2, the first connection structure 3 is electrically connected to the gate 2, and a current passes through the second lead-out structure 7 and the plurality of gates 2 to apply a voltage to the Fin etching region 101 through the first connection structure 3 and the second connection structure 4.
In this embodiment, the first connection structure 3 and the second connection structure 4 are arranged to simultaneously detect the leakage current (denoted as I2) of the Fin etching region 101 and the leakage current (denoted as I1) of the Spacer etching region 102, and the sizes of I1 and I2 are compared to determine the in-time adjustment process of the Fin etching and the Spacer etching. Specifically, when the leakage current is less than 10-7A, the leakage current is considered to be small, and when the leakage current is greater than 10-7A, the leakage current is considered to be large. When the leakage current I2 is high and the leakage current I1 is low, the Fin etching process is problematic and needs to be adjusted; when the leakage current I2 is low and the leakage current I1 is high, the Spacer etching process is indicated to have problems and needs to be adjusted; when the leakage currents I1 and I2 are both larger than 10-7A, the problems of the Fin and Spacer etching processes are shown, and the Fin and Spacer etching processes need to be adjusted; when the leakage currents I1 and I2 are both smaller than 10-7A, the Fin and Spacer etching processes have no problem.
Example four
Different from the above three embodiments, in this embodiment, as shown in fig. 4, a plurality of first detection units and second detection units are disposed on a substrate, the first detection units and the second detection units are disposed adjacent to each other or in other arrangement modes capable of achieving the purpose of the present disclosure, and each first detection unit includes a plurality of to-be-detected fins 1, a plurality of gates 2, a second lead-out structure 7, and a first connection structure 3. And a plurality of Fin1 to be tested are arranged on the substrate in parallel. The top end of Fin1 to be detected is provided with two different etching areas, a Fin etching area 101 formed by direct etching of Fin, and a Spacer etching area 102 formed by a Spacer etching process. In this embodiment, the plurality of gates 2 are arranged in parallel, vertically cover the plurality of fins 1 to be tested, the first connection structure 3 is a through hole disposed on the Spacer etching region 102 and communicated with the gate 2 closest to the through hole, and the gate 2 is communicated with the second lead-out structure 7. The second detection unit comprises a plurality of Fins 1 to be detected, a plurality of grids 2, a second leading-out structure 7, a second connecting structure 4, a third connecting structure 5 and a fourth connecting structure 6; and a plurality of Fin1 to be tested are arranged on the substrate in parallel. The top end of Fin1 to be measured is provided with two different etching areas, a Fin etching area 101 and a Spacer etching area 102. In this embodiment, the gate 2 is vertical and covers a plurality of fins 1 to be tested, a second connection structure 4 is a through hole disposed in the Fin etching region 101 of the Fin1 to be tested, a third connection structure 5 is further disposed on the second connection structure 4, the fourth connection structure 6 is electrically connected to the second connection structure 4 through the third connection structure 5, and the fourth connection structure 6 is connected to the second lead-out structure (not shown in the figure).
The first detection unit and the second detection unit are arranged simultaneously, leakage current of a Fin etching area 101 and a Spacer etching area 102 can be detected, effectiveness of two processes of Fin etching and Spacer etching can be judged by judging magnitude of the leakage current of the Fin etching area 101 and the effectiveness of the two processes of the Spacer etching, leakage current of the Fin etching area 101 (marked as I2) and leakage current of the Spacer etching area 102 (marked as I1) can be detected simultaneously by arranging the first connecting structure 3 and the second connecting structure 4, and the processes can be adjusted timely by judging the Fin etching and the Spacer etching by comparing magnitudes of I1 and I2. Specifically, when the leakage current is less than 10-7A, the leakage current is considered to be small, and when the leakage current is greater than 10-7A, the leakage current is considered to be large. When the leakage current I2 is high and the leakage current I1 is low, the Fin etching process is problematic and needs to be adjusted; when the leakage current I2 is low and the leakage current I1 is high, the Spacer etching process is indicated to have problems and needs to be adjusted; when the leakage currents I1 and I2 are both larger than 10-7A, the Fin and Spacer etching processes have problems, and the Fin and Spacer etching processes need to be adjusted; when the leakage currents I1 and I2 are both less than 10-7A, the Fin and Spacer etching processes have no problem.
In some embodiments, as shown in fig. 5, a plurality of first detecting units, second detecting units, and third detecting units are disposed on a substrate, and the arrangement of the first detecting units, the second detecting units, and the third detecting units on the substrate is not limited. The first detection unit comprises a plurality of Fin1 to be detected, a plurality of grid electrodes 2, a second leading-out structure 7 and a first connecting structure 3. And a plurality of Fin1 to be tested are arranged on the substrate in parallel. The top end of Fin1 to be detected is provided with two different etching areas, a Fin etching area 101 formed by direct etching of Fin, and a Spacer etching area 102 formed by a Spacer etching process. The second detection unit comprises a plurality of Fins 1 to be detected, a plurality of grids 2, a second leading-out structure 7, a second connecting structure 4, a third connecting structure 5 and a fourth connecting structure 6; and a plurality of Fin1 to be tested are arranged on the substrate in parallel. The top end of the Fin1 to be detected is provided with two different etching areas, namely a Fin etching area 101 and a Spacer etching area 102. The third detection unit comprises a plurality of Fin1 to be detected, a plurality of grid electrodes 2, a second leading-out structure 7, a first connection structure 3 and a second connection structure 4, wherein the Fin1 to be detected is arranged on the substrate in parallel. The top end of Fin1 to be detected is provided with two different etching areas, a Fin etching area 101 formed by direct etching of Fin, and a Spacer etching area 102 formed by a Spacer etching process. The connection relationship among the units is the same as that in the first, second, and third embodiments, and will not be described again here. Through set up a plurality of different detecting element on the base, realize the detection in many etching district, once detect the multiple electric leakage condition, effectively improve detection efficiency to judge the validity of two kinds of etching processes through the electric leakage current size.
The above description of the embodiments is only intended to facilitate the understanding of the method and the core idea of the present invention. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, the present invention can be further modified and modified, and such modifications and modifications also fall within the scope of the appended claims.
Claims (10)
1. An electrical detection structure for monitoring Fin residues in a FinFET process is characterized by comprising a substrate and a first detection unit arranged on the substrate, wherein a first leading-out structure is arranged on the substrate and is used for being electrically connected with an external circuit; the first detection unit comprises a plurality of Fins to be detected, a plurality of grids, a second lead-out structure and a first connection structure; forming an etching area in the top end area of the Fin to be tested; the first connecting structure is arranged on the etching area and is electrically connected with the grid electrode closest to the etching area; the etching area is electrically connected with the grid electrode closest to the first connecting structure through the first connecting structure; and the grid electrode connected with the first connecting structure is electrically connected with the second leading-out structure.
2. The electrical detection structure for monitoring Fin residues in a FinFET process of claim 1, further comprising a second detection unit.
3. The electrical detection structure for monitoring Fin residues in a FinFET process of claim 1, further comprising a third detection unit.
4. The electrical detection structure for monitoring Fin residues in a FinFET process of claim 1, wherein the first connection structure is a plurality of through holes.
5. An electrical detection structure for monitoring Fin residues in a FinFET process is characterized by comprising a substrate and a second detection unit arranged on the substrate, wherein a first leading-out structure is arranged on the substrate and is used for being electrically connected with an external circuit; the second detection unit comprises a plurality of Fins to be detected, a plurality of grids, a second lead-out structure, a second connection structure, a third connection structure and a fourth connection structure; forming an etching area in the top end area of the Fin to be tested; the second connecting structure is arranged on the etching area and is electrically connected with the fourth connecting structure through the third connecting structure; the etching area is electrically connected with the fourth connecting structure through the second connecting structure and the third connecting structure; the fourth connecting structure is electrically connected with the second leading-out structure.
6. The electrical detection structure for monitoring Fin residue in FinFET process of claim 1 or 5, wherein said etched region is formed by direct etching of Fin.
7. The electrical detection structure for monitoring Fin residues in a FinFET process of claim 1 or 5, wherein the etched region is formed by a Spacer etching process.
8. The electrical detection structure for monitoring Fin residues in the FinFET process according to claim 1 or 5, wherein the electrical detection structure further comprises a third detection unit, and the third detection unit comprises a plurality of Fins to be detected, a plurality of gates, a second lead-out structure, a first connection structure and a second connection structure; forming an etching area in the top end area of the Fin to be detected; the first connecting structure is arranged on the Fin etching area or the Spacer etching area and is electrically connected with the grid electrode closest to the first connecting structure; the second connecting structure is arranged on the Fin etching area or the Spacer etching area, and is electrically connected with the grid electrode through the first connecting structure, and the grid electrode connected with the first connecting structure is electrically connected with the second leading-out structure.
9. The electrical detection structure for monitoring Fin residues in a FinFET process of claim 1 or claim 5, further comprising a voltage or current source electrically connected to the substrate at one end through the first extraction structure and the second extraction structure at the other end, and applying a voltage or current to the detection cell through the second extraction structure.
10. The electrical detection structure for monitoring Fin residues in a FinFET process of claim 5, wherein the second connection structure is a via, and the second connection structure is a plurality of second connection structures.
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