CN101819974A - Groove type metal oxide semiconductor transistor - Google Patents
Groove type metal oxide semiconductor transistor Download PDFInfo
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- CN101819974A CN101819974A CN201010153755A CN201010153755A CN101819974A CN 101819974 A CN101819974 A CN 101819974A CN 201010153755 A CN201010153755 A CN 201010153755A CN 201010153755 A CN201010153755 A CN 201010153755A CN 101819974 A CN101819974 A CN 101819974A
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Abstract
The invention discloses a groove type metal oxide semiconductor transistor which comprises a semiconductor substrate, an epitaxial layer, channel regions, a plurality of grooves, grid electrodes, grid electrode medium layers, source electrode regions, an insulation layer, source electrode contact jack plugs and grid electrode contact jack plugs, wherein the epitaxial layer and the channel regions are sequentially formed in the semiconductor substrate, the plurality of grooves are formed in the semiconductor substrate, the grid electrodes are formed in the plurality of grooves, each grid electrode medium layer is arranged between each groove and each grid electrode, the source electrode regions are formed in the corresponding channel regions at both sides of the grooves, the insulation layer is formed on the semiconductor substrate, the source electrode contact jack plugs penetrate through the insulation layer and extend into the corresponding source electrode regions and the corresponding channel regions, the grid electrode contact jack plugs penetrate through the insulation layer, and the bottom end surface of each grid electrode contact jack plug is level with the top end surface of the corresponding grid electrode. The invention can enhance the stability of a semiconductor device.
Description
Technical field
The present invention relates to integrated circuit and make the field, particularly relate to a kind of groove type metal oxide semiconductor transistor.
Background technology
At groove type metal oxide semiconductor transistor (Trench Metal Oxide Semiconductor FieldEffect Transistor, MOSFET) or perhaps in the vertical type bipolar transistor (vertical transistor), grid is in the groove that is formed in the Semiconductor substrate, and the source electrode of described groove type metal oxide semiconductor transistor (source) is the both sides that are formed at described grid.In described groove type metal oxide semiconductor transistor, in order to reduce the conducting resistance of its unit are, reduce current loss, the critical size of single groove type metal oxide semiconductor transistor is more and more littler, and the degree of depth of groove is also more and more littler.
Specifically please refer to Fig. 1, it is the schematic diagram of existing a kind of groove type metal oxide semiconductor transistor, as shown in Figure 1, existing a kind of groove type metal oxide semiconductor transistor comprises: Semiconductor substrate 100, epitaxial loayer 110, channel region 120, a plurality of groove 130, a plurality of grid 140, gate dielectric layer 150, source area 160, insulating barrier 170, source electrode contact plunger 180, grid contact plunger 190.Described epitaxial loayer 110 is formed in the Semiconductor substrate 100, described channel region 120 is formed in the Semiconductor substrate 100 and is positioned on the epitaxial loayer 110, described a plurality of groove 130 is formed in the Semiconductor substrate 100, described grid 140 is formed in described a plurality of groove 130, gate dielectric layer 150 is formed between described groove 130 and the described grid 140, source area 160 is formed in the corresponding channel region 120 and is positioned at described groove 130 both sides, described insulating barrier 170 is formed on the described Semiconductor substrate 100, described insulating barrier 170 comprises oxide layer 171 and is formed at boron-phosphorosilicate glass layer 172 on the oxide layer 171, described source electrode contact plunger 180 runs through insulating barrier 170 and extend in the corresponding source area 160 and in the corresponding channel region 120, described grid contact plunger 190 runs through described insulating barrier 170 and extend into (bottom face of described grid contact plunger 190 is lower than the top end face of corresponding grid 140) in the corresponding grid 140.
Wherein, described source electrode contact plunger 180 and grid contact plunger 190 are to utilize with a photoetching process (utilizing a mask plates) to form, and therefore, the degree of depth of described source electrode contact plunger 180 and grid contact plunger 190 also is identical.Specifically, the formation technology of described source electrode contact plunger 180 and grid contact plunger 190 comprises the steps: at first, on insulating barrier 170, apply photoresist, and carrying out the contact hole photoetching to form the patterning photoresist layer, described patterning photoresist layer has grid contact hole pattern and source electrode contact hole pattern; Then, adopt the mode of dry etching, etching is not patterned photoresist layer covered dielectric layer 170, and to form grid contact hole and source electrode contact hole, described grid contact hole is identical with the degree of depth of source electrode contact hole; Next, depositing metal layers in described source electrode contact hole and grid contact hole is to form source electrode contact plunger 180 and grid contact plunger 190.
Specifically please refer to Fig. 2, it is the schematic diagram of existing another kind of groove type metal oxide semiconductor transistor, detailed, existing another kind of groove type metal oxide semiconductor transistor comprises: Semiconductor substrate 200, epitaxial loayer 210, channel region 220, a plurality of groove 230, a plurality of grid 240, gate dielectric layer 250, source area 260, insulating barrier 270, source electrode contact plunger 280, grid contact plunger 290, described insulating barrier 270 comprise oxide layer 271 and are formed at boron-phosphorosilicate glass layer 272 on the oxide layer 271.Along with the range of application of groove type metal oxide semiconductor transistor is more and more wider, and size of semiconductor device diminishes, as shown in Figure 2, in some semiconductor device application, the degree of depth that needs source electrode contact plunger 280 to stretch into channel region 220 still keeps darker, to reach the purpose that contacts source area and well region simultaneously; The degree of depth of grid contact plunger 290 then needs to reduce, thereby has produced the Technology Need that source electrode contact plunger 280 and grid contact plunger 290 need Twi-lithography technology to form.But, in actual production, find, when producing groove type metal oxide semiconductor transistor shown in Figure 2, because grid contact plunger 290 runs through insulating barrier 270 and extend in the corresponding grid 240, need the long dry etching time, the plasma that this dry etching process is used very easily damages gate dielectric layer 250, influences stability of semiconductor device.
Summary of the invention
The invention provides a kind of groove type metal oxide semiconductor transistor, reduce of the damage of dry etching process ionic medium body, improve stability of semiconductor device gate dielectric layer.
For solving the problems of the technologies described above, the invention provides a kind of groove type metal oxide semiconductor transistor, comprising: Semiconductor substrate; Be formed at epitaxial loayer and channel region in the described Semiconductor substrate successively; Be formed at a plurality of grooves in the described Semiconductor substrate; Be formed at the grid in described a plurality of groove; Be formed at the gate dielectric layer between described groove and the described grid; Be formed in the corresponding channel region and be positioned at the source area of described groove both sides; Be formed at the insulating barrier on the described Semiconductor substrate; Run through insulating barrier and extend in the corresponding source area and the source electrode contact plunger in the corresponding channel region; The grid contact plunger that runs through described insulating barrier, the bottom face of described grid contact plunger flushes with the top end face of pairing grid.
Optionally, in described groove type metal oxide semiconductor transistor, described Semiconductor substrate is the N type semiconductor substrate, and described epitaxial loayer is a N type epitaxial loayer, and the ion implantation concentration of described Semiconductor substrate is higher than the ion implantation concentration of described epitaxial loayer.
Optionally, in described groove type metal oxide semiconductor transistor, described grid is the N type polysilicon bar utmost point.
Optionally, in described groove type metal oxide semiconductor transistor, described Semiconductor substrate is the P type semiconductor substrate, and described epitaxial loayer is a P type epitaxial loayer, and the ion implantation concentration of described Semiconductor substrate is higher than the ion implantation concentration of described epitaxial loayer.
Optionally, in described groove type metal oxide semiconductor transistor, described grid is the P type polysilicon bar utmost point.
Optionally, in described groove type metal oxide semiconductor transistor, described insulating barrier comprises oxide layer and is formed at boron-phosphorosilicate glass layer on the described oxide layer.
Compared with prior art, groove type metal oxide semiconductor transistor of the present invention has the following advantages:
The bottom face of grid contact plunger of the present invention flushes with the top end face of pairing grid, that is to say, in terms of existing technologies, the degree of depth of described grid contact plunger is less, therefore, it is shorter to form the required dry etching time of described grid contact plunger, can reduce the damage of dry etching process ionic medium body to gate dielectric layer, improves stability of semiconductor device.
Description of drawings
Fig. 1 is the schematic diagram of existing a kind of groove type metal oxide semiconductor transistor;
Fig. 2 is the schematic diagram of existing another kind of groove type metal oxide semiconductor transistor;
Fig. 3 is the schematic diagram of the groove type metal oxide semiconductor transistor that the embodiment of the invention provided.
Embodiment
Below in conjunction with generalized section groove type metal oxide semiconductor transistor of the present invention is described in more detail, the preferred embodiments of the present invention have wherein been represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is, a kind of groove type metal oxide semiconductor transistor is provided, the bottom face of the grid contact plunger of described groove type metal oxide semiconductor transistor flushes with the top end face of pairing grid, that is to say, in terms of existing technologies, the degree of depth of described grid contact plunger is less, therefore, it is shorter to form the required dry etching time of described grid contact plunger, can reduce of the damage of dry etching process ionic medium body, improve stability of semiconductor device gate dielectric layer.
Please refer to Fig. 3, it is the schematic diagram of the groove type metal oxide semiconductor transistor that the embodiment of the invention provided, as shown in Figure 3, groove type metal oxide semiconductor transistor comprises: Semiconductor substrate 300, epitaxial loayer 310, channel region 320, a plurality of groove 330, a plurality of grid 340, gate dielectric layer 350, source area 360, insulating barrier 370, source electrode contact plunger 380, grid contact plunger 390.
Described epitaxial loayer 310 is formed in the Semiconductor substrate 300, described channel region 320 is formed in the Semiconductor substrate 300 and is positioned on the epitaxial loayer 310, described a plurality of groove 330 is formed in the Semiconductor substrate 200, described grid 340 is formed in described a plurality of groove 330, gate dielectric layer 350 is formed between described groove 330 and the described grid 340, source area 360 is formed in the corresponding channel region 320 and is positioned at described groove 330 both sides, described insulating barrier 370 is formed on the described Semiconductor substrate 300, described source electrode contact plunger 380 runs through insulating barrier 370 and extend in the corresponding source area 360 and in the corresponding channel region 320, described grid contact plunger 390 runs through described insulating barrier 370, and the bottom face of described grid contact plunger 390 flushes with the top end face of pairing grid 340.Because the bottom face of described grid contact plunger 390 flushes with the top end face of pairing grid, that is to say, in terms of existing technologies, the degree of depth of described grid contact plunger 390 is less, therefore, it is very short to form the required dry etching time of described grid contact plunger 390, can reduce the damage to gate dielectric layer 350 of the plasma that uses in the dry etching process, improves stability of semiconductor device.
In a specific embodiment of the present invention, described source electrode contact plunger 380 and grid contact plunger 390 can utilize Twi-lithography technology (utilizing two mask plates) to form respectively, so that the bottom face of described grid contact plunger 390 flushes with the top end face of pairing grid 340.
In a specific embodiment of the present invention, described Semiconductor substrate 300 is the N type semiconductor substrate, and described epitaxial loayer 310 is a N type epitaxial loayer, and the ion implantation concentration of described Semiconductor substrate 300 is higher than the ion implantation concentration of described epitaxial loayer 310.Accordingly, described grid 340 is the N type polysilicon bar utmost point, and described source area 360 is a N+ type source area, and the ion implantation concentration of described source area 360 is higher than the ion implantation concentration of epitaxial loayer 310.
In another specific embodiment of the present invention, described Semiconductor substrate 300 can also be the P type semiconductor substrate, described epitaxial loayer 310 can also be P type epitaxial loayer, and the ion implantation concentration of described Semiconductor substrate 300 is higher than the ion implantation concentration of described epitaxial loayer 310.Accordingly, described grid 340 is the P type polysilicon bar utmost point, and described source area 360 is a P+ type source area, and the ion implantation concentration of described source area 360 is higher than the ion implantation concentration of epitaxial loayer 310.
In a specific embodiment of the present invention, described insulating barrier 370 comprises oxide layer 371 and is formed at boron-phosphorosilicate glass layer 372 on the oxide layer 371 that the material of described grid oxic horizon 350 is a silicon dioxide.
In sum, the invention provides a kind of groove type metal oxide semiconductor transistor, the bottom face of the grid contact plunger of described groove type metal oxide semiconductor transistor flushes with the top end face of pairing grid, that is to say, in terms of existing technologies, the degree of depth of described grid contact plunger is less, therefore, it is shorter to form the required dry etching time of described grid contact plunger, can reduce of the damage of dry etching process ionic medium body, improve stability of semiconductor device gate dielectric layer.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (6)
1. groove type metal oxide semiconductor transistor comprises:
Semiconductor substrate;
Be formed at epitaxial loayer and channel region in the described Semiconductor substrate successively;
Be formed at a plurality of grooves in the described Semiconductor substrate;
Be formed at the grid in described a plurality of groove;
Be formed at the gate dielectric layer between described groove and the described grid;
Be formed in the corresponding channel region and be positioned at the source area of described groove both sides;
Be formed at the insulating barrier on the described Semiconductor substrate;
Run through insulating barrier and extend in the corresponding source area and the source electrode contact plunger in the corresponding channel region;
The grid contact plunger that runs through described insulating barrier, the bottom face of described grid contact plunger flushes with the top end face of pairing grid.
2. groove type metal oxide semiconductor transistor as claimed in claim 1, it is characterized in that, described Semiconductor substrate is the N type semiconductor substrate, and described epitaxial loayer is a N type epitaxial loayer, and the ion implantation concentration of described Semiconductor substrate is higher than the ion implantation concentration of described epitaxial loayer.
3. groove type metal oxide semiconductor transistor as claimed in claim 2 is characterized in that, described grid is the N type polysilicon bar utmost point.
4. groove type metal oxide semiconductor transistor as claimed in claim 1, it is characterized in that, described Semiconductor substrate is the P type semiconductor substrate, and described epitaxial loayer is a P type epitaxial loayer, and the ion implantation concentration of described Semiconductor substrate is higher than the ion implantation concentration of described epitaxial loayer.
5. groove type metal oxide semiconductor transistor as claimed in claim 4 is characterized in that, described grid is the P type polysilicon bar utmost point.
6. groove type metal oxide semiconductor transistor as claimed in claim 1 is characterized in that, described insulating barrier comprises oxide layer and is formed at boron-phosphorosilicate glass layer on the described oxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201010153755.7A CN101819974B (en) | 2010-04-22 | 2010-04-22 | Groove type metal oxide semiconductor transistor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010153755.7A CN101819974B (en) | 2010-04-22 | 2010-04-22 | Groove type metal oxide semiconductor transistor |
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| CN101819974A true CN101819974A (en) | 2010-09-01 |
| CN101819974B CN101819974B (en) | 2015-01-07 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184857A (en) * | 2011-03-29 | 2011-09-14 | 上海宏力半导体制造有限公司 | Method for preparing trench field effect tube |
| CN102779843A (en) * | 2012-07-23 | 2012-11-14 | 上海宏力半导体制造有限公司 | Transistor and forming method thereof |
| CN103413765A (en) * | 2013-08-27 | 2013-11-27 | 矽力杰半导体技术(杭州)有限公司 | Groove MOSFET device and manufacturing method thereof |
| CN109585564A (en) * | 2018-12-26 | 2019-04-05 | 芜湖启迪半导体有限公司 | A kind of silicon carbide MOSFET device and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040012050A1 (en) * | 2002-07-19 | 2004-01-22 | Hitachi, Ltd. | Semiconductor device |
| CN101127351A (en) * | 2006-08-14 | 2008-02-20 | 谢福渊 | Grid contact and conduction channel in high-density groove metal oxide semiconductor field effect transistor (MOSFET) |
| US20090215237A1 (en) * | 2006-08-28 | 2009-08-27 | Advanced Analogic Technologies, Inc. | Method of forming lateral trench MOSFET with direct trench polysilicon contact |
-
2010
- 2010-04-22 CN CN201010153755.7A patent/CN101819974B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040012050A1 (en) * | 2002-07-19 | 2004-01-22 | Hitachi, Ltd. | Semiconductor device |
| CN101127351A (en) * | 2006-08-14 | 2008-02-20 | 谢福渊 | Grid contact and conduction channel in high-density groove metal oxide semiconductor field effect transistor (MOSFET) |
| US20090215237A1 (en) * | 2006-08-28 | 2009-08-27 | Advanced Analogic Technologies, Inc. | Method of forming lateral trench MOSFET with direct trench polysilicon contact |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184857A (en) * | 2011-03-29 | 2011-09-14 | 上海宏力半导体制造有限公司 | Method for preparing trench field effect tube |
| CN102779843A (en) * | 2012-07-23 | 2012-11-14 | 上海宏力半导体制造有限公司 | Transistor and forming method thereof |
| CN103413765A (en) * | 2013-08-27 | 2013-11-27 | 矽力杰半导体技术(杭州)有限公司 | Groove MOSFET device and manufacturing method thereof |
| CN103413765B (en) * | 2013-08-27 | 2016-08-10 | 矽力杰半导体技术(杭州)有限公司 | Groove MOSFET device and preparation method thereof |
| CN109585564A (en) * | 2018-12-26 | 2019-04-05 | 芜湖启迪半导体有限公司 | A kind of silicon carbide MOSFET device and preparation method thereof |
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| Publication number | Publication date |
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| CN101819974B (en) | 2015-01-07 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140514 |
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