CN105448973A - Well resistor structure and manufacturing method thereof and silicon device on insulator - Google Patents
Well resistor structure and manufacturing method thereof and silicon device on insulator Download PDFInfo
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- CN105448973A CN105448973A CN201410407727.1A CN201410407727A CN105448973A CN 105448973 A CN105448973 A CN 105448973A CN 201410407727 A CN201410407727 A CN 201410407727A CN 105448973 A CN105448973 A CN 105448973A
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- well region
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- insulating barrier
- electric resistance
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Abstract
The invention relates to a well resistor structure, including an insulating layer and an active region on the insulating layer. The active region includes a well region, and also includes a trench isolation structure extending downwards to the insulating layer, and the trench isolation structure surrounds the well region in a transverse direction and separates the well region in a vertical direction; and the well resistor structure also includes a metal contact which is arranged on the well region and is in contact with the well region. The invention also relates to a manufacturing method of the well resistor structure and a silicon device on an insulator. According to the well resistor structure provided by the invention, the trench isolation structure is formed in the active region, so that the well region is blocked by the trench isolation structure in the transverse direction, transverse diffusion of majority carriers is not formed, and thus well resistance with a relatively accurate resistance value can be obtained.
Description
Technical field
The present invention relates to semiconductor device, particularly relate to a kind of trap electric resistance structure, a kind of manufacture method of trap electric resistance structure, also relate to a kind of SOI device comprising trap electric resistance structure.
Background technology
In Analog Circuit Design, the error of resistance is generally divided into absolute error and matching error.Generally the absolute error of device can be far longer than the matching error of device.Because the absolute error of resistance is larger, general resistance is all be applied in require in very low circuit to absolute error, general it is considered that the matching precision of resistance during circuit design.For matching precision, generally, polycrystalline resistor is better than trap resistance.This is because the horizontal proliferation of trap is larger, so be difficult under identity unit area obtain more accurate resistance.Therefore usually select polycrystalline resistor during circuit design.
Summary of the invention
Based on this, be necessary to provide a kind of trap electric resistance structure that can obtain resistance value more accurately.
A kind of trap electric resistance structure, comprise the active area on insulating barrier and insulating barrier, described active area comprises well region, described active area also comprises the groove isolation construction extending downward described insulating barrier, and described well region surrounds by described groove isolation construction in the horizontal, on vertical, described well region is separated; Described trap electric resistance structure also comprises to be located on well region and the hard contact contacted with well region.
Wherein in an embodiment, described well region makes cross section be straight strip or serpentine structure because being separated by groove isolation construction.
Wherein in an embodiment, the two ends of every bar trap resistance are provided with hard contact described in a group, and the quantity often organizing hard contact is two or more.
Wherein in an embodiment, described insulating barrier is oxygen buried layer.
There is a need to provide a kind of SOI device.
A kind of SOI device, comprise aforesaid trap electric resistance structure, described insulating barrier is oxygen buried layer.
There is a need to the manufacture method that a kind of trap electric resistance structure is provided, comprise the following steps: to provide the substrate of the silicon layer be formed with on insulating barrier and insulating barrier; Active area is defined with the photoetching on described silicon layer of active area reticle; Inject reticle photoetching with trap and in described active area, form well region by ion implantation; Etch with the photoetching of deep trench isolation reticle, in described active area, etch the groove extending downward described insulating barrier; Fill insulant in described groove, forms groove isolation construction, and described well region surrounds by described groove isolation construction in the horizontal, on vertical, described well region is separated; Described well region is formed the hard contact contacted with well region.
Wherein in an embodiment, described well region makes cross section be straight strip or serpentine structure because being separated by groove isolation construction.
Wherein in an embodiment, described substrate is the substrate of silicon on insulated substrate.
There is a need to the manufacture method that another kind of trap electric resistance structure is provided, comprise the following steps: to provide the substrate of the silicon layer be formed with on insulating barrier and insulating barrier; Active area is defined with the photoetching on described silicon layer of active area reticle; Etch with the photoetching of deep trench isolation reticle, in described active area, etch the groove extending downward described insulating barrier; Fill insulant in described groove, forms groove isolation construction; Inject reticle photoetching with trap and in described active area, form well region by ion implantation, described well region surrounds by described well region in the horizontal, being separated by described groove isolation construction on vertical; Described well region is formed the hard contact contacted with well region.
Wherein in an embodiment, described well region makes cross section be straight strip or serpentine structure because being separated by groove isolation construction.
Above-mentioned trap electric resistance structure, by forming groove isolation construction in active area region, make well region in the horizontal stop by groove isolation construction, the horizontal proliferation of majority carrier can not be formed, therefore can obtain resistance value trap resistance more accurately.
Accompanying drawing explanation
By the more specifically explanation of the preferred embodiments of the present invention shown in accompanying drawing, above-mentioned and other object of the present invention, Characteristics and advantages will become more clear.Reference numeral identical in whole accompanying drawing indicates identical part, and does not deliberately draw accompanying drawing by actual size equal proportion convergent-divergent, focuses on purport of the present invention is shown.
Fig. 1 is the vertical view of trap electric resistance structure in an embodiment;
Fig. 2 is the vertical view of trap electric resistance structure in another embodiment;
Fig. 3 is the cutaway view of the electric resistance structure of trap shown in Fig. 2 along A-A line;
Fig. 4 is the flow chart of the manufacture method of trap electric resistance structure in an embodiment;
Fig. 5 is the flow chart of the manufacture method of trap electric resistance structure in another embodiment.
Embodiment
For enabling object of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Fig. 1 is the vertical view of trap electric resistance structure in an embodiment.Comprise the active area 10 on insulating barrier (Fig. 1 does not show) and insulating barrier.Active area 10 comprises well region 14 and extends downward the groove isolation construction 12 of insulating barrier.Well region 14 surrounds by groove isolation construction 12 in the horizontal, on vertical, well region 14 is separated.That is, the degree of depth of groove isolation construction 12 is at least the same with well region 14, thus makes well region 14 cannot cross groove isolation construction 12 to horizontal expansion in the position being provided with groove isolation construction 12.The cross section of well region 14 is strip, this strip can be as shown in Figure 1 vertical, without bending, directly rectangular without bending, also can be the rectangular of bending structure as 9-section whip.Trap electric resistance structure also comprises to be located on well region 14 and the hard contact 16 contacted with well region 14, and hard contact 16 is arranged at the two ends of each resistance.
Above-mentioned trap electric resistance structure, by forming groove isolation construction 12 in active area region, make well region 14 in the horizontal stop by groove isolation construction 12, the horizontal proliferation of majority carrier can not be formed, therefore can obtain resistance value trap resistance more accurately.
Above-mentioned trap electric resistance structure can be applied in the device of silicon-on-insulator (SOI) technique, and insulating barrier is oxygen buried layer.Understandable, in the active area of device, many resistance can be set, and be not limited to shown in Fig. 1.
Fig. 2 is the vertical view of trap electric resistance structure in another embodiment, and Fig. 3 is the cutaway view of Fig. 2 along A-A direction.Trap electric resistance structure comprises the active area 20 field oxide structure of both sides, active area 20 (in the not shown Fig. 3 of Fig. 2) that insulating barrier 30 and insulating barrier 30 are defined by field oxide structure.Active area 20 comprises well region 24 and extends downward the groove isolation construction 22 of insulating barrier 30.In the present embodiment, by shape and the position of appropriate design groove isolation construction 22, make it be separated by well region 24, form cross section in the well region structure of crawling.According to common practise, the resistance value computing formula of the resistance of box structure is: R=(ρ/h) * (L/W)
Wherein ρ is resistivity, and h is the degree of depth of box structure, and L is the length of box structure, and W is the width of box structure.The trap resistance of the serpentine structure shown in Fig. 2, the L that can be grown very much in limited device area and very narrow W, therefore can obtain the resistance of high value, meets the application of high resistant completely.
Fig. 2, embodiment illustrated in fig. 3 in, the two ends of a trap resistance are respectively provided with one group of hard contact 26, and often organizing the quantity of hard contact 26 is two or more (being 4) in the present embodiment.The quantity increasing hard contact 26 can reduce the contact resistance of contact area ohmic contact, is conducive to the reliability ensureing device in addition.
Fig. 4 is the flow chart of the manufacture method of trap electric resistance structure in an embodiment, comprises the following steps:
S110, provides the substrate of the silicon layer be formed with on insulating barrier and insulating barrier.
In the present embodiment, substrate is the substrate of silicon-on-insulator (SOI) structure, and insulating barrier is oxygen buried layer.
S120, defines active area with the photoetching on silicon layer of active area reticle.
S130, injects reticle photoetching with trap and in active area, forms well region by ion implantation.
S140, etches with the photoetching of deep trench isolation reticle, etches the groove extending downward insulating barrier in active area.
S150, fill insulant in groove, forms groove isolation construction.
Adopt deep trench isolation technique Formation Depth at least the same with well region, thus by separated for well region deep trouth on vertically.The cross section of well region is strip.In the present embodiment, be first in deep trouth, form oxide layer, then fill polysilicon in deep trouth after etching deep trouth (groove).The oxidized layer of polysilicon in deep trouth stops thus directly can not contact with well region.
S160, well region is formed the hard contact contacted with well region.
Hard contact is arranged at the two ends of each resistance.
The manufacture method of above-mentioned trap electric resistance structure, defines suitable channel patterns by rational layout design, is defined the shape of trap resistance by groove isolation construction.Due to the stop of groove isolation construction, the horizontal proliferation of majority carrier can not be formed, therefore can obtain resistance value trap resistance more accurately.
By layout design make trap resistance be formed shape that cross section is as shown in Figure 2 serpentine structure, the resistance of high value can be obtained, meet the application of high resistant.Adopt said method to manufacture trap resistance, additionally can not increase the quantity of reticle, relative to need extra increase by one piece of definition high resistance region reticle and increase the polycrystalline resistor structure of one high resistance implantation step, can process costs be saved.Because SOI technology material cost is higher, the manufacture method of the above-mentioned trap electric resistance structure that photoetching level is less, processing step is more simplified is more competitive.
Embodiment illustrated in fig. 4 is first do trap to inject, then does deep trench isolation.In another embodiment, also first can do deep trench isolation, then do trap injection, as shown in Figure 5:
S210, provides the substrate of the silicon layer be formed with on insulating barrier and insulating barrier.
S220, defines active area with the photoetching on silicon layer of active area reticle.
S230, etches with the photoetching of deep trench isolation reticle, etches the groove extending downward insulating barrier in active area.
S240, fill insulant in groove, forms groove isolation construction.
S250, injects reticle photoetching with trap and in active area, forms well region by ion implantation.
S260, well region is formed the hard contact contacted with well region.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a trap electric resistance structure, comprise the active area on insulating barrier and insulating barrier, described active area comprises well region, it is characterized in that, described active area also comprises the groove isolation construction extending downward described insulating barrier, and described well region surrounds by described groove isolation construction in the horizontal, on vertical, described well region is separated; Described trap electric resistance structure also comprises to be located on well region and the hard contact contacted with well region.
2. trap electric resistance structure according to claim 1, is characterized in that, described well region makes cross section be straight strip or serpentine structure because being separated by groove isolation construction.
3. trap electric resistance structure according to claim 1, is characterized in that, the two ends of every bar trap resistance are provided with hard contact described in a group, and the quantity often organizing hard contact is two or more.
4. trap electric resistance structure according to claim 1, is characterized in that, described insulating barrier is oxygen buried layer.
5. a SOI device, is characterized in that, comprise according to the trap electric resistance structure in claim 1-3 described in any one, described insulating barrier is oxygen buried layer.
6. a manufacture method for trap electric resistance structure, comprises the following steps:
The substrate of the silicon layer be formed on insulating barrier and insulating barrier is provided;
Active area is defined with the photoetching on described silicon layer of active area reticle;
Inject reticle photoetching with trap and in described active area, form well region by ion implantation;
Etch with the photoetching of deep trench isolation reticle, in described active area, etch the groove extending downward described insulating barrier;
Fill insulant in described groove, forms groove isolation construction, and described well region surrounds by described groove isolation construction in the horizontal, on vertical, described well region is separated;
Described well region is formed the hard contact contacted with well region.
7. the manufacture method of trap electric resistance structure according to claim 6, is characterized in that, described well region makes cross section be straight strip or serpentine structure because being separated by groove isolation construction.
8. the manufacture method of trap electric resistance structure according to claim 6, is characterized in that, described substrate is the substrate of silicon on insulated substrate.
9. a manufacture method for trap electric resistance structure, comprises the following steps:
The substrate of the silicon layer be formed on insulating barrier and insulating barrier is provided;
Active area is defined with the photoetching on described silicon layer of active area reticle;
Etch with the photoetching of deep trench isolation reticle, in described active area, etch the groove extending downward described insulating barrier;
Fill insulant in described groove, forms groove isolation construction;
Inject reticle photoetching form well region by ion implantation in described active area with trap, described well region surrounds by described well region in the horizontal, separated by described groove isolation construction on vertical and make cross section be strip;
Described well region is formed the hard contact contacted with well region.
10. the manufacture method of trap electric resistance structure according to claim 9, is characterized in that, described well region makes cross section be straight strip or serpentine structure because being separated by groove isolation construction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410407727.1A CN105448973A (en) | 2014-08-18 | 2014-08-18 | Well resistor structure and manufacturing method thereof and silicon device on insulator |
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| CN201410407727.1A CN105448973A (en) | 2014-08-18 | 2014-08-18 | Well resistor structure and manufacturing method thereof and silicon device on insulator |
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| CN105448973A true CN105448973A (en) | 2016-03-30 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106803501A (en) * | 2017-02-08 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | Pore chain resistance |
| CN108511422A (en) * | 2017-02-28 | 2018-09-07 | 意法半导体(克洛尔2)公司 | Integrated circuit with improved resistance region |
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Cited By (4)
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| CN106803501A (en) * | 2017-02-08 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | Pore chain resistance |
| CN106803501B (en) * | 2017-02-08 | 2019-08-13 | 上海华虹宏力半导体制造有限公司 | Pore chain resistance |
| CN108511422A (en) * | 2017-02-28 | 2018-09-07 | 意法半导体(克洛尔2)公司 | Integrated circuit with improved resistance region |
| CN108511422B (en) * | 2017-02-28 | 2021-11-12 | 意法半导体(克洛尔2)公司 | Integrated circuit with improved resistance area |
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Effective date of registration: 20170927 Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Applicant after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Applicant before: Wuxi CSMC Semiconductor Co., Ltd. |
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Application publication date: 20160330 |