CN214099585U

CN214099585U - Fin height test structure in FinFET integrated circuit manufacturing process

Info

Publication number: CN214099585U
Application number: CN202022940754.9U
Authority: CN
Inventors: 张飞虎
Original assignee: Hangzhou Guangli Microelectronics Co ltd
Current assignee: Hangzhou Guangli Microelectronics Co ltd
Priority date: 2020-12-10
Filing date: 2020-12-10
Publication date: 2021-08-31
Anticipated expiration: 2030-12-10

Abstract

The utility model relates to a Fin height test structure in FinFET integrated circuit manufacturing process, which comprises at least one basic unit; the basic unit comprises a substrate, a Fin to be tested, a grid to be tested and an isolation layer; embedding Fin to be tested in the isolation layer; the isolating layer is horizontally arranged on the upper surface of the substrate, and the thickness of the isolating layer is the distance between the polar plates; the grid electrode to be tested is arranged on the upper surface of the isolation layer, and the substrate, the isolation layer and the grid electrode to be tested form a parallel plate capacitor structure. The utility model discloses a test structure of Fin height in FinFET integrated circuit manufacturing process, structural design is simple, easily makes, can monitor the height of Fin among the FinFET manufacturing process simply effectively, has played very important effect to the stability control of manufacturing process.

Description

Fin height test structure in FinFET integrated circuit manufacturing process

Technical Field

The utility model belongs to the semiconductor manufacturing field relates to a test structure, especially a test structure of Fin height among FinFET integrated circuit manufacturing process.

Background

With the continuous development of Integrated Circuit (IC) processes, when the feature size is smaller than 22nm, the conventional planar transistor has the problems of significantly increased short channel effect, sharply increased leakage current, reduced mobility, and the like. Under such circumstances, new devices of various new structures and new materials have been developed, and the most advanced IC processes employ finfets instead of the conventional planar MOSFETs because they have excellent short channel resistance, reduce sub-threshold leakage current, and can reduce the influence of process variations on device performance. The FinFET is of a three-dimensional structure, the space advantage is fully utilized, the opening and judgment of the channel can be controlled in multiple directions on multiple side faces of the three-dimensional gate, and the gate of the FinFET is of a fin-shaped 3D three-dimensional structure. FinFET is because its three-dimensional structure, the same effective channel width, and the source drain area of FinFET is littleer than planar MOSFET's source drain area, therefore can link together more closely between the transistor, can place more FinFET transistors on the chip of same area, and FinFET transistor density has improved 21% than traditional planar MOSFET. The FinFET process not only improves the integration level of the integrated circuit, but also greatly improves the performance.

While FinFET devices are the best choice for sub-22 nm processes, process control becomes more complex with many challenges due to the nature of fabrication at the nanometer level. The width and height of the Fin (Fin) must be ensured to be consistent in the FinFET manufacturing process, otherwise performance parameters such as threshold voltage of the device are affected, and the performance parameters of each transistor in the circuit are greatly different from each other. Therefore, the width and height conditions of Fin in the FinFET manufacturing process are monitored, the FinFET production process can be effectively guided, and the performance of the device is greatly improved.

The Fin height is directly related to the depth of the oxide Trench in the Short Trench Isolation (STI) region, and the depth is affected by many factors, such as: STI oxide filling process, STI-CMP, Fin density, Fin oxide groove, etc., the variation of Fin height on the wafer can cause the deterioration of Idsat uniformity inside the silicon wafer. Currently, the measurement of the Fin height is mainly monitored by Optical Critical Dimension (OCD) measurement or TEM slicing, wherein the measurement accuracy of the OCD technology highly depends on the optical hardware structure, the spectrum type and the inherent interaction between the incident light and various materials with different topological structures, and the OCD can only measure a specific structure, and the establishment of OCD lib is troublesome; the TEM sectioning method can only monitor one sample periodically, for example, a week, and has the disadvantages of high monitoring cost, small sample amount, poor representativeness, and the like.

Therefore, a faster and more convenient monitoring method is needed to measure the Fin height, so as to achieve the purpose of accurately and rapidly guiding the FinFET production process.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a Fin height's test structure in FinFET integrated circuit manufacturing process for the Fin height of technology in the control FinFET production.

In order to achieve the above object, a Fin height test structure in FinFET integrated circuit manufacturing process comprises at least one basic unit; the basic unit comprises a substrate, a Fin to be tested, a grid to be tested and an isolation layer; embedding the Fin to be tested in the isolation layer; the isolating layer is flatly arranged on the upper surface of the substrate, and the thickness of the isolating layer is the distance between the polar plates; the grid electrode to be tested is arranged on the upper surface of the isolation layer; the substrate, the isolation layer and the grid electrode to be tested form a parallel plate capacitor structure. This application is through the capacitor structure who forms as test structure, can be more convenient monitor or measure the Fin height, reach the purpose of accurate quick instruction FinFET production technology.

The basic unit can comprise a connecting structure, and the connecting structure is connected with the Fin to be tested and/or the grid electrode to be tested, so that the connection test is facilitated. The line width and length requirements of the connecting structure can be adjusted according to actual process requirements, and generally can meet the range of 10-1000 nm.

The basic unit further comprises a voltage source, and the voltage source is respectively connected to the grid electrode to be tested and the connecting structure; the capacitance value of the capacitor structure is measured after the capacitor structure reaches charge balance by applying voltage to the parallel plate capacitor structure formed by the substrate, the isolation layer and the grid electrode to be measured.

In the application, the number of Fins to be tested is not limited, and the range can be met: 1 to 200 pieces. Similarly, the line width and length of the gate to be tested, the distance between the gates to be tested, and the like can be determined according to the actual process requirements of the semiconductor, and generally satisfy the following ranges: 10 to 1000 nm.

Preferably, the basic unit further comprises an auxiliary gate, and the auxiliary gate crosses over the Fin to be tested; the test interference can be reduced, and the stability of the test result is higher. Preferably, the line width and length of the auxiliary gate satisfy the range: 10 to 1000 nm.

The number of the basic units in the test structure does not limit the number of the basic units to meet the range: 1 to 10 ten thousand. A plurality of different or same basic units can be connected in series or in parallel for testing, and the stability and the accuracy of capacitance testing can be improved.

The utility model discloses a test structure of Fin height among FinFET integrated circuit manufacturing process compares with prior art and has following advantage:

the FinFET integrated circuit manufacturing process Fin height test structure is simple in structural design and easy to manufacture, the FinFET integrated circuit manufacturing process Fin height can be simply and effectively monitored, the Fin heights of different positions can be monitored in the same wafer, and then the semiconductor production process is guided, so that the product performance is greatly improved, and the FinFET integrated circuit manufacturing process Fin height test structure plays an important role in monitoring the stability of the manufacturing process.

Drawings

FIG. 1 is a top view of a test structure for Fin height in a FinFET integrated circuit fabrication process according to an embodiment;

FIG. 2 is a cross-sectional view of a test structure for Fin height in a FinFET integrated circuit fabrication process according to the present embodiment;

reference numerals:

1. a connecting structure; 2. an auxiliary gate; 3. a grid to be tested; 4. fin to be detected; 5. an isolation layer; 6. a substrate.

Detailed Description

The present invention will be further described with reference to the accompanying drawings and specific embodiments.

Examples

As shown in fig. 1-2, a Fin height test structure in a FinFET integrated circuit manufacturing process includes two basic units, each of which includes a substrate 6, a Fin4 to be tested, a gate 3 to be tested, an auxiliary gate 2, an isolation layer 5, and a connection structure 1; the Fin4 to be tested is embedded in the isolation layer 5; the auxiliary grid 5 crosses the Fin4 to be tested; the isolation layer 5 is horizontally arranged on the upper surface of the substrate 6, the thickness of the isolation layer is the distance of the polar plate, and the upper surface of the isolation layer 5 is flush with the bottom surface of the auxiliary grid 5; the gate 3 to be tested is arranged on the upper surface of the isolation layer 5; two connecting structures 1 are provided, are connected with Fin4 to be tested and can lead out Fin for communication test; the substrate 6, the isolation layer 5 and the gate 3 to be tested form a parallel plate capacitor structure. The number of Fin4 to be detected ranges: 1 ~ 200, 3 line width and length value ranges of the grid that awaits measuring: 10-1000nm, the auxiliary gate 2 line width and length value range: 10-1000nm, and the distance between the to-be-detected grid electrodes 3 ranges: 10-1000nm, the line width and length of the connecting structure 1 have value ranges: 10 to 1000 nm. The test structure is externally connected with a voltage source, and the grid electrode 3 to be tested and the connecting structure 1 are respectively connected with the anode and the cathode of the voltage source.

Based on the test structure, a voltage source applies certain voltage excitation to the basic unit, the capacitance value is tested and measured after the charge balance, and a capacitance calculation formula is used

Obtaining the distance between the polar plates:

wherein: the capacitance value C can be obtained through testing, epsilon is a constant, s is the area of the grid electrode to be tested, and d is the distance between the polar plates. And obtaining a Fin height value which is the Fin overall height-pole plate distance d from the pole plate distance, wherein the Fin overall height is a fixed design value.

In some embodiments, the number of elementary units satisfies the range: 1 to 10 ten thousand.

In some embodiments, a plurality of different or same basic units can be connected in series or in parallel for testing, so that the test is more stable and the test structure is more accurate.

While the preferred embodiments of the present invention have been described in detail, it will be understood by those skilled in the art that the invention is not limited thereto, and that various changes and modifications may be made without departing from the spirit of the invention.

Claims

1. A test structure of Fin height in FinFET integrated circuit manufacturing process is characterized by comprising at least one basic unit; the basic unit comprises a substrate, a Fin to be tested, a grid to be tested and an isolation layer; embedding the Fin to be tested in the isolation layer; the isolating layer is flatly arranged on the upper surface of the substrate, and the thickness of the isolating layer is the distance between the polar plates; the grid electrode to be tested is arranged on the upper surface of the isolation layer; the substrate, the isolation layer and the grid electrode to be tested form a parallel plate capacitor structure.

2. The FinFET integrated circuit fabrication process Fin height test structure of claim 1, wherein said base cell further comprises a connection structure to connect to Fin under test and/or to-be-tested gate.

3. The FinFET integrated circuit fabrication process Fin height test structure of claim 2, wherein said base cell further comprises a voltage source connected to the gate under test and the connection structure, respectively.

4. The structure for testing Fin height in FinFET integrated circuit manufacturing process according to claim 1 or 2, wherein an auxiliary gate is further included in the basic unit, and the auxiliary gate crosses Fin to be tested.

5. The test structure of Fin height in FinFET integrated circuit manufacturing process of claim 1 or 2, wherein the number of said basic units satisfies the range: 1 to 10 ten thousand.

6. The FinFET integrated circuit fabrication process Fin height test structure of claim 5, wherein said plurality of different or same basic cells are tested in series or in parallel.

7. The structure of claim 3, wherein the number of Fins to be tested satisfies the range: 1 to 200 pieces.

8. The structure for testing Fin height in FinFET integrated circuit manufacturing process according to claim 1 or 2, wherein the line width and length of the gate to be tested and the distance between the gates to be tested satisfy the following ranges: 10 to 1000 nm.

9. The test structure of Fin height in FinFET integrated circuit fabrication process of claim 2, wherein the line width and length of said connection structure satisfy the range of: 10 to 1000 nm.

10. The test structure of Fin height in FinFET integrated circuit manufacturing process of claim 4, wherein the line width and length of the auxiliary gate satisfy the range of: 10 to 1000 nm.