CN117524898A - Thermal effect device structure, forming method thereof and thermal resistance obtaining method - Google Patents

Thermal effect device structure, forming method thereof and thermal resistance obtaining method Download PDF

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Publication number
CN117524898A
CN117524898A CN202210894040.XA CN202210894040A CN117524898A CN 117524898 A CN117524898 A CN 117524898A CN 202210894040 A CN202210894040 A CN 202210894040A CN 117524898 A CN117524898 A CN 117524898A
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Prior art keywords
gate
transistor
thermal resistance
gate structure
effect device
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Inventor
余开浩
万露红
叶好华
胡梅丽
朱辰东
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202210894040.XA priority Critical patent/CN117524898A/en
Publication of CN117524898A publication Critical patent/CN117524898A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K7/00—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
    • G01K7/16—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors

Abstract

A thermal effect device structure, a method of forming the thermal effect device structure, and a method of obtaining thermal resistance, wherein the thermal effect device structure includes: a substrate comprising a first device region; a first gate structure located on the first device region, the first gate structure comprising a P-type transistor work function layer; the first source-drain region is positioned at two sides of the first grid structure, and N-type doping ions or P-type doping ions are arranged in the first source-drain region. The thermal effect device structure, the forming method of the thermal effect device structure and the thermal resistance obtaining method improve the accuracy of thermal resistance measurement of the transistor.

Description

Thermal effect device structure, forming method thereof and thermal resistance obtaining method
Technical Field
The invention relates to the technical field of semiconductors, in particular to a thermal effect device structure, a forming method of the thermal effect device structure and a thermal resistance obtaining method.
Background
With the development of semiconductor technology, the size of semiconductor devices is continuously reduced, and thus, the size of field effect transistors is reduced, and the integration level of the field effect transistors is increased.
However, the field Effect transistor with high integration has poor thermal conductivity and high structural limitation, which results in serious Self-Heating Effect (SHE) of the device, thereby adversely affecting the performance of the device. Thus, accurate characterization of the self-heating effect of a field effect transistor device is important to obtain device performance.
Thermal resistance (Thermal Resistance) is an important parameter that characterizes the temperature change of the device at different operating powers. In order to ensure accuracy and convenience of measurement, a gate structure in a field effect transistor is often employed as a measurement object. However, in the prior art, the accuracy of the thermal resistance of a portion of the transistor measured by the gate structure remains to be improved.
Disclosure of Invention
The invention solves the technical problem of providing a thermal effect device structure, a forming method of the thermal effect device structure and a thermal resistance acquisition method, and improves the accuracy of thermal resistance measurement of a transistor.
In order to solve the technical problems, the technical scheme of the invention provides a thermal effect device structure, which comprises a substrate, a first electrode and a second electrode, wherein the substrate comprises a first device region; a first gate structure on the first device region, the first gate structure comprising a P-type transistor work function layer and a first gate on the P-type transistor work function layer; the first source-drain region is positioned at two sides of the first grid structure, and N-type doping ions or P-type doping ions are arranged in the first source-drain region.
Optionally, the substrate includes a base and a plurality of fin structures located on the base.
Optionally, the first gate structure spans a top and sidewall surfaces of a portion of the fin structure.
Optionally, the substrate comprises a planar structure.
Optionally, the thermal effect device structure further comprises: and a first gate dielectric layer between the substrate and the first gate structure.
Optionally, the material of the P-type transistor work function layer includes an alloy.
Optionally, the first gate structure includes a gate structure of a PMOS ultra-low threshold voltage transistor.
Optionally, the substrate includes a number of first device regions greater than 1; the first gate structures on the plurality of first device regions are different in length, the number of the first gate structures on the plurality of first device regions is different, or the first gate structures on the plurality of first device regions are different in width, and the plurality of first device regions are provided with reference test regions, wherein the first gate structures in the reference test regions are provided with reference gate lengths, and the reference gate lengths are the minimum values of the first gate structure lengths on the first device regions.
Optionally, the substrate further comprises a second device region.
Optionally, when the first source-drain region has N-type doped ions, the thermal effect device structure further includes: a reference transistor located on the second device region, the reference transistor comprising: a second gate structure comprising an N-type transistor work function layer; the second source-drain regions are positioned on two sides of the second gate structure, N-type doped ions are arranged in the second source-drain regions, and the length of the second gate structure is the length of the reference gate.
Optionally, the material of the N-type transistor work function layer includes an alloy.
Optionally, the thickness of the P-type transistor work function layer is greater than the thickness of the N-type transistor work function layer.
Optionally, when the first source-drain region has P-type doped ions therein, the thermal effect device structure further includes: a reference transistor located on the second device region, the reference transistor comprising: a second gate structure comprising a P-type transistor work function structure having a thickness different from a thickness of the P-type transistor work function layer of the first gate structure; the second source-drain regions are positioned on two sides of the second gate structure, P-type doped ions are arranged in the second source-drain regions, and the length of the second gate structure is the length of the reference gate.
Correspondingly, the technical scheme of the invention also provides a method for forming the thermal effect device structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a first device region; forming a first gate structure on the first device region, the first gate structure including a P-type transistor work function layer; and forming a first source drain region at two sides of the first grid structure, wherein N-type doping ions or P-type doping ions are arranged in the first source drain region.
Correspondingly, the technical scheme of the invention also provides a thermal resistance acquisition method, which comprises the following steps: providing a thermal effect device structure, the thermal effect device structure comprising: the semiconductor device comprises a substrate, a first semiconductor layer and a second semiconductor layer, wherein the substrate comprises a plurality of first device areas and second device areas; the first grid structures are positioned on the first device regions and comprise P-type transistor work function layers, the lengths of the first grid structures on the first device regions are different, the number of the first grid structures on the first device regions is different or the widths of the first grid structures on the first device regions are different, a reference test region is arranged in the first device regions, the first grid structures on the reference test region have a reference grid length, and the reference grid length is the minimum value of the first grid structure lengths on the first device regions; the first source-drain regions are positioned at two sides of each first gate structure and are internally provided with N-type doping ions or P-type doping ions; a reference transistor located on the second device region, the reference transistor comprising a second gate structure, the second gate structure having a length that is the reference gate length; acquiring first thermal resistance values corresponding to the first grid structures by adopting a thermal resistance measurement method, wherein the first thermal resistance values corresponding to the first grid structures on the reference test area are first reference thermal resistance values; acquiring an initial second thermal resistance value of the reference transistor by adopting a thermal resistance measurement method; acquiring a thermal resistance offset, wherein the thermal resistance offset is the difference value between a first reference thermal resistance and an initial second thermal resistance; and adding the first thermal resistance values and the thermal resistance value offset to obtain second thermal resistance values corresponding to the first grid structures on the first device regions.
Optionally, when the first source-drain region of the thermal effect device structure has N-type doped ions, the second gate structure of the reference transistor includes an N-type transistor work function layer; the thickness of the P-type transistor work function layer is larger than that of the N-type transistor work function layer.
Optionally, the material of the P-type transistor work function layer comprises an alloy; the material of the N-type transistor work function layer comprises an alloy.
Optionally, the thermal resistance measurement method used for obtaining the first thermal resistance value corresponding to each first gate structure includes: heating the thermal effect device structure for a plurality of times to reach a plurality of test temperatures, and respectively obtaining first unit resistance values of the first grid structure corresponding to the test temperatures by applying first voltages to two ends of the first grid structure; acquiring the temperature resistance coefficient of the first grid structure according to each first unit resistance value and each test temperature; the thermal effect device structure is enabled to be in a plurality of working powers, and a second unit resistance value of the first grid structure corresponding to each working power is obtained; acquiring the working temperature increment of the first grid structure corresponding to each working power according to each second unit resistance value and the temperature resistance coefficient; and acquiring a first thermal resistance value corresponding to the first grid structure according to each working power and each working temperature increment of the first grid structure.
Optionally, when the first source drain region of the thermal effect device structure has an N-type doped ion, the reference transistor includes an NMOS standard threshold voltage transistor, an NMOS low threshold voltage transistor, or an NMOS ultra-low threshold voltage transistor.
Optionally, the length of the reference grid ranges from 2 nanometers to 14 nanometers.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the thermal effect device structure provided by the technical scheme of the invention, the first gate structure on the first device region comprises a P-type transistor work function layer, and the first source/drain region is internally provided with N-type doping ions or P-type doping ions. When the first source drain region is provided with N-type doping ions, the transistor on the first device region combines a PMOS grid structure and other transistor structures of NMOS at the same time, so that a special NMOS thermal effect device structure is formed. The first gate structure comprises a P-type transistor work function layer, and the P-type transistor work function layer is more sensitive to temperature, so that the first gate structure is more sensitive to temperature change. When the transistor structure on the first device region works, the special NMOS thermal effect device structure can accurately measure the temperature change through the first grid structure of the special NMOS thermal effect device structure while playing the NMOS function, so that the accuracy of the subsequent thermal resistance measurement is improved. Similarly, by selecting the P-type transistor work function layer which is more sensitive to temperature from the first grid structure, a special PMOS thermal effect device structure can be formed when the P-type doped ions are arranged in the first source drain region, so that the accuracy of thermal resistance measurement of the corresponding PMOS transistor is improved.
Further, the first gate structure includes a gate structure of a PMOS ultra-low threshold voltage transistor. Compared with other PMOS transistors, the temperature resistance coefficient of the PMOS ultralow threshold voltage transistor is larger, so that more accurate temperature change can be obtained in the measurement process of the thermal resistance, and the measurement accuracy of the thermal resistance is higher.
In the method for forming the thermal effect device structure provided by the technical scheme of the invention, the first grid structure formed on the first device region comprises a P-type transistor work function layer, and the formed first source/drain region is internally provided with N-type doping ions or P-type doping ions. When the first source drain region is provided with N-type doping ions, the transistor on the first device region combines a PMOS grid structure and other transistor structures of NMOS at the same time, so that a special NMOS thermal effect device structure is formed. The first gate structure comprises a P-type transistor work function layer, and the P-type transistor work function layer is more sensitive to temperature, so that the first gate structure is more sensitive to temperature change. When the transistor structure on the first device region works, the special NMOS thermal effect device structure can accurately measure the temperature change through the first grid structure of the special NMOS thermal effect device structure while playing the NMOS function, so that the accuracy of the subsequent thermal resistance measurement is improved. Similarly, by selecting the P-type transistor work function layer which is more sensitive to temperature from the first grid structure, a special PMOS thermal effect device structure can be formed when the P-type doped ions are arranged in the first source drain region, so that the accuracy of thermal resistance measurement of the corresponding PMOS transistor is improved.
According to the thermal resistance obtaining method provided by the technical scheme of the invention, when N-type doped ions are arranged in the first source-drain region in the thermal effect device structure, the first thermal resistance values of special NMOS transistors with different gate lengths, gate numbers and gate widths are accurately measured by means of special NMOS transistor structures on each first device region, and the transistors are combined with the PMOS gate structure and other NMOS transistor structures at the same time, so that the defect that the thermal resistance values cannot be accurately measured due to the fact that the temperature resistance coefficient of the conventional NMOS transistor structure is too low is overcome. After the first thermal resistance values of the special NMOS transistor structure are obtained, the initial second thermal resistance values are used as anchor points to correct the first thermal resistance values, and the influence caused by the PMOS grid structure in the special NMOS transistor structure is stripped, so that the thermal resistance values of the conventional NMOS transistor structure with different grid lengths, grid numbers and grid widths, namely the second thermal resistance values, are accurately obtained, and the accuracy of thermal resistance performance evaluation of the NMOS transistor device is improved. Similarly, when the first source drain region is provided with the P-type doped ions, the accuracy of thermal resistance measurement of the corresponding PMOS transistor is improved by means of a special PMOS thermal effect device structure.
Drawings
FIGS. 1 to 3 are schematic structural views of a thermal effect device structure according to an embodiment of the present invention;
FIG. 4 is a flow chart of a thermal resistor obtaining method according to an embodiment of the invention;
fig. 5 to 8 are schematic diagrams of a second thermal resistance value obtaining method according to an embodiment of the invention;
fig. 9 is a schematic diagram of each second thermal resistance value obtaining method in the thermal resistance obtaining method according to another embodiment of the invention.
Detailed Description
As described in the background art, in the process of measuring the thermal resistance of a transistor, in order to ensure the accuracy and convenience of measurement, a gate structure in a field effect transistor is often adopted as a measurement object. However, in the prior art, the temperature resistivity of the gate structure of most transistors is very small, so that the temperature variation of the gate structure under different measurement conditions cannot be accurately obtained, and thus the obtained thermal resistance value is poor in accuracy. At present, in each transistor structure, only the temperature resistance coefficient of the grid structure of the ultra-low threshold voltage transistor (PULVT) in the PMOS transistor is larger, so that the thermal resistance value of the transistor under different structures and sizes can be accurately obtained. For the NMOS transistor, only when the gate length of the NMOS transistor is smaller, the more accurate temperature resistivity and thermal resistance value can be obtained, and for the NMOS transistor with a larger gate length, the temperature resistivity is too small, so that the accurate thermal resistance value cannot be obtained, and therefore, the evaluation of the thermal resistance performance of the device is adversely affected. In addition, for PMOS low threshold voltage transistors (PLVT) or PMOS standard threshold voltage transistors (PSVT) with larger gate lengths, the temperature resistivity is also smaller, so the measurement accuracy of the thermal resistance is also to be improved.
In order to solve the above technical problems, the technical solution of the present invention provides a thermal effect device structure, which includes a first gate structure on a first device region including a P-type transistor work function layer, and a first source/drain region including N-type doped ions or P-type doped ions. When the first source drain region is provided with N-type doping ions, the transistor on the first device region combines a PMOS grid structure and other transistor structures of NMOS at the same time, so that a special NMOS thermal effect device structure is formed. The first gate structure comprises a P-type transistor work function layer, and the P-type transistor work function layer is more sensitive to temperature, so that the first gate structure is more sensitive to temperature change. When the transistor structure on the first device region works, the special NMOS thermal effect device structure can accurately measure the temperature change through the first grid structure of the special NMOS thermal effect device structure while playing the NMOS function, so that the accuracy of the subsequent thermal resistance measurement is improved. Similarly, by selecting the P-type transistor work function layer which is more sensitive to temperature from the first grid structure, a special PMOS thermal effect device structure can be formed when the P-type doped ions are arranged in the first source drain region, so that the accuracy of thermal resistance measurement of the corresponding PMOS transistor is improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 3 are schematic structural views of a thermal effect device structure according to an embodiment of the present invention. Wherein fig. 1 and 2 are schematic structural views on a first device region of the thermal effect device structure of the embodiment, and fig. 3 is a schematic structural view on a second device region of the thermal effect device structure of the embodiment.
Referring to fig. 1 and 2, fig. 1 is a top view of fig. 2 along a direction P, and fig. 2 is a schematic cross-sectional structure of fig. 1 along a direction AA', where the thermal effect device structure includes: a substrate (not labeled), the substrate comprising a first device region 101; a first gate structure 103 located on the first device region 101, the first gate structure 103 including a P-type transistor work function layer (not shown) and a first gate (not shown) located on the P-type transistor work function layer; and the first source-drain region 105 is positioned at two sides of the first gate structure 103, and N-type doping ions are arranged in the first source-drain region 105.
In this embodiment, the substrate (not labeled) includes a base and a plurality of fin structures located on the base, and the first device region 101 includes a first base 100 and a plurality of first fin structures 104. Materials for the substrate include silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), and the like. Specifically, in this embodiment, the material of the substrate is silicon.
In this embodiment, the first gate structure 103 spans a portion of the top and sidewall surfaces of the first fin structure 104.
In another embodiment, the substrate comprises a planar structure. The first gate structure is located on the surface of the substrate.
In other embodiments, the substrate and the first gate structure may also be any structure suitable for HKMG processes.
In this embodiment, the first gate structure 103 includes a P-type transistor work function layer (not shown), and a first gate (not shown) on the P-type transistor work function layer. The thickness and the material of the work function layer of the P-type transistor meet the requirements of the structure and the material of the work function layer applicable to the PMOS transistor; the first grid electrode meets the requirement of the grid electrode of the PMOS transistor. Thus, the first gate structure 103 is a PMOS gate structure.
In this embodiment, the P-type transistor work function layer material includes an alloy.
Because the first gate structure 103 on the first device region 101 is a P-type transistor gate structure, and the first source drain region 105 has N-type doped ions therein, the transistor on the first device region 101 combines the gate structure of the PMOS transistor and other transistor structures of the NMOS transistor at the same time, thereby forming a special NMOS transistor thermal effect device structure. Since the first gate structure 103 includes a P-type transistor work function layer, the thickness of the P-type transistor work function layer is larger than that of the N-type transistor work function layer in the conventional NMOS transistor gate structure, so that the ratio of the alloy material in the first gate structure 103 is larger; since the alloy material is more sensitive to temperature, the first gate structure 103 is more sensitive to temperature variations. When the transistor structure on the first device region 101 works, the special NMOS transistor thermal effect device structure can accurately measure the temperature change through the first gate structure 103, thereby improving the accuracy of the subsequent thermal resistance measurement.
In this embodiment, the first gate structure 103 includes a gate structure of a PMOS ultra low threshold voltage (PULVT) transistor. Compared with other PMOS transistors, the temperature resistance coefficient of the PMOS ultralow threshold voltage transistor is larger, and the sensitivity of the PMOS ultralow threshold voltage transistor to temperature is higher, so that more accurate temperature change can be obtained in the measurement process of the thermal resistor, and the measurement accuracy of the thermal resistor is higher. In this embodiment, the thermal effect device structure further includes: a first gate dielectric layer 102 between the substrate and the first gate structure 103.
With continued reference to fig. 1, in this embodiment, the thermal effect device structure further includes: a first electrical connection layer 110 electrically connected to the first gate structure 103, and a second electrical connection layer 111 connected to the first electrical connection layer 110, the first and second electrical connection layers 110 and 111 connecting the first gate structure 103 to an external circuit.
In this embodiment, the first electrical connection layer 110 is electrically connected to the first gate structure 103 through the first plug 112; the second electrical connection layer 111 is also electrically connected to the first electrical connection layer 110 via the first plug 112.
Note that the first source drain region 105 is omitted from fig. 1 for ease of understanding.
In this embodiment, the substrate includes a number of first device regions 101 greater than 1; the first gate structures 103 on the number of first device regions 101 are different in length, the number of first gate structures 103 on the number of first device regions 101 are different, or the first gate structures 103 on the number of first device regions 101 are different in width. Therefore, in the subsequent thermal resistance test, the thermal resistance values of the transistor structures having different lengths of the first gate structures 103, the thermal resistance values of the transistor structures having different numbers of the first gate structures 103, and the thermal resistance values of the transistor structures having different widths of the first gate structures 103 can be measured, respectively.
Note that, the length of the first gate structure 103 refers to the size of the area between the first source and drain regions 105 on both sides of the first gate structure 103, and the width of the first gate structure 103 is perpendicular to the length of the first gate structure 103.
Specifically, the first device regions 101 have a reference test region (not shown), where the first gate structures 103 in the reference test region have a reference gate length, and the reference gate length is the minimum value of the lengths of the first gate structures 103 on each first device region 101.
In another embodiment, the first source drain region has P-type dopant ions therein. The first gate structure includes a P-type transistor work function layer, and a first gate located on the P-type transistor work function layer. Specifically, the thickness and the material of the work function layer of the P-type transistor meet the requirements of the structure and the material of the work function layer suitable for the PMOS ultra-low threshold voltage transistor, so that the first gate structure meets the requirements of the gate structure of the PMOS ultra-low threshold voltage transistor and is the gate structure of the PMOS ultra-low threshold voltage transistor.
Since the P-type transistor work function layer suitable for the PMOS ultra-low threshold voltage transistor gate structure is selected in the first gate structure, it is more sensitive to temperature variation. Thus, the transistors on the first device region combine the gate structure of the PMOS ultra-low threshold voltage transistor, as well as the remaining transistor structures of other types of PMOS transistors, to form a special PMOS transistor thermal effect device structure. When the transistor structure on the first device region works, the special PMOS transistor thermal effect device structure can accurately measure the temperature change through the first grid structure of the PMOS ultralow threshold voltage transistor, thereby improving the accuracy of the subsequent thermal resistance measurement.
Referring to fig. 3, in this embodiment, the substrate further includes a second device region 110. The thermal effect device structure further comprises: a reference transistor (not labeled) located on the second device region 110, the reference transistor comprising: a second gate structure 113, the second gate structure 113 comprising an N-type transistor work function layer (not shown); the second source-drain regions 115 are located at two sides of the second gate structure 113, N-type doped ions are located in the second source-drain regions 115, and the length of the second gate structure 113 is the reference gate length; a second gate dielectric layer 112 between the substrate and a second gate structure 113.
In this embodiment, the thickness of the P-type transistor work function layer is greater than the thickness of the N-type transistor work function layer.
In this embodiment, the material of the N-type transistor work function layer includes an alloy.
In this embodiment, the transistor structure on the second device region 110 is a conventional NMOS transistor structure. Since the second gate structure 113 includes the N-type transistor work function layer having a smaller thickness, the second gate structure 113 is less sensitive to temperature, and the measured temperature resistivity of the second gate structure 113 is small. Particularly, when the gate structure length of the NMOS transistor structure is large, the temperature resistivity thereof is too small, so that an accurate thermal resistance value cannot be obtained; and only when the gate structure length of the NMOS transistor structure is small, that is, when the length of the second gate structure 113 is the reference gate length, a more accurate temperature resistivity and thermal resistance value can be obtained.
In the subsequent thermal resistance test process for the thermal effect device structure, the transistor structures on the first device region 101 and the second device region 110 are tested in cooperation with each other, so as to obtain accurate thermal resistance values of NMOS transistor structures with different lengths of gate structures, different numbers of gate structures or different widths of gate structures.
In another embodiment, the first source drain region has P-type doped ions therein, and the thermal effect device structure further includes: a reference transistor located on the second device region, the reference transistor comprising: a second gate structure comprising a P-type transistor work function structure having a thickness different from a thickness of the P-type transistor work function layer of the first gate structure; the second source-drain regions are positioned at two sides of the second gate structure, P-type doped ions are arranged in the second source-drain regions, and the length of the second gate structure is the length of the reference gate; and a second gate dielectric layer between the substrate and the second gate structure.
In the embodiment, the second gate structure includes a P-type transistor work function structure that is suitable for use in a gate structure of a PMOS low threshold voltage transistor (PLVT) or a gate structure of a PMOS standard threshold voltage transistor (PSVT), and thus the second gate structure is a gate structure of a PMOS low threshold voltage transistor or a gate structure of a PMOS standard threshold voltage transistor.
Since the second gate structure is not highly sensitive to temperature, the measured temperature resistivity of the second gate structure is small. Particularly, when the gate structure length of the PMOS low-threshold voltage transistor or the PMOS standard-threshold voltage transistor is larger, the temperature resistance coefficient is smaller, and the acquired thermal resistance value is lower in accuracy; and only when the gate structure length of the corresponding transistor structure is small, that is, when the length of the second gate structure is the reference gate length, a more accurate temperature resistivity and thermal resistance value can be obtained.
In the subsequent thermal resistance test process of the thermal effect device structure, the transistor structures on the first device region and the second device region are mutually matched for testing, so that accurate thermal resistance values of the PMOS low-threshold voltage transistor or the PMOS standard-threshold voltage transistor with different lengths of gate structures, different numbers of gate structures or different widths of gate structures are obtained.
Correspondingly, the embodiment of the invention also provides a method for forming the thermal effect device structure.
With continued reference to fig. 1 and 2, the method for forming the thermal effect device structure includes: providing a substrate comprising a first device region 101; forming a first gate structure 103 on the first device region 101, the first gate structure 103 including a P-type transistor work function layer; a first source drain region 105 is formed at two sides of the first gate structure 103, and N-type doped ions are formed in the first source drain region 105.
In this embodiment, since the first gate structure 103 formed on the first device region 101 includes a P-type transistor work function layer, and the first source drain region 105 formed has N-type doping ions therein, the transistor on the first device region 101 combines the PMOS gate structure and other NMOS transistor structures to form a special NMOS thermal effect device structure. Since the first gate structure 103 includes a P-type transistor work function layer, the P-type transistor work function layer is more sensitive to temperature, thereby making the first gate structure 103 more sensitive to temperature variations. When the transistor structure on the first device region 101 works, the special NMOS thermal effect device structure can accurately measure the temperature change through the first gate structure 103 provided with the special NMOS thermal effect device structure while playing the NMOS function, so that the accuracy of the subsequent thermal resistance measurement is improved.
In this embodiment, the method for forming the first gate structure 103 includes: forming a first gate material layer (not shown) on the substrate, and a mask layer (not shown) on the first gate material layer; the first gate material layer is etched using the mask layer as a mask to form a first gate structure 103.
In this embodiment, the mask layer is used to form a gate structure of a PMOS ultra low threshold voltage (pulset) transistor, so that the sensitivity of the first gate structure 103 to temperature variation is further improved, and the accuracy of subsequent thermal resistance measurement is improved.
In another embodiment, the first source drain region has P-type dopant ions therein.
Correspondingly, the embodiment of the invention also provides a thermal resistance acquisition method which can more accurately measure the thermal resistance values of the transistor structures with different lengths of gate structures, different numbers of gate structures or different widths of gate structures.
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
FIG. 4 is a flow chart of a thermal resistor obtaining method according to an embodiment of the invention; fig. 5 to 8 are schematic diagrams of a second thermal resistance value obtaining method according to an embodiment of the invention.
Referring to fig. 4 in conjunction with fig. 1 to 3, the thermal resistance obtaining method includes:
step S100: providing a thermal effect device structure, the thermal effect device structure comprising: a substrate comprising a number of first device regions 101 and second device regions 110; the first gate structures 103 are located on the first device regions 101, the first gate structures 103 comprise P-type transistor work function layers, the lengths of the first gate structures 103 on the first device regions 101 are different, the numbers of the first gate structures 103 on the first device regions 101 are different or the widths of the first gate structures 103 on the first device regions 101 are different, and a reference test region is arranged in the first device regions 101, the first gate structures 103 on the reference test region have a reference gate length which is the minimum value of the lengths of the first gate structures 103 on the first device regions 101; first source drain regions 105 located at both sides of each first gate structure 103; a reference transistor located on the second device region 110, the reference transistor comprising a second gate structure 113, the second gate structure 113 having a length that is the reference gate length.
In this embodiment, the first source drain region 105 has N-type doped ions therein.
Step S110: acquiring first thermal resistance values corresponding to the first grid structures 103 by adopting a thermal resistance measurement method, wherein the first thermal resistance values corresponding to the first grid structures 103 on the reference test area are first reference thermal resistance values;
step S120: acquiring an initial second thermal resistance value of the reference transistor by adopting a thermal resistance measurement method;
step S130: acquiring a thermal resistance offset, wherein the thermal resistance offset is the difference value between a first reference thermal resistance and an initial second thermal resistance;
step S140: the first thermal resistance values and the thermal resistance value offset are added to obtain second thermal resistance values corresponding to the first gate structures 103 on the first device regions 101.
Each step in the thermal resistance obtaining method is described in detail below with reference to fig. 1 to 8.
Referring to step S100 in fig. 4 in conjunction with fig. 1 to 3, a thermal effect device structure is provided, the thermal effect device structure comprising: a substrate comprising a number of first device regions 101 and second device regions 110; the first gate structures 103 are located on the first device regions 101, the first gate structures 103 comprise P-type transistor work function layers, the lengths of the first gate structures 103 on the first device regions 101 are different, the numbers of the first gate structures 103 on the first device regions 101 are different or the widths of the first gate structures 103 on the first device regions 101 are different, and a reference test region is arranged in the first device regions 101, the first gate structures 103 on the reference test region have a reference gate length which is the minimum value of the lengths of the first gate structures 103 on the first device regions 101; the first source drain regions 105 are located at two sides of each first gate structure 103, and N-type doping ions are located in the first source drain regions 105; a reference transistor located on the second device region 110, the reference transistor comprising a second gate structure 113, the second gate structure 113 having a length that is the reference gate length.
In this embodiment, the thickness of the P-type transistor work function layer is greater than the thickness of the N-type transistor work function layer.
In this embodiment, the P-type transistor work function layer material includes an alloy; the material of the N-type transistor work function layer comprises an alloy.
In this embodiment, the reference gate length ranges from 2 nm to 14 nm.
Specifically, the first gate structure 103 includes a gate structure of a PMOS ultra low threshold voltage (PULVT) transistor.
In this embodiment, on the one hand, the first gate structure 103 on the first device region 101 includes a P-type transistor work function layer, and the first source drain region 105 has N-type doping ions therein, so that the transistor on the first device region 101 combines the PMOS gate structure and other NMOS transistor structures to form a special NMOS thermal effect device structure. Since the first gate structure 103 includes a P-type transistor work function layer, the P-type transistor work function layer is more sensitive to temperature, thereby making the first gate structure 103 more sensitive to temperature variations. On the other hand, the reference transistor on the second device region 110 is a conventional NMOS transistor structure, and in the process of performing the thermal resistance test on the thermal effect device structure, the transistor structures on the first device region 101 and the second device region 110 can be mutually matched for testing, so as to obtain accurate thermal resistance values of NMOS transistor structures with gate structures of different lengths, different numbers of gate structures or gate structures of different widths.
It should be noted that the first thermal resistance corresponding to each first gate structure 103 refers to the thermal resistance of the corresponding transistor structure having the first gate structure 103 on the first device region 101. Specifically, the specific structures of the first gate structure 103, the first source drain region 105 and the reference transistor on the second device region 110 in the first device region 101 in this embodiment are described in fig. 1 to 3, and are not repeated here.
Referring to step S110 in fig. 4 in conjunction with fig. 5, a thermal resistance measurement method is adopted to obtain a first thermal resistance value corresponding to each first gate structure 103, where the first thermal resistance value corresponding to the first gate structure 103 on the reference test area is a first reference thermal resistance value (as shown in point B in fig. 5).
It should be noted that the first thermal resistance corresponding to each first gate structure 103 refers to the thermal resistance of the corresponding transistor structure having the first gate structure 103 on the first device region 101.
In this embodiment, the thermal resistance measurement method includes: heating the thermal effect device structure for a plurality of times to reach a plurality of test temperatures, and respectively obtaining first unit resistance values of the first gate structure 103 corresponding to the test temperatures by applying first voltages to two ends of the first gate structure 103; acquiring the temperature resistance coefficient of the first gate structure 103 according to each first unit resistance value and each test temperature; the thermal effect device structure is positioned at a plurality of working powers, and a second unit resistance value of the first grid structure 103 corresponding to each working power is obtained; acquiring the working temperature increment of the first grid structure 103 corresponding to each working power according to each second unit resistance value and the temperature resistance coefficient; and acquiring a first thermal resistance value corresponding to the first gate structure 103 according to each working power and each working temperature increment of the first gate structure 103.
Since the first gate structure 103 includes a P-type transistor work function layer, the P-type transistor work function layer is more sensitive to temperature, thereby making the first gate structure 103 more sensitive to temperature variations. Because the transistors on the first device region 101 combine the PMOS gate structure and other transistor structures of the NMOS at the same time, when the transistor structures on the first device region 101 operate, on one hand, the special NMOS thermal effect device structure can perform the function of the NMOS itself; on the other hand, the transistor structures with the first gate structures 103 having different lengths, the transistor structures with the first gate structures 103 having different numbers, or the transistor structures with the first gate structures 103 having different widths on each first device region 101 can react to temperature changes more sensitively, so that the measurement accuracy of the first thermal resistance value corresponding to each first gate structure 103 is higher.
In this embodiment, the lengths of the first gate structures 103 on the first device regions 101 are different, but the remaining structures, numbers, and widths are the same.
With continued reference to fig. 5, after obtaining the first thermal resistance value corresponding to each first gate structure 103, a coordinate system is established with the gate structure Length and the thermal resistance value Rth as axes; and drawing a plurality of first test points corresponding to the first thermal resistance values and the lengths of the first gate structures 103 in a coordinate system by taking the lengths of the first gate structures 103 on each first device region 101 and the first thermal resistance values corresponding to the corresponding first gate structures 103 as coordinates.
Note that in this embodiment, since the transistor structure on the first device region 101 is combined with the Gate structure of the PMOS ultra-low threshold voltage transistor, i.e., the PULVT Gate structure, and other transistor structures of the NMOS transistor, this particular NMOS transistor structure on each first device region 101 is denoted as an nmos_pulvt Gate transistor in fig. 5.
In another embodiment, the number of first gate structures on each first device region is different, but the remaining structures are the same. Therefore, the first thermal resistance value corresponding to the first gate structures on each first device region and the number of the first gate structures can be used as coordinates, and a plurality of first test points corresponding to the first thermal resistance value and the number of the first gate structures can be drawn.
In yet another embodiment, the first gate structures on each first device region are different in width, but the remaining structures are the same. Therefore, the first thermal resistance value corresponding to the first gate structure on each first device region and the width of each first gate structure can be used as coordinates, and a plurality of first test points corresponding to the first thermal resistance value and the width of each first gate structure can be drawn.
Referring to step S120 in fig. 4 in conjunction with fig. 6, an initial second thermal resistance value of the reference transistor is obtained by using a thermal resistance measurement method.
It should be noted that the initial second thermal resistance value of the reference transistor is obtained by measuring and acquiring the resistance change and the temperature change of the second gate structure 113.
In this embodiment, the thermal resistance measurement method is the same as the thermal resistance measurement method for obtaining the first thermal resistance value in S110, and will not be described herein. In this embodiment, the reference transistor is a conventional NMOS transistor structure, and the length of the second gate structure 113 is the reference gate length, i.e., the minimum value of the length of the first gate structure 103 on each first device region 101. Because the length of the second gate structure 113 is smaller, the temperature resistivity and the thermal resistance of the second gate structure 113 can be obtained more accurately.
In this embodiment, the reference transistor is an NMOS low threshold voltage (NLVT) transistor.
With continued reference to fig. 6, a reference point (shown as a point a) corresponding to the reference transistor is plotted on the coordinate axis with the length of the reference transistor and the initial second thermal resistance value of the reference transistor as coordinates.
Referring to step S130 in fig. 4 in conjunction with fig. 7, a thermal resistance offset H is obtained, where the thermal resistance offset is a difference between the first reference thermal resistance and the initial second thermal resistance.
Since the first reference thermal resistance (as shown in the B-point) and the initial second thermal resistance (as shown in the a-point) are both higher in accuracy, the transistor structure corresponding to the first reference thermal resistance is the same as the length of the Gate structure of the reference transistor, and the other parts of the transistor structure are the same, the only difference between the first Gate structure 103 and the second Gate structure 113 is that the first Gate structure 103 includes a P-type transistor work function layer, and the second Gate structure 113 includes an N-type transistor work function layer, and therefore, the thermal resistance offset H means that compared with the conventional NMOS transistor structure, the NMOS transistor with a special structure, that is, the nmos_pulse Gate transistor has the effect of the thermal resistance due to the PMOS Gate structure.
Referring to step S140 in fig. 4 in conjunction with fig. 8, the first thermal resistance values and the thermal resistance offset are added to obtain second thermal resistance values corresponding to the first gate structures 103 on the first device regions 101.
Because the step S110 more accurately obtains the first thermal resistance value corresponding to each first gate structure 103, and the step S130 also more accurately obtains the thermal resistance value offset, on this basis, the initial second thermal resistance value may be used as an anchor point to correct each first thermal resistance value, and the correction degree is the thermal resistance value offset, so as to obtain each second thermal resistance value corresponding to the first gate structure 103 on each first device region 101, where the second thermal resistance value is a thermal resistance value of an NMOS transistor, and each NMOS transistor has the same gate length, gate number, or gate width as each first gate structure 103.
The thermal resistance obtaining method in this embodiment more accurately measures the first thermal resistance value of the special NMOS transistor with different gate lengths, gate numbers or gate widths by means of the special NMOS transistor structure on each first device region 101, and the transistor combines the PMOS gate structure and other transistor structures of the NMOS at the same time, thereby overcoming the defect that the conventional NMOS transistor structure cannot accurately measure the thermal resistance value due to the too low temperature resistance coefficient. After the first thermal resistance values of the special NMOS transistor structure are obtained, the initial second thermal resistance values are used as anchor points to correct the first thermal resistance values, and the influence caused by the PMOS grid structure in the special NMOS transistor structure is stripped, so that the thermal resistance values of the conventional NMOS transistor structure with different grid lengths, grid numbers or grid widths, namely the second thermal resistance values, are accurately obtained, and the accuracy of thermal resistance performance evaluation of the NMOS transistor device is improved.
In other embodiments, the reference transistor comprises an NMOS standard threshold voltage (NSVT) transistor, an NMOS low threshold voltage (NLVT) transistor, or an NMOS ultra low threshold voltage (NULVT) transistor.
Referring to fig. 9, fig. 9 is a schematic diagram of each second thermal resistance value obtaining method in the thermal resistance obtaining method according to another embodiment of the invention.
On the basis of acquiring a plurality of first thermal resistance values, continuously acquiring each second thermal resistance value, each third thermal resistance value and each fourth thermal resistance value corresponding to the first grid structure on each first device region, wherein the method for acquiring the first thermal resistance values in the embodiment is the same as the method for acquiring the first thermal resistance values in fig. 4 to 8; the method for obtaining each second thermal resistance value, each third thermal resistance value, and each fourth thermal resistance value in the embodiment is the same as the method for obtaining the second thermal resistance value described in fig. 4.
In the embodiment, the second thermal resistance is a thermal resistance of a conventional NMOS standard threshold voltage (NSVT) transistor, the third thermal resistance is a thermal resistance of a conventional NMOS low threshold voltage (NLVT) transistor, and the fourth thermal resistance is a thermal resistance of a conventional NMOS ultra low threshold voltage (NULVT) transistor.
The length of the gate structure of the NMOS standard threshold voltage (NSVT) transistor, the length of the NMOS low threshold voltage (NLVT) transistor, and the length of the NMOS ultra low threshold voltage (NULVT) transistor respectively correspond to the length of the first gate structure on each first device region.
In another embodiment, the number of first gate structures on each first device region is different, but the remaining structures are the same. Accordingly, corresponding thermal resistance values of NMOS standard threshold voltage (NSVT), NMOS low threshold voltage (NLVT), and NMOS ultra low threshold voltage (NULVT) transistors having different numbers of gates can be acquired by the thermal resistance acquisition method.
In yet another embodiment, the first gate structures on each first device region are different in width, but the remaining structures are the same. Accordingly, corresponding thermal resistance values of NMOS standard threshold voltage (NSVT), NMOS low threshold voltage (NLVT), and NMOS ultra low threshold voltage (NULVT) transistors having different gate widths can be acquired by the thermal resistance acquisition method.
In addition, another embodiment of the present invention further provides a thermal resistance obtaining method for improving the accuracy of measurement of the thermal resistance of the PMOS transistor.
In the embodiment, P-type doped ions are provided in a first source drain region on a first device region of the provided thermal effect device structure, a second gate structure included in a reference transistor on the second device region has a P-type transistor work function structure, and the thickness of the P-type transistor work function structure is different from that of a P-type transistor work function layer of the first gate structure. In particular, the second gate structure includes a P-type transistor work function structure suitable for use in a gate structure of a PMOS low threshold voltage transistor (PLVT) or a gate structure of a PMOS standard threshold voltage transistor (PSVT).
The transistors in the first device region are combined with the grid structure of the PMOS ultra-low threshold voltage transistor and the other transistor structures of the PMOS low-threshold voltage transistor or the PMOS standard threshold voltage transistor at the same time, so that a special PMOS transistor thermal effect device structure is formed. When the transistor structure on the first device region works, the special PMOS transistor thermal effect device structure can accurately measure the temperature change through the first grid structure of the PMOS ultralow threshold voltage transistor while playing the function of the PMOS low threshold voltage transistor or the PMOS standard threshold voltage transistor, so that the accuracy of the subsequent thermal resistance measurement is improved.
On the basis, a thermal resistance obtaining method is adopted to obtain the thermal resistance value of the PMOS low threshold voltage transistor or the PMOS standard threshold voltage transistor. The thermal resistance obtaining method is the same as that shown in fig. 4 to 8.
According to the thermal resistance acquisition method, the first thermal resistance values of the special PMOS transistors with different gate lengths, gate numbers or gate widths are accurately measured by means of the special PMOS transistor structures on the first device regions, the gate structures of the PMOS ultra-low threshold voltage transistors are combined with other transistor structures of the PMOS low threshold voltage transistors or the PMOS standard threshold voltage transistors, the defect that the accuracy of the measured thermal resistance values is low due to the fact that the temperature resistance coefficient of the conventional PMOS low threshold voltage transistors or the PMOS standard threshold voltage transistors is too low is overcome, the thermal resistance values of the conventional PMOS low threshold voltage transistors or the conventional PMOS standard threshold voltage transistors with different gate lengths, gate numbers or gate widths are accurately obtained, and accordingly improvement of accuracy of thermal resistance performance evaluation of the PMOS low threshold voltage transistors or the PMOS standard threshold voltage transistor devices is facilitated.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (20)

1. A thermal effect device structure, comprising:
a substrate comprising a first device region;
a first gate structure on the first device region, the first gate structure comprising a P-type transistor work function layer and a first gate on the P-type transistor work function layer;
the first source-drain region is positioned at two sides of the first grid structure, and N-type doping ions or P-type doping ions are arranged in the first source-drain region.
2. The thermal effect device structure of claim 1, wherein the substrate comprises a base and a plurality of fin structures located on the base.
3. The thermal effect device structure of claim 2, wherein the first gate structure spans a top and sidewall surfaces of a portion of the fin structure.
4. The thermal effect device structure of claim 1, wherein said substrate comprises a planar structure.
5. The thermal effect device structure of claim 1, further comprising: and a first gate dielectric layer between the substrate and the first gate structure.
6. The thermal effect device structure of claim 1, wherein a material of said P-type transistor work function layer comprises an alloy.
7. The thermal effect device structure of claim 1, wherein the first gate structure comprises a gate structure of a PMOS ultra-low threshold voltage transistor.
8. The thermal effect device structure of claim 1, wherein said substrate comprises a number of first device regions greater than 1; the first gate structures on the plurality of first device regions are different in length, the number of the first gate structures on the plurality of first device regions is different, or the first gate structures on the plurality of first device regions are different in width, and the plurality of first device regions are provided with reference test regions, wherein the first gate structures in the reference test regions are provided with reference gate lengths, and the reference gate lengths are the minimum values of the first gate structure lengths on the first device regions.
9. The thermal effect device structure of claim 8, wherein said substrate further comprises a second device region.
10. The thermal effect device structure of claim 9, wherein when said first source drain region has N-type dopant ions therein, said thermal effect device structure further comprises: a reference transistor located on the second device region, the reference transistor comprising: a second gate structure comprising an N-type transistor work function layer; the second source-drain regions are positioned on two sides of the second gate structure, N-type doped ions are arranged in the second source-drain regions, and the length of the second gate structure is the length of the reference gate.
11. The thermal effect device structure of claim 10, wherein a material of said N-type transistor work function layer comprises an alloy.
12. The thermal effect device structure of claim 10, wherein a thickness of said P-type transistor work function layer is greater than a thickness of said N-type transistor work function layer.
13. The thermal effect device structure of claim 9, wherein when there are P-type dopant ions within the first source drain region, the thermal effect device structure further comprises: a reference transistor located on the second device region, the reference transistor comprising: a second gate structure comprising a P-type transistor work function structure having a thickness different from a thickness of the P-type transistor work function layer of the first gate structure; the second source-drain regions are positioned on two sides of the second gate structure, P-type doped ions are arranged in the second source-drain regions, and the length of the second gate structure is the length of the reference gate.
14. A method of forming a thermal effect device structure, comprising:
providing a substrate, wherein the substrate comprises a first device region;
forming a first gate structure on the first device region, the first gate structure including a P-type transistor work function layer;
and forming a first source drain region at two sides of the first grid structure, wherein N-type doping ions or P-type doping ions are arranged in the first source drain region.
15. A thermal resistance acquisition method, characterized by comprising:
providing a thermal effect device structure, the thermal effect device structure comprising: the semiconductor device comprises a substrate, a first semiconductor layer and a second semiconductor layer, wherein the substrate comprises a plurality of first device areas and second device areas; the first grid structures are positioned on the first device regions and comprise P-type transistor work function layers, the lengths of the first grid structures on the first device regions are different, the number of the first grid structures on the first device regions is different or the widths of the first grid structures on the first device regions are different, a reference test region is arranged in the first device regions, the first grid structures on the reference test region have a reference grid length, and the reference grid length is the minimum value of the first grid structure lengths on the first device regions; the first source-drain regions are positioned at two sides of each first gate structure and are internally provided with N-type doping ions or P-type doping ions; a reference transistor located on the second device region, the reference transistor comprising a second gate structure, the second gate structure having a length that is the reference gate length;
Acquiring first thermal resistance values corresponding to the first grid structures by adopting a thermal resistance measurement method, wherein the first thermal resistance values corresponding to the first grid structures on the reference test area are first reference thermal resistance values;
acquiring an initial second thermal resistance value of the reference transistor by adopting a thermal resistance measurement method;
acquiring a thermal resistance offset, wherein the thermal resistance offset is the difference value between a first reference thermal resistance and an initial second thermal resistance;
and adding the first thermal resistance values and the thermal resistance value offset to obtain second thermal resistance values corresponding to the first grid structures on the first device regions.
16. The method of claim 15, wherein the second gate structure of the reference transistor comprises an N-type transistor work function layer when N-type dopant ions are present in the first source drain region of the thermal effect device structure; the thickness of the P-type transistor work function layer is larger than that of the N-type transistor work function layer.
17. The thermal resistance acquisition method according to claim 16, wherein a material of the P-type transistor work function layer includes an alloy; the material of the N-type transistor work function layer comprises an alloy.
18. The method of claim 15, wherein the thermal resistance measurement method used to obtain the first thermal resistance value corresponding to each first gate structure comprises: heating the thermal effect device structure for a plurality of times to reach a plurality of test temperatures, and respectively obtaining first unit resistance values of the first grid structure corresponding to the test temperatures by applying first voltages to two ends of the first grid structure; acquiring the temperature resistance coefficient of the first grid structure according to each first unit resistance value and each test temperature; the thermal effect device structure is enabled to be in a plurality of working powers, and a second unit resistance value of the first grid structure corresponding to each working power is obtained; acquiring the working temperature increment of the first grid structure corresponding to each working power according to each second unit resistance value and the temperature resistance coefficient; and acquiring a first thermal resistance value corresponding to the first grid structure according to each working power and each working temperature increment of the first grid structure.
19. The method of claim 16, wherein the reference transistor comprises an NMOS standard threshold voltage transistor, an NMOS low threshold voltage transistor, or an NMOS ultra low threshold voltage transistor when the first source drain region of the thermal effect device structure has N-type dopant ions therein.
20. The method of claim 15, wherein the reference gate length is in the range of 2 nm to 14 nm.
CN202210894040.XA 2022-07-27 2022-07-27 Thermal effect device structure, forming method thereof and thermal resistance obtaining method Pending CN117524898A (en)

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