CN110931463B - Semiconductor device test structure and manufacturing method thereof - Google Patents
Semiconductor device test structure and manufacturing method thereof Download PDFInfo
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- CN110931463B CN110931463B CN201911241192.4A CN201911241192A CN110931463B CN 110931463 B CN110931463 B CN 110931463B CN 201911241192 A CN201911241192 A CN 201911241192A CN 110931463 B CN110931463 B CN 110931463B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Abstract
The application provides a semiconductor device test structure and a manufacturing method thereof, wherein the method comprises the steps of providing a substrate, forming an isolation structure on the substrate, defining an active region and a connection region connected with the active region by the isolation structure, then forming a gate dielectric layer on the active region, and forming a gate on the gate dielectric layer to serve as a first conductive structure; and forming a second conductive structure above the active region connecting region to form a test structure, and directly applying different voltages to the first conductive structure and the second conductive structure to achieve the purpose of performing electrical test on the gate dielectric layer. Compared with the prior art, the manufacturing method has fewer and simple process steps, so that the electrical property testing step can be advanced, the research and development period of the semiconductor device is shortened, and the research and development speed is increased; meanwhile, only three mask plates are adopted in the process of manufacturing and forming the semiconductor device test structure, so that the number of the mask plates is reduced, and the research and development cost is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a semiconductor device testing structure and a manufacturing method thereof.
Background
In the manufacturing process of an integrated circuit, a semiconductor device comprises a gate structure, which usually comprises a gate dielectric layer structure, wherein the gate dielectric layer structure is an important part of a basic component, and the quality of the gate dielectric layer structure determines the performance of the semiconductor device. In addition, the gate dielectric layer structure is often the first step in circuit development, and later device development is started on the basis of good performances of the gate dielectric layer structure in all aspects.
However, the process from the gate dielectric layer structure to the back end is smooth and long, so that the research and development learning period in development is long, and the improvement of the research and development speed and the reduction of the research and development cost are not facilitated.
Disclosure of Invention
In view of the above, the present invention provides a semiconductor device test structure and a manufacturing method thereof, so as to solve the problems in the prior art that the device research and development learning period is long, and the improvement of the research and development speed and the reduction of the research and development cost are not facilitated.
In order to achieve the purpose, the invention provides the following technical scheme:
a method for manufacturing a semiconductor device test structure comprises the following steps:
providing a substrate;
forming an isolation structure on the substrate, wherein the isolation structure defines an active region and a connection region, the active region and the connection region are electrically connected in the substrate, and the active region and the connection region are arranged on the surface of the substrate in an isolation mode;
forming a gate dielectric layer on the active region;
forming a first conductive structure on the gate dielectric layer;
a second conductive structure is formed on the connection region.
Preferably, the forming of the isolation structure on the substrate specifically includes:
providing a first mask plate, wherein the pattern of the first mask plate corresponds to the pattern of an isolation structure to be formed;
etching the substrate based on the first mask plate to form a first groove;
and depositing an insulating material, and filling the first groove to form the isolation structure.
Preferably, the forming of the gate dielectric layer on the active region specifically includes:
oxidizing the substrate to form a gate dielectric layer body on the substrate;
providing a second mask plate, wherein the pattern of the second mask plate corresponds to the pattern of the gate dielectric layer to be formed;
and etching the gate dielectric layer body based on the second mask plate, reserving the gate dielectric layer body above the active region, removing the gate dielectric layer body in other regions, and forming the gate dielectric layer.
Preferably, the forming of the first conductive structure on the gate dielectric layer and the forming of the second conductive structure on the connection region specifically include:
forming a whole layer of conductive material on the gate dielectric layer, the isolation structure and the substrate;
providing a third mask plate, wherein patterns of the third mask plate correspond to the patterns of the first conductive structure and the second conductive structure to be formed;
and etching the whole layer of conductive material based on the third mask plate, reserving the conductive material covering the gate dielectric layer to form a first conductive structure, and forming a second conductive structure by the conductive material electrically connected with the connection area.
Preferably, the first conductive structure includes a first sub-conductive structure located on the gate dielectric layer and a first pad located outside the gate dielectric layer and electrically connected to the first sub-conductive structure;
the second conductive structure comprises a second sub-conductive structure positioned on the connecting area and a second bonding pad positioned outside the connecting area and electrically connected with the second sub-conductive structure.
Preferably, the forming a gate dielectric layer on the active region and the forming a first conductive structure on the gate dielectric layer specifically include:
oxidizing the substrate to form a gate dielectric layer body on the substrate;
forming a whole first conductive layer on the gate dielectric layer body;
providing a fourth mask plate, wherein the pattern of the fourth mask plate corresponds to the pattern of the first conductive structure to be formed;
and etching the gate dielectric layer body and the first conductive layer based on the fourth mask plate, and reserving the gate dielectric layer body and the first conductive layer above the active region to form the gate dielectric layer and the first conductive structure.
Preferably, the forming of the second conductive structure on the connection region specifically includes:
forming a full-layer second conductive layer on the isolation structure, the substrate and the first conductive structure;
providing a fifth mask plate, wherein the fifth mask plate corresponds to the pattern of the second conductive structure;
and etching the second conductive layer based on the fifth mask plate, and reserving the second conductive layer electrically connected with the connection area to form a second conductive structure.
Preferably, the substrate is made of intentionally doped monocrystalline silicon, the first conductive structure and the second conductive structure are made of polycrystalline silicon, and the gate dielectric layer is an oxide layer.
The invention also provides a semiconductor device test structure formed by the manufacturing method of the semiconductor device test structure, which comprises the following steps:
a substrate;
the isolation structures define an active area and a connection area, the active area and the connection area are electrically connected in the substrate, and the active area and the connection area are arranged on the surface of the substrate in an isolated mode through the isolation structures;
a gate dielectric layer located on the active region;
a first conductive structure located on the gate dielectric layer;
a second conductive structure on the connection region.
Preferably, the substrate is made of intentionally doped monocrystalline silicon, the first conductive structure and the second conductive structure are made of polycrystalline silicon, and the gate dielectric layer is an oxide layer.
Preferably, the first conductive structure includes a first sub-conductive structure located on the gate dielectric layer and a first pad located outside the gate dielectric layer and electrically connected to the first sub-conductive structure;
the second conductive structure comprises a second sub-conductive structure positioned on the connecting area and a second bonding pad positioned outside the connecting area and electrically connected with the second sub-conductive structure.
According to the technical scheme, the manufacturing method of the semiconductor device testing structure comprises the steps of providing a substrate, forming an isolation structure on the substrate, defining an active region and a connection region electrically connected with the active region by the isolation structure, then manufacturing a gate dielectric layer on the active region, and forming a first conductive structure on the gate dielectric layer, wherein the first conductive structure is a gate; and forming a second conductive structure above the connecting region, and applying different voltages to the first conductive structure and the second conductive structure to detect the insulating property of the gate dielectric layer so as to achieve the purpose of performing electrical test on the gate dielectric layer. The manufacturing method of the semiconductor device test structure provided by the invention has fewer and simple process steps, so that the electrical test step can be advanced, the research and development period of the semiconductor device is shortened, and the research and development speed is increased; meanwhile, only three mask plates are adopted in the process of manufacturing and forming the semiconductor device test structure, so that the number of the mask plates is reduced, and the research and development cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flow chart of a method for fabricating a semiconductor device test structure according to an embodiment of the present invention;
FIG. 2 is a schematic top view of a semiconductor device testing structure according to an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view along AA' in FIG. 2;
FIG. 4 is a schematic cross-sectional view taken along line BB' in FIG. 2;
FIG. 5 is a top view of a semiconductor device test structure according to an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view along AA' in FIG. 5;
FIG. 7 is a schematic cross-sectional view taken along line BB' in FIG. 5;
FIG. 8 is a schematic top view of a first mask;
FIG. 9 is a schematic top view of a second mask;
fig. 10 is a schematic top view of a third mask;
FIG. 11 is a top view of a semiconductor device test structure according to an embodiment of the present invention;
FIG. 12 is a schematic cross-sectional view taken along AA' in FIG. 11;
FIG. 13 is a schematic cross-sectional view taken along line BB' in FIG. 11;
fig. 14 is a schematic top view of the first mask;
fig. 15 is a schematic top view of a second mask;
fig. 16 is a schematic top view of a third mask.
Detailed Description
As described in the background section, the semiconductor device in the prior art has a long development and learning period, which is not favorable for increasing the development speed.
The inventor finds that the reason for the above phenomenon is that in the prior art, after the gate dielectric layer structure is manufactured, the electrical test can be performed only by continuing to manufacture the back-end metal connecting wire, the bonding pad and the like. At this time, the device is found to have electrical problems, which results in the obsolescence of the previous research and development processes and the need to restart the research and development processes. However, the trial and error process of one device usually requires a long time, which results in a slow development speed, and the manufacturing process includes many etching processes, so that more masks are needed, which results in a waste of cost.
An improved approach is proposed in the prior art to electrically connect the metal through the pad and then allow electrical testing when the device is fabricated to the first metal layer. Although a certain development time is saved, the development speed is still relatively low, and more mask plates are still needed.
Based on this, the invention provides a method for manufacturing a semiconductor device test structure, which comprises the following steps:
providing a substrate;
forming an isolation structure on the substrate, wherein the isolation structure defines an active region and a connection region, the active region and the connection region are electrically connected in the substrate, and the active region and the connection region are arranged on the surface of the substrate in an isolation mode;
forming a gate dielectric layer on the active region, wherein the gate dielectric layer completely covers the active region;
forming a first conductive structure on the gate dielectric layer, wherein the first conductive structure completely covers the gate dielectric layer;
a second conductive structure is formed on the connection region.
The invention provides a method for manufacturing a semiconductor device test structure, which comprises the steps of providing a substrate, forming an isolation structure on the substrate, defining an active region and a connection region electrically connected with the active region by the isolation structure, then manufacturing a gate dielectric layer on the active region, and forming a gate on the gate dielectric layer to serve as a first conductive structure; and forming a second conductive structure above the connecting region, and applying different voltages to the first conductive structure and the second conductive structure to detect the insulating property of the gate dielectric layer so as to achieve the purpose of performing electrical test on the gate dielectric layer. The manufacturing method of the semiconductor device test structure provided by the invention has fewer and simple process steps, so that the electrical test step can be advanced, the research and development learning period of the semiconductor device is shortened, and the research and development speed is increased; meanwhile, only three mask plates are adopted in the process of manufacturing and forming the semiconductor device test structure, so that the number of the mask plates is reduced, and the research and development cost is reduced.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a method for manufacturing a semiconductor device test structure according to an embodiment of the present invention, including:
s101: providing a substrate;
in this embodiment, the substrate is a semiconductor substrate, so that various devices can be formed over the substrate. The substrate material of the embodiment of the invention can be monocrystalline silicon.
S102: forming an isolation structure on the substrate, wherein the isolation structure defines an active region and a connection region, the active region and the connection region are electrically connected in the substrate, and the active region and the connection region are arranged on the surface of the substrate in an isolation mode;
the specific steps of forming the isolation structure on the substrate may include:
providing a first mask plate, wherein the pattern of the first mask plate corresponds to the pattern of an isolation structure to be formed, the specific form of the isolation structure is not limited in this embodiment, and optionally, the isolation structure may be Shallow Trench Isolation (STI);
etching the substrate based on the first mask plate to form a first groove;
and depositing an insulating material, and filling the first groove to form the isolation structure.
In this embodiment, the first mask pattern and the pattern of the isolation structure to be formed correspond to each other, and the first mask pattern includes:
the pattern of the first mask plate is the same as the pattern of the isolation structure to be formed; and the first mask plate pattern is complementary with the pattern of the isolation structure to be formed.
When the first mask plate patterns are in different shapes, the corresponding etching processes comprise different photoetching processes, the adopted photoresist forms different patterns, the final achieved purposes are the same, and the first grooves are formed on the substrate. Then, the substrate is filled with an insulating material, and the insulating material in the first groove forms an isolation structure.
The isolation structure defines different areas on the substrate, and the different areas comprise an active area and a connection area connected with the active area, wherein the active area, namely a well area (well) or an AA area, is an effective functional area of a device; the connecting region of the active region is a well pick up region and is used for electrically connecting the effective functional region of the device to the external connecting region.
In this embodiment, the active region and the connection region are formed by intentionally doping on a single crystal silicon substrate.
S103: forming a gate dielectric layer on the active region;
in this embodiment, a gate needs to be formed on the active region subsequently, so that a gate dielectric layer is formed on the active region first, and the gate dielectric layer completely covers the active region. In this embodiment, the area covered by the gate dielectric layer is not limited, and optionally, the gate dielectric layer completely covers the active area, where the fact that the projection of the gate dielectric layer on the substrate is greater than the projection of the uppermost surface of the active area on the substrate, and the projection of the uppermost surface of the active area on the substrate is located on the projection of the gate dielectric layer on the substrate, is referred to as the fact that the gate dielectric layer completely covers the active area.
S104: forming a first conductive structure on the gate dielectric layer;
in this embodiment, the coverage area of the first conductive structure is also not limited, and optionally, the first conductive structure completely covers the gate dielectric layer. The semiconductor device test structure provided by the invention aims to detect whether the insulation performance of the gate dielectric layer is good, so that when the first conductive structure is formed on the gate dielectric layer, the first conductive structure can completely cover the gate dielectric layer so as to wrap the gate dielectric layer, and the phenomenon that the insulation performance of the gate dielectric layer is not good due to electric leakage caused by other structures can be avoided in the detection process.
S105: a second conductive structure is formed on the connection region.
And forming a second conductive structure on the connecting region, and applying voltage to the first conductive structure and the second conductive structure to detect whether the gate dielectric layer is well insulated or not so as to realize the detection of the gate dielectric layer. The second conductive structure completely covers the connection region of the active region and maintains a low contact resistance.
It should be noted that, in the manufacturing method provided by the embodiment of the present invention, the first conductive structure and the second conductive structure may be formed separately in steps as described above; and can be formed simultaneously in the same step, and the specific forming process will be described in detail in the following embodiments.
According to the manufacturing method of the semiconductor device testing structure provided by the embodiment of the invention, after the gate dielectric layer is formed, the first conducting structure and the second conducting structure are formed, and then the performance of the gate dielectric layer can be detected by applying voltage to the first conducting structure and the second conducting structure. Compared with a process method which can realize pad connection and perform electrical test after the first metal layer is manufactured, the semiconductor device test structure manufacturing method provided by the embodiment of the invention at least omits the process time of side wall oxide space, interlayer dielectric layer ILD of a grid and the first metal layer, through hole CT and first layer metal M1loop, saves the use of mask plates of corresponding processes, greatly reduces the number of the mask plates, and can reduce the manufacturing cost of the semiconductor device test structure while improving the research and development speed.
Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor device testing structure, please refer to fig. 2-4, wherein fig. 2 is a schematic top view of the semiconductor device testing structure provided by the embodiment of the present invention, and fig. 3 is a schematic cross-sectional structure along AA' in fig. 2; FIG. 4 is a schematic cross-sectional view taken along line BB' in FIG. 2; the semiconductor device test structure in the embodiment of the invention comprises:
a substrate (not shown in the figures);
a plurality of isolation structures located in the surface of the substrate, as shown in fig. 3 and 10 in fig. 4, wherein the isolation structures 10 define an active region 11 and a connection region 12, the active region 11 and the connection region 12 are electrically connected in the substrate, and the active region 11 and the connection region 12 are isolated from each other at the surface of the substrate by the isolation structures 10;
the gate dielectric layer 13 is positioned on the active region 11, and the gate dielectric layer 13 can completely cover the active region 11;
a first conductive structure 14 located on the gate dielectric layer 13, wherein the first conductive structure 14 may completely cover the gate dielectric layer 13;
a second conductive structure 15 on said connection region 12.
In this embodiment, the specific material of each structure is not limited, and optionally, the isolation structure 10 is an insulating material, and may be an oxide, such as silicon oxide; the substrate may be a monocrystalline silicon material and the corresponding isolation structure may be silicon oxide. In this embodiment, the gate dielectric layer 13 may be obtained by oxidizing a single crystal silicon substrate, and therefore, the gate dielectric layer 13 may also be made of silicon oxide. In this embodiment, the first conductive structure 14 and the second conductive structure 15 may be made of the same material, and are both polysilicon, so that the first conductive structure and the second conductive structure may be formed at one time. The active region and the connection region may be intentionally doped layers formed by intentionally doping a single crystalline silicon substrate.
It should be noted that, in order to facilitate the contact between the probe of the detection circuit and the first conductive structure and the second conductive structure, in this embodiment, as shown in fig. 5 to fig. 7, the first conductive structure may include a first sub-conductive structure 14 'located on the gate dielectric layer 13 and a first pad 16 located outside the gate dielectric layer 13 and electrically connected to the first sub-conductive structure 14'; the second conductive structure includes a second sub-conductive structure 15 'located on the connection region 12 and a second pad 17 located outside the connection region 12 and electrically connected to the second sub-conductive structure 15'.
Because the active region and the connection region are both intentionally doped monocrystalline silicon and have a conductive function, and the first conductive structure and the second conductive structure also have a conductive function, a detection circuit is formed by applying different voltages to the first conductive structure 14 and the second conductive structure 15, if the gate dielectric layer is well insulated, no current can be generated, and if the gate dielectric layer has a leakage problem, a current is formed in the detection circuit, so that the quality of the gate dielectric layer is detected.
The manufacturing method of the semiconductor device test structure can be formed by adopting different manufacturing steps, but the inventor finds that the corresponding semiconductor device test structure can be manufactured by adopting at least 3 mask plates.
The two manufacturing methods are described in detail with reference to the accompanying drawings, and other methods capable of forming a semiconductor device test structure by using 3 mask plates are also within the protection scope of the embodiment of the present invention, and are not described in detail in the embodiment of the present invention.
The first method is specifically as follows:
referring to fig. 5-10, fig. 5 is a top view of a semiconductor device test structure according to an embodiment of the present invention; FIG. 6 is a schematic cross-sectional view along AA' in FIG. 5; FIG. 7 is a schematic cross-sectional view taken along line BB' in FIG. 5; FIG. 8 is a schematic top view of a first mask; FIG. 9 is a schematic top view of a second mask; fig. 10 is a schematic top view of a third mask.
Firstly, providing a first mask plate, as shown in fig. 8, wherein the pattern of the first mask plate corresponds to the pattern of the isolation structure to be formed; in this embodiment, the pattern of the first mask is complementary to the pattern of the isolation structure to be formed, as shown in fig. 8, the filled portion is a hollow portion in actual production, and the first mask shields a portion of the substrate of the isolation structure to be formed.
Etching the substrate based on the first mask plate to form a first groove; in this embodiment, the region outside the isolation structure to be formed may be covered by the photoresist by coating the photoresist, and the region to be formed may not be covered by the photoresist, so that the exposed substrate may be etched to form the first groove.
And depositing an insulating material, and filling the first groove to form the isolation structure. The insulating material filled in this embodiment may be silicon oxide, silicon nitride, or other insulating materials, which is not limited in this embodiment. Through the above steps, a plurality of isolation structures are formed on the substrate, as indicated by reference numeral 10 in fig. 6 and 7.
Then, forming a gate dielectric layer body on the substrate, wherein the gate dielectric layer body can be formed by adopting different preparation methods, and can be obtained by adopting an oxidized substrate in the optional embodiment; it should be noted that, since the isolation structure is an insulating structure, usually silicon oxide, when the substrate is oxidized, only the surface of the substrate outside the isolation structure is oxidized to form an oxide layer, that is, a gate dielectric body is formed.
Providing a second mask plate, wherein the pattern of the second mask plate corresponds to the pattern of the gate dielectric layer to be formed; as shown in fig. 9, the pattern of the second mask in this embodiment is the same as the pattern of the gate dielectric layer to be formed, that is, the filling portion shown in fig. 9 is a hollow portion and is also a portion corresponding to the gate dielectric layer.
And etching the gate dielectric layer body based on the second mask plate, reserving the gate dielectric layer body above the active region, removing the gate dielectric layer body in other regions, and forming the gate dielectric layer.
After the second mask plate covers the gate dielectric layer body, photoresist covering is carried out on the hollowed-out area, and the gate dielectric layer body is removed through an etching process in other areas which are not covered by the photoresist, so that only the gate dielectric layer body above the active area is reserved to form a gate dielectric layer, and the gate dielectric layer completely covers the active area.
Forming a whole layer of conductive material on the gate dielectric layer, the isolation structure and the substrate;
providing a third mask plate, wherein patterns of the third mask plate correspond to the patterns of the first conductive structure and the second conductive structure to be formed;
and etching the whole layer of conductive material based on the third mask plate, reserving the conductive material covering the gate dielectric layer to form a first conductive structure, and forming a second conductive structure by the conductive material electrically connected with the connection area.
In this embodiment, the first conductive structure and the second conductive structure are formed in the same step, and the same mask plate is used. Specifically, as shown in fig. 10, the third mask plate includes a first sub conductive structure region located in the gate dielectric layer region and a first pad region connected to the first sub conductive structure region; and a second sub-conductive structure region at the connection region and a second pad region connected to the second sub-conductive structure region.
As shown in fig. 10, the third mask pattern is the same as the patterns of the first conductive structure and the second conductive structure to be formed, and the filled portion in fig. 10 is a hollow portion, and the photoresist is formed on the region where the first conductive structure and the second conductive structure are to be formed through the hollow portion to shield the region where the first conductive structure and the second conductive structure are to be formed, so that the conductive material in other regions is etched and removed, and the remaining conductive material forms the first conductive structure and the second conductive structure.
According to the manufacturing method of the semiconductor device testing structure, 3 mask plates are adopted to form the semiconductor device testing structure, different voltages are applied to the first conducting structure and the second conducting structure of the testing structure, and the gate dielectric layer is subjected to electrical testing, so that the problem that in the prior art, the research and development learning period of a semiconductor device is long due to the fact that electrical testing is carried out after a plurality of back-end processes are completed is solved, the use of the mask plates is saved, and the cost in the research and development process can be reduced.
The second manufacturing method provided by the embodiment of the invention is as follows:
referring to fig. 11-16, fig. 11 is a top view of a semiconductor device test structure according to an embodiment of the present invention; FIG. 12 is a schematic cross-sectional view taken along AA' in FIG. 11; FIG. 13 is a schematic cross-sectional view taken along line BB' in FIG. 11; fig. 14 is a schematic top view of the first mask; fig. 15 is a schematic top view of a second mask; fig. 16 is a schematic top view of a third mask.
The semiconductor device test structure shown in fig. 11-13 also includes:
a substrate (not shown in the figures);
a plurality of isolation structures located in the surface of the substrate, as shown in fig. 12 and 20 in fig. 13, wherein the isolation structures 20 define an active region 21 and a connection region 22, the active region 21 and the connection region 22 are electrically connected in the substrate, and the active region 21 and the connection region 22 are isolated from each other at the surface of the substrate by the isolation structures 20;
the gate dielectric layer 23 is positioned on the active region 21, and the gate dielectric layer 23 completely covers the active region 21;
the first sub-conductive structure 24 is positioned on the gate dielectric layer 23, and the first sub-conductive structure 24 completely covers the gate dielectric layer 23;
a second sub-conductive structure 25 on the connection region 22.
Also included in this embodiment is a first bond pad 26 electrically connected to the first sub-conductive structure 24, and a second bond pad 27 electrically connected to the second sub-conductive structure 25.
The manufacturing method comprises the following steps:
firstly, as in the previous manufacturing method, providing a first mask plate, as shown in fig. 14, wherein the pattern of the first mask plate corresponds to the pattern of the isolation structure to be formed; in this embodiment, the pattern of the first mask is complementary to the pattern of the isolation structure to be formed, as shown in fig. 14, the filled portion is a hollow portion in actual production, and the first mask shields a portion of the substrate of the isolation structure to be formed.
Then, oxidizing the substrate to form a gate dielectric layer body on the substrate; it should be noted that, since the isolation structure is an insulating structure, usually silicon oxide, when the substrate is oxidized, only the surface of the substrate outside the isolation structure is oxidized to form an oxide layer, that is, a gate dielectric body is formed.
Forming a whole first conductive layer on the gate dielectric layer body; in this embodiment, the first conductive layer is formed on the gate dielectric body and the isolation structure by a deposition process, so that the first conductive layer is a whole layer structure.
Providing a fourth mask plate, wherein the pattern of the fourth mask plate corresponds to the pattern of the first conductive structure to be formed; as shown in fig. 15, the fourth mask pattern is the same as the pattern of the first conductive structure to be formed. The filling area of the fourth mask plate is a hollow area, and the conductive material is covered on the hollow area by adopting photoresist.
And etching the gate dielectric layer body and the first conductive layer based on the fourth mask plate, and reserving the gate dielectric layer body and the first conductive layer above the active region to form the gate dielectric layer and the first conductive structure. And etching the part which is not covered by the photoresist to reserve the first conductive layer only above the active area, and reserving the conductive layer of the first pad area connected with the active area when the first conductive structure comprises the first pad so as to form the first pad.
Then, forming a whole second conductive layer on the isolation structure, the substrate and the first conductive structure; that is, the entire second conductive layer is formed through a deposition process.
Providing a fifth mask plate, wherein the fifth mask plate corresponds to the pattern of the second conductive structure; as shown in fig. 16, the pattern of the fifth mask is the same as the pattern of the second conductive structure, and similarly, the filling region is a hollow region, and a photoresist can be covered on the hollow region to protect the second conductive structure.
And etching the second conductive layer based on the fifth mask plate, and reserving the second conductive layer electrically connected with the connection area to form a second conductive structure. And removing the uncovered part of the photoresist through a photoetching process to form a second conductive structure, and similarly, when the second conductive structure comprises a second pad, reserving the conductive layer of the second pad area to form the second pad.
According to the two manufacturing methods of the semiconductor device testing structure, no matter which method is adopted, the manufacturing method for forming the semiconductor device testing structure in the embodiment of the invention can form the semiconductor device testing structure by adopting 3 mask plates, so that the use of the mask plates is reduced, and the manufacturing cost of the semiconductor device testing structure is reduced.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for manufacturing a semiconductor device test structure is characterized by comprising the following steps:
providing a substrate;
forming an isolation structure on the substrate, wherein the isolation structure defines an active region and a connection region, the active region and the connection region are electrically connected in the substrate, and the active region and the connection region are arranged on the surface of the substrate in an isolation mode;
forming a gate dielectric layer on the active region;
forming a first conductive structure on the gate dielectric layer;
forming a second conductive structure on the connection region;
forming a gate dielectric layer on the active region and forming a first conductive structure on the gate dielectric layer, specifically including:
oxidizing the substrate to form a gate dielectric layer body on the substrate;
forming a whole first conductive layer on the gate dielectric layer body;
providing a fourth mask plate, wherein the pattern of the fourth mask plate corresponds to the pattern of the first conductive structure to be formed;
and etching the gate dielectric layer body and the first conductive layer based on the fourth mask plate, and reserving the gate dielectric layer body and the first conductive layer above the active region to form the gate dielectric layer and the first conductive structure.
2. The method for fabricating the semiconductor device test structure according to claim 1, wherein the forming of the isolation structure on the substrate specifically comprises:
providing a first mask plate, wherein the pattern of the first mask plate corresponds to the pattern of an isolation structure to be formed;
etching the substrate based on the first mask plate to form a first groove;
and depositing an insulating material, and filling the first groove to form the isolation structure.
3. The method for fabricating the test structure of the semiconductor device according to claim 1, wherein the forming a gate dielectric layer on the active region specifically comprises:
oxidizing the substrate to form a gate dielectric layer body on the substrate;
providing a second mask plate, wherein the pattern of the second mask plate corresponds to the pattern of the gate dielectric layer to be formed;
and etching the gate dielectric layer body based on the second mask plate, reserving the gate dielectric layer body above the active region, removing the gate dielectric layer body in other regions, and forming the gate dielectric layer.
4. The method for fabricating the test structure of the semiconductor device according to claim 3, wherein the forming the first conductive structure on the gate dielectric layer and the forming the second conductive structure on the connection region specifically include:
forming a whole layer of conductive material on the gate dielectric layer, the isolation structure and the substrate;
providing a third mask plate, wherein patterns of the third mask plate correspond to the patterns of the first conductive structure and the second conductive structure to be formed;
and etching the whole layer of conductive material based on the third mask plate, reserving the conductive material covering the gate dielectric layer to form a first conductive structure, and forming a second conductive structure by the conductive material electrically connected with the connection area.
5. The method of fabricating a semiconductor device test structure of claim 1,
the first conductive structure comprises a first sub-conductive structure positioned on the gate dielectric layer and a first bonding pad positioned outside the gate dielectric layer and electrically connected with the first sub-conductive structure;
the second conductive structure comprises a second sub-conductive structure positioned on the connecting area and a second bonding pad positioned outside the connecting area and electrically connected with the second sub-conductive structure.
6. The method for fabricating the semiconductor device test structure according to claim 1, wherein the forming of the second conductive structure on the connection region specifically comprises:
forming a full-layer second conductive layer on the isolation structure, the substrate and the first conductive structure;
providing a fifth mask plate, wherein the fifth mask plate corresponds to the pattern of the second conductive structure;
and etching the second conductive layer based on the fifth mask plate, and reserving the second conductive layer electrically connected with the connection area to form a second conductive structure.
7. The method of claim 1, wherein the substrate is an intentionally doped monocrystalline silicon material, the first conductive structure and the second conductive structure are polycrystalline silicon materials, and the gate dielectric layer is an oxide layer.
8. A semiconductor device test structure formed by the method of fabricating a semiconductor device test structure of any one of claims 1-7, the semiconductor device test structure comprising:
a substrate;
the isolation structures define an active area and a connection area, the active area and the connection area are electrically connected in the substrate, and the active area and the connection area are arranged on the surface of the substrate in an isolated mode through the isolation structures;
a gate dielectric layer located on the active region;
a first conductive structure located on the gate dielectric layer;
a second conductive structure on the connection region.
9. The semiconductor device test structure of claim 8, wherein the substrate is an intentionally doped monocrystalline silicon material, the first conductive structure and the second conductive structure are polycrystalline silicon materials, and the gate dielectric layer is an oxide layer.
10. The semiconductor device test structure of claim 8,
the first conductive structure comprises a first sub-conductive structure positioned on the gate dielectric layer and a first bonding pad positioned outside the gate dielectric layer and electrically connected with the first sub-conductive structure;
the second conductive structure comprises a second sub-conductive structure positioned on the connecting area and a second bonding pad positioned outside the connecting area and electrically connected with the second sub-conductive structure.
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