KR100223750B1 - Semiconductor element isolation film manufacturing method - Google Patents
Semiconductor element isolation film manufacturing method Download PDFInfo
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- KR100223750B1 KR100223750B1 KR1019960025378A KR19960025378A KR100223750B1 KR 100223750 B1 KR100223750 B1 KR 100223750B1 KR 1019960025378 A KR1019960025378 A KR 1019960025378A KR 19960025378 A KR19960025378 A KR 19960025378A KR 100223750 B1 KR100223750 B1 KR 100223750B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000002955 isolation Methods 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000010408 film Substances 0.000 claims abstract description 73
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000010409 thin film Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 230000004888 barrier function Effects 0.000 claims abstract description 5
- 150000004767 nitrides Chemical class 0.000 claims description 18
- 239000000126 substance Substances 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims 1
- 238000007517 polishing process Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 20
- 229910052710 silicon Inorganic materials 0.000 abstract description 20
- 239000010703 silicon Substances 0.000 abstract description 20
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 238000001039 wet etching Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000009835 boiling Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체 장치에 있어서, 반도체 기판상에 마스크용 박막을 형성하는 단계; 상기 박막상에 트렌치 형성을 위한 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스터 패턴을 식각장벽으로 상기 박막과 상기 반도체 기판의 소정깊이를 식각하여 트렌치를 형성하되, 수직선상의 상기 트렌치 및 상기 포토레지스트 패턴 측벽보다 상기 박막 측벽이 더 제거되도록 식각하는 단계; 상기 포토레지스트 패턴을 제거하는 단계; 전체구조 상부에 절연막을 형성한 후, 상기 박막의 상부 표면이 드러날때까지 에치백하는 단계; 상기 박막을 제거하는 단계; 및 상기 절연막을 식각하되, 상기 트렌치된 반도체 기판 상부 모서리 아래로 내려오지 않도록 제거하는 단계를 포함해서 이루어진 소자분리막 형성방법에 관한 것으로, 소자간 전기적 절연을 위한 소자분리막 영역을 트렌치 구조로 형성하고, 소자간 절연막인 필드산화막 패턴이 트렌치된 실리콘 기판 모서리 아래로 내려오지 않도록 조정하여, 후속 트랜지스터 형성 공정시 게이트 전극용 전도막과 하부 실리콘 기판과의 접속에 의한 임계전압 강하를 제거하여 소자의 특성을 향상시킬 수 있다.A semiconductor device comprising: forming a thin film for a mask on a semiconductor substrate; Forming a photoresist pattern for forming a trench on the thin film; Forming a trench by etching the thin film and a predetermined depth of the semiconductor substrate using the photoresist pattern as an etch barrier, and etching the thin film sidewalls more than the vertical trench and sidewalls of the photoresist pattern; Removing the photoresist pattern; Forming an insulating film over the entire structure, and then etching back until the upper surface of the thin film is exposed; Removing the thin film; And etching the insulating layer to remove the insulating layer so that the insulating layer is not lowered below the upper edge of the trenched semiconductor substrate, wherein the isolation layer is formed in a trench structure for electrical isolation between devices. The field oxide pattern, which is an inter-element insulating film, is adjusted so as not to fall below the corner of the trenched silicon substrate, thereby eliminating the threshold voltage drop caused by the connection between the gate electrode conductive film and the lower silicon substrate during the subsequent transistor formation process. Can be improved.
Description
제1a도 내지 제1c도는 본 발명의 일실시예에 따른 반도체 장치의 소자분리막 형성 공정 단면도.1A to 1C are cross-sectional views of a device isolation film forming process of a semiconductor device according to an embodiment of the present invention.
제2a도 내지 제2c도는 본 발명의 다른 실시예에 따른 반도체 장치의 소자분리막 형성 공정 단면도.2A to 2C are cross-sectional views of a device isolation film forming process of a semiconductor device according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 실리콘 기판 12 : 패드 산화막11 silicon substrate 12 pad oxide film
13 : 질화막 14 : 감광막13: nitride film 14: photosensitive film
15 : 산화막15: oxide film
본 발명은 반도체 장치의 소자분리막 형성방법에 관한 것이다.The present invention relates to a method of forming an isolation film in a semiconductor device.
일반적으로, 소자분리막은 집적소자를 구성하는 개별소자를 전기적 및 구조적으로 서로 분리시켜, 각 소자가 인접한 소자의 간섭을 받지 않고 독자적으로 주어진 기능을 수행할 수 있도록 한다.In general, the device isolation film electrically and structurally separates individual devices constituting the integrated device from each other so that each device can perform a given function independently without interference from adjacent devices.
상기와 같은 소자간 절연을 위한 소자분리막을 형성하기 위한 종래 방법은 다음과 같다.The conventional method for forming the device isolation film for the inter-device insulation as described above is as follows.
먼저, 실리콘 기판 상부에 패드 산화막 및 질화막을 차례로 형성한 후, 소자 분리 마스크를 이용한 식각에 의해 질화막, 패드 산화막 및 소정깊이의 실리콘 기판을 제거하여 트렌치 구조를 형성한 다음, 전체구조 상부에 산화막을 증착한다.First, a pad oxide film and a nitride film are sequentially formed on the silicon substrate, and then a trench structure is formed by removing the nitride film, the pad oxide film and the silicon substrate having a predetermined depth by etching using an element isolation mask, and then forming an oxide film on the entire structure. Deposit.
이어서, 상기 질화막이 드러날 때까지 상기 산화막을 화학적 기계적 연마(Chemical Mechanical Polishing) 방식으로 제거하여 평탄화하고, 상기 질화막 및 상기 패드 산화막을 제거한 후, 잔류하는 산화막으로 소자간 절연막인 필드 산화막을 형성한다.Subsequently, the oxide film is removed and planarized by chemical mechanical polishing until the nitride film is exposed, and then the nitride film and the pad oxide film are removed, and then a field oxide film, which is an inter-element insulating film, is formed from the remaining oxide film.
계속해서, 활성영역의 실리콘 기판 상에 희생산화막을 성장시킨 후, 성장시킨 상기 희생산화막을 습식식각으로 제거하고 게이트 산화막을 성장시킨다.Subsequently, after the sacrificial oxide film is grown on the silicon substrate in the active region, the grown sacrificial oxide film is removed by wet etching to grow the gate oxide film.
상기와 같은 종래의 소자분리막 형성 과정에서, 상기 질화막, 패드산화막 및 희생산화막을 제거하기 위한 식각공정시 사용된 식각제(Etchant)에 의해 필드 산화막과 실리콘 기판이 접해있는 접합부위의 필드 산화막이 제거되어 필드산화막 표면이 실리콘 기판 상부 아래로 내려감에 따라 트렌치 측벽의 실리콘 기판의 일부가 노출된다. 따라서, 후속 트랜지스터 형성 공정시 게이트 전극용 전도막이 노출된 트렌치 측벽의 실리콘 기판을 덮게되어 모서리 부분이 게이트 전압에 의한 게이트의 전기장을 크게 받는다. 이에 의해, 트랜지스터의 임계전압이 낮아져서 소자의 전기적 특성을 약화시키는 문제점이 있다.In the conventional device isolation film formation process as described above, the field oxide film on the junction where the field oxide film and the silicon substrate are in contact with each other is removed by an etchant used during the etching process for removing the nitride film, the pad oxide film, and the sacrificial oxide film. As the surface oxide film surface is lowered above the silicon substrate, a part of the silicon substrate of the trench sidewall is exposed. Therefore, in the subsequent transistor formation process, the conductive film for the gate electrode covers the silicon substrate on the exposed sidewall of the trench so that the corner portion receives a large electric field of the gate due to the gate voltage. As a result, the threshold voltage of the transistor is lowered, which causes a problem of weakening the electrical characteristics of the device.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 트랜지스터의 임계 전압 저하에 의한 소자의 특성 악화를 방지하는 반도체 장치의 소자분리막 형성방법을 제공함에 그 목적이 있다.Disclosure of Invention The present invention devised to solve the above problems has an object of the present invention is to provide a method for forming a device isolation film of a semiconductor device that prevents deterioration of device characteristics due to a decrease in the threshold voltage of a transistor.
상기 목적을 달성하기 위하여 본 발명은 반도체 기판 상에 마스크용 박막을 형성하는 제1 단계; 상기 마스크용 박막 상에, 소자분리를 위한 트렌치 영역을 정의하는 포토레지스트 패턴을 형성하는 제2 단계; 상기 포토레지스트 패턴을 식각장벽으로 상기 마스크용 박막과 상기 반도체 기판을 식각하여 상기 반도체 기판 내에 트렌치를 형성하되, 식각되는 상기 마스크용 박막의 폭이 상기 트렌치 및 상기 포토레지스트 패턴의 폭보다 크도록 하여 상기 트렌치 주변의 상기 반도체 기판을 노출시키는 제3 단계; 상기 포토레지스트 패턴을 제거하는 제4 단계; 상기 제4 단계가 완료된 전체구조 상에 절연막을 형성하는 제5 단계; 상기 마스크용 박막의 상부 표면이 드러날 때까지 상기 절연막을 제거하는 제6 단계; 상기 마스크용 박막을 제거하는 제7 단계; 및 상기 절연막의 일부를 식각하여 상기 트렌치 내부를 채우며 상기 트렌치 주변의 상기 반도체 기판을 덮는 절연막으로 이루어지는 소자분리막을 형성하는 제8 단계를 포함하는 반도체 장치의 소자분리막 형성방법을 제공한다.The present invention to achieve the above object is a first step of forming a thin film for the mask on a semiconductor substrate; Forming a photoresist pattern on the mask thin film to define a trench region for device isolation; Forming a trench in the semiconductor substrate by etching the mask thin film and the semiconductor substrate using the photoresist pattern as an etch barrier, so that the width of the mask thin film to be etched is greater than the width of the trench and the photoresist pattern. Exposing the semiconductor substrate around the trench; A fourth step of removing the photoresist pattern; A fifth step of forming an insulating film on the entire structure in which the fourth step is completed; A sixth step of removing the insulating film until the upper surface of the mask thin film is exposed; A seventh step of removing the mask thin film; And an eighth step of forming an isolation layer including an insulating layer to etch a portion of the insulating layer to fill the inside of the trench and to cover the semiconductor substrate around the trench.
이하, 본 발명의 일실시예에 따른 반도체 장치의 소자분리막 형성 방법을 제1a도 내지 제1c도를 참조하여 설명한다.Hereinafter, a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1A to 1C.
먼저, 제1a도에 도시한 바와 같이 실리콘 기판(10) 상부에 패드 산화막(11) 및 질화막(12)을 차례로 형성한 후, 활성영역과 오버랩되는 감광막(13)을 형성한 다음, 상기 감광막(13)을 식각장벽 이용한 식각(Etch) 공정으로 상기 질화막(12), 패드 산화막(11) 및 소정깊이의 실리콘 기판(10)을 제거하여 트렌치 구조를 형성하되, 전자(electron)의 세기와 식각기(Etching Species)의 기능을 응용하여 동방향 및 비등방향 식각이 이루어지도록 조절함으로써, 상기 질화막(12) 및 패드 산화막(11)의 수직방향 뿐만 아니라 수평방향으로도 식각이 이루어지도록하여 트렌치된 실리콘 기판의 입구보다 넓게 형성한다.First, as shown in FIG. 1A, the pad oxide film 11 and the nitride film 12 are sequentially formed on the silicon substrate 10, and then the photosensitive film 13 overlapping the active region is formed. 13) to form a trench structure by removing the nitride film 12, the pad oxide film 11 and the silicon substrate 10 of a predetermined depth by an etching process using an etching barrier, the strength and etching of the electron (electron) By applying the function of (Etching Species) to adjust the etching in the same direction and boiling direction, the silicon substrate trenched by etching not only in the vertical direction but also in the horizontal direction of the nitride film 12 and the pad oxide film 11 Form wider than the entrance.
이어서, 제1b도에 도시한 바와 같이 상기 감광막(13)을 제거한 후, 전체구조 상부에 산화막(14)을 증착한 다음, 상기 질화막(12)이 드러날 때까지 화학적 기계적 연마 방식에 의해 상기 산화막(14)을 제거하여 평탄화한다.Subsequently, as shown in FIG. 1B, after the photosensitive film 13 is removed, the oxide film 14 is deposited on the entire structure, and then the oxide film is formed by chemical mechanical polishing until the nitride film 12 is exposed. 14) Remove and flatten.
마지막으로, 제1c도에 도시한 바와 같이 상기 질화막(12) 및 패드 산화막(11)을 습식식각에 의해 제거한 다음, 상기 산화막(14)을 적절한 습식긱각에 의해 제거하여 필드산화막(14a)을 형성한다. 이에 따라, 상기 필드 산화막 패턴이 트렌치된 실리콘 기판 모서리 아래로 내려오지 않게 된다.Finally, as shown in FIG. 1C, the nitride film 12 and the pad oxide film 11 are removed by wet etching, and then the oxide film 14 is removed by an appropriate wet gig angle to form a field oxide film 14a. do. As a result, the field oxide layer pattern does not fall below the edge of the trenched silicon substrate.
이하, 본 발명의 다른 실시예에 따른 반도체 장치의 소자분리막 형성 방법을 제2a도 내지 제2c도를 참조하여 설명한다.Hereinafter, a method of forming an isolation layer of a semiconductor device according to another exemplary embodiment of the present invention will be described with reference to FIGS. 2A through 2C.
먼저, 제2a도에 도시한 바와 같이 실리콘 기판(20) 상부에 패드 산화막(21) 및 질화막(22)을 차례로 형성한 후, 소자분리 마스크를 이용한 식각공정에 의해 상기 실리콘 기판(20)이 드러날 때까지 상기 질화막(22), 패드 산화막(21)을 제거한다.First, as shown in FIG. 2A, the pad oxide layer 21 and the nitride layer 22 are sequentially formed on the silicon substrate 20, and then the silicon substrate 20 is exposed by an etching process using an element isolation mask. The nitride film 22 and the pad oxide film 21 are removed until it is removed.
이어서, 제2b도에 도시한 바와 같이 전체구조 상부에 제1 산화막을 증착한 후, 비등방성 전면식각에 의해 상기 패드 산화막(21) 및 상기 질화막(22) 측벽에 제1 산화막 스페이서(23)를 형성한 다음, 상기 질화막(22) 및 상기 산화막 스페이서(23)를 식각장벽으로한 식각 공정에 의해 소정깊이의 실리콘 기판(20)을 제거하여 트렌치 구조를 형성한다.Subsequently, as illustrated in FIG. 2B, after depositing the first oxide layer on the entire structure, the first oxide spacer 23 is disposed on sidewalls of the pad oxide layer 21 and the nitride layer 22 by anisotropic front etching. After the formation, a trench structure is formed by removing the silicon substrate 20 having a predetermined depth by an etching process using the nitride film 22 and the oxide spacer 23 as an etch barrier.
마지막으로, 제2c도에 도시한 바와 같이 전체구조 상부에 제2 산화막(24)을 증착하고, 화학적 기계적 연마 방식에 의해 상기 질화막(22)이 드러날 때까지 상기 제2 산화막(24)을 제거하여 평탄화한 다음, 상기 질화막(22) 및 패드 산화막(21)을 습식식각에 의해 제거하고, 상기 제1 및 제2 산화막(23, 24)을 적절한 습식식각에 의해 제거하여 필드 산화막(24a)을 형성한다. 이에 따라, 상기 필드 산화막 패턴이 트렌치된 실리콘 기판(20) 모서리 아래로 내려오지 않게 된다.Finally, as shown in FIG. 2C, the second oxide film 24 is deposited on the entire structure, and the second oxide film 24 is removed until the nitride film 22 is exposed by chemical mechanical polishing. After the planarization, the nitride layer 22 and the pad oxide layer 21 are removed by wet etching, and the first and second oxide layers 23 and 24 are removed by appropriate wet etching to form the field oxide layer 24a. do. As a result, the field oxide layer pattern does not fall below the corner of the trenched silicon substrate 20.
상기와 같이 이루어지는 본 발명은 소자간 전기적 절연을 위한 소자분리막 영역을 트렌치 구조로 형성하고, 소자간 절연막인 필드산화막 패턴이 트렌치된 실리콘 기판 모서리 아래로 내려오지 않도록 조정하여, 후속 트랜지스터 형성 공정시 게이트 전극용 전도막과 하부 실리콘 기판과의 접속에 의한 임계전압 강하를 제거하여 소자의 특성을 향상시킬 수 있다.According to the present invention, the device isolation film region for the electrical isolation between devices is formed in a trench structure, and the field oxide film pattern, which is an inter-device insulating film, is adjusted so as not to fall below the corner of the trenched silicon substrate, so that the gate is formed during the subsequent transistor formation process. The characteristics of the device can be improved by removing the threshold voltage drop caused by the connection between the electrode conductive film and the lower silicon substrate.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.
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KR100431087B1 (en) * | 2002-07-12 | 2004-05-12 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
KR100857575B1 (en) * | 2002-06-21 | 2008-09-09 | 매그나칩 반도체 유한회사 | Method for forming the Isolation Layer of Semiconductor Device |
KR100984855B1 (en) * | 2003-07-26 | 2010-10-04 | 매그나칩 반도체 유한회사 | Method for forming element isolation layer of semiconductor device |
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KR100431087B1 (en) * | 2002-07-12 | 2004-05-12 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
KR100984855B1 (en) * | 2003-07-26 | 2010-10-04 | 매그나칩 반도체 유한회사 | Method for forming element isolation layer of semiconductor device |
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