CN104538382A - Electrical performance test structure and manufacturing method and electrical performance testing process thereof - Google Patents
Electrical performance test structure and manufacturing method and electrical performance testing process thereof Download PDFInfo
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- CN104538382A CN104538382A CN201510003666.7A CN201510003666A CN104538382A CN 104538382 A CN104538382 A CN 104538382A CN 201510003666 A CN201510003666 A CN 201510003666A CN 104538382 A CN104538382 A CN 104538382A
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Abstract
The invention relates to the technical field of semiconductor manufacturing, in particular to an electrical performance test structure and a manufacturing method and an electrical performance testing process of the electrical performance test structure. The electrical performance testing process can be applied to testing of electrical performance of a gate oxide before manufacturing of an interlayer dielectric layer and before a back-end process. Namely, a micro pad connected with the gate oxide and a substrate is arranged on the electrical performance test structure with a grid electrode, the testing process difficulty is greatly lowered, and on the premise of not damaging a wafer substrate, the electrical performance test on the gate oxide of an NMOS component and a PMOS component is achieved, so that test samples are prevented from being damaged, the test efficiency is greatly improved, and the process cost is effectively lowered.
Description
Technical field
The present invention relates to semiconducter device testing technical field, particularly relate to a kind of testing electrical property structure and preparation method thereof, testing electrical property technique.
Background technology
In the preparation process of semiconductor device, according to some special requirement, at interlayer dielectric layer (Inter Layer Dielectrics, be called for short ILD) formed before, sometimes needing when not forming testing cushion (probing pad), measuring the electric property of the gate oxide (gateoxide) of preparation.
The method of traditional measurement gate oxide mainly comprises nano-probe and measures method (Nanoprober) and manually measure method (Manual prober), but, when adopting the gate oxide of nano-probe measurement method to the semiconductor device of preparation electrically to measure, need when preparing sample to destroy wafer (broke the wafer), and prepare chronic (the long time for sample preparation) of the testing time of sample and nano-probe, need preparation and the test that within 3 ~ 4 hours, just can complete 1 sample, testing efficiency lower (low throughput), if need the measurement obtaining the gate oxide covering the distribution of whole wafer, need preparation tens samples, the time in general needs one week or a few week just can complete sample preparation and test, and then make testing cost higher (high cost).
Simultaneously, when adopting the gate oxide of manual measurement method to the semiconductor device of preparation electrically to measure, need under an optical microscope, the probe (tip) of the needle point that direct use is very thin, cautiously slowly touch corresponding polysilicon gate (gate poly) and other region do not destroyed between polysilicon gate level, need to realize from the back side (wafer backside) of wafer being electrically connected with substrate (substrate) simultaneously, and then can make manually to measure method and have the following disadvantages:
1) be difficult to tell test structure (teststructure) figure under light microscope (optical system), and due to the size of polysilicon gate and probe tip all very little, and probe tip is comparatively large relative to the broadband of polysilicon gate, and then the difficulty of aiming at when making to test is very large.
2) specimen breakdown (sample damage) is easily caused.
3) need to arrange a syndeton, be connected with substrate from wafer rear for during test, and then increase the test resistance (high substrate resistance) of substrate
4) wafer of P type doping can only be applied in the measurement technique of the electric capacity of nmos device (having substrate P).
Summary of the invention
For above-mentioned technical problem, this application provides a kind of testing electrical property structure, comprising:
Substrate, is provided with gate regions, and is positioned at the first test section and second test section of these both sides, gate regions;
Gate oxide, covers the described substrate being positioned at described gate regions, and extends in described first test section of part;
Grid, covers on described gate oxide;
Wherein, the described grid extending to described first test section is defined as the first miniature pad, the described substrate that part is positioned at described second test section is defined as the second miniature pad, and utilizes described first miniature pad and described second miniature pad to carry out testing electrical property technique to described gate oxide.
As a preferred embodiment, in above-mentioned testing electrical property structure:
Also be provided with the first fleet plough groove isolation structure in described substrate, and this first fleet plough groove isolation structure is across described gate regions and described first test section;
Described first miniature pad is positioned on described first fleet plough groove isolation structure.
As a preferred embodiment, in above-mentioned testing electrical property structure:
The second fleet plough groove isolation structure and the 3rd isolation structure is also provided with in described substrate, described second fleet plough groove isolation structure is arranged in described gate regions in the region closing on described second test section, and described 3rd fleet plough groove isolation structure is arranged in the substrate of described second test section away from the outside of side, described gate regions;
Wherein, described second miniature pad is arranged between described second fleet plough groove isolation structure and described 3rd fleet plough groove isolation structure.
As a preferred embodiment, in above-mentioned testing electrical property structure:
Described first miniature pad and described second miniature pad are all greater than 10um × 10um for the length and width size on the surface tested.
As a preferred embodiment, in above-mentioned testing electrical property structure:
Described first miniature pad and described second miniature pad are (20 ~ 30um) × (20 ~ 30um) for the length and width size on the surface tested.
As a preferred embodiment, in above-mentioned testing electrical property structure:
Described first miniature pad is less than 30% of described gate upper surface area for the area on the surface tested.
Present invention also provides a kind of method preparing testing electrical property structure, can be used for the testing electrical property structure prepared described in above-mentioned any one, described method comprises:
There is provided the substrate that is provided with gate regions, the first test section and the second test section, and described first test section and the second test section lay respectively at the both sides of described gate regions;
On the gate regions of described substrate, prepare gate oxide and grid successively, and this gate oxide and described grid all extend in described first test section;
The described grid that definition is positioned at described first test section is the first miniature pad, and the section substrate that definition is positioned at described second test section is the second miniature pad;
Described first miniature pad and described second miniature pad is utilized to carry out testing electrical property technique to described gate oxide.
As a preferred embodiment, above-mentioned prepares in the method for testing electrical property structure:
Also be provided with the first fleet plough groove isolation structure in described substrate, and this first fleet plough groove isolation structure is across described gate regions and described first test section;
Described first miniature pad is positioned on described first fleet plough groove isolation structure.
As a preferred embodiment, above-mentioned prepares in the method for testing electrical property structure:
The second fleet plough groove isolation structure and the 3rd isolation structure is also provided with in described substrate, described second fleet plough groove isolation structure is arranged in described gate regions in the region closing on described second test section, and described 3rd fleet plough groove isolation structure is arranged in the substrate of described second test section away from the outside of side, described gate regions;
Wherein, described second miniature pad is arranged between described second fleet plough groove isolation structure and described 3rd fleet plough groove isolation structure.
Present invention also provides a kind of testing electrical property technique, comprising:
Testing electrical property structure described in one above-mentioned any one is provided;
Two probes are utilized to be electrically connected with described first miniature pad and described second miniature pad, to carry out testing electrical property technique to described gate oxide respectively.
In sum, owing to have employed technique scheme, present patent application describes a kind of testing electrical property structure and preparation method thereof, testing electrical property technique, can be applicable at interlayer dielectric layer and back-end process (Back End Of Line, be called for short BEOL) before, testing electrical property technique is carried out to gate oxide, namely by the gate oxide testing electrical property structure being formed with grid, prepare the miniature pad (mini-pad) be connected with gate oxide and substrate respectively, while greatly reducing measurement technology difficulty, can also under the prerequisite need not carrying out fragmentation (do not need broke thewafer) to wafer, realize carrying out testing electrical property to the gate oxide of nmos device and PMOS device, effectively to avoid to the damage that causes of test sample simultaneously, greatly enhance productivity, effective reduction testing cost.
Accompanying drawing explanation
Fig. 1 is the vertical view of testing electrical property structure in the embodiment of the present application;
Fig. 2 is the cutaway view of testing electrical property structure in the embodiment of the present application;
Fig. 3 is the schematic flow sheet of the method preparing testing electrical property structure in the embodiment of the present application.
Embodiment
Testing electrical property structure in the application and preparation method thereof, testing electrical property technique, all can be applicable in the testing electrical property technique of gate oxide, namely before interlayer dielectric layer and last part technology step, miniature pad prepared by the sample being formed with grid structure, for the testing electrical property of its gate oxide, relative to traditional structure &processes, weld pad (pad) is not also formed owing to now testing on sample, traditional nano-probe test needs to destroy wafer, and then make whole wafer loss, greatly increase the cost of test technology, its process cycle is also longer, adopts and manually measures then easily damage measure samples devices structure, cause measurement inaccurate, and technology difficulty is large, then by forming the first miniature pad be connected with gate oxide on grid structure in the embodiment of the application, pick-up area is prepared the second miniature pad be connected with substrate, and utilize the first above-mentioned miniature pad and the gate oxide of the second miniature pad to test sample to carry out testing electrical property, and then (namely wafer is not destroyed while avoiding destroying wafer, when follow-up needs, can also be carried out other produce), can also avoid causing damage to test sample, guarantee the precision measured, and measurement technology difficulty can be reduced, effectively increase work efficiency and reduce process costs.
Just with specific embodiment, the application is further described by reference to the accompanying drawings below, but it is not as the restriction of the application.
Embodiment one
Fig. 1 is the vertical view of testing electrical property structure in the embodiment of the present application, and Fig. 2 is the cutaway view of testing electrical property structure in the embodiment of the present application; As shown in Fig. 1 ~ 2, the testing electrical property structure in the present embodiment comprises:
Substrate 1, this substrate 1 is provided with the first fleet plough groove isolation structure (STI) 11, second fleet plough groove isolation structure 12 and the 3rd fleet plough groove isolation structure 13, and this substrate 1 is also provided with gate regions 4, and be positioned at the first test section 5 and the second test section 6 of both sides, gate regions 4; wherein, across the first test section 5 and gate regions 4, (namely a part for this first fleet plough groove isolation structure 11 is arranged in the first above-mentioned test section 5 to the first above-mentioned fleet plough groove isolation structure 11, remainder is then arranged in gate regions 4, as shown in Figure 2, the most areas of this first fleet plough groove isolation structure 11 is arranged in the first test section 5), the second above-mentioned fleet plough groove isolation structure 12 is then arranged in the region (namely this second fleet plough groove isolation structure 12 closes on the second test section 6 and is arranged in gate regions 4) that the second test section 6 is closed in gate regions 4, above-mentioned the 3rd fleet plough groove isolation structure 13 is arranged in the substrate 1 of the second test section 6 away from the outside of side, gate regions 4 and (the second fleet plough groove isolation structure 12 and the 3rd shallow trench isolation is set as the second test section 6 from the substrate between 13), and the 3rd fleet plough groove isolation structure 13 also and between the second above-mentioned fleet plough groove isolation structure 12 has default distance, so that follow-up substrate 1 between this second fleet plough groove isolation structure 12 and the 3rd fleet plough groove isolation structure 13 arranges miniature pad, for follow-up test technology.
Further, the substrate being positioned at gate regions 4 is provided with gate oxide 2, and this gate oxide 2 also extends in the first test section 5, to cover the portion of upper surface of the first fleet plough groove isolation structure 11 being arranged in this first test section 5, grid 3 covers the upper surface of above-mentioned gate oxide 2.
Further, be arranged in the first test section 5 at above-mentioned grid 2 and be also provided with the first pad zone 52, this first pad zone 52 is closed on gate regions 4 and is arranged, and the substrate 1 being arranged in the second test section 6 is provided with the second pad zone 61, this second pad zone 61 is also closed on gate regions 4 and is arranged on substrate 1, and namely above-mentioned first pad zone 52 and the second pad zone 61 are all for the preparation of follow-up normal weld pad.
Further, in the first above-mentioned test section 5, the grid (being namely arranged in the grid structure between side wall (figure does not indicate) and the first pad zone 52) that definition closes on the first above-mentioned pad zone 52 is the first miniature pad (mini-pad) 51; In the second above-mentioned test section 6, on substrate 1 between the second fleet plough groove isolation structure 12 and the 3rd fleet plough groove isolation structure 13, the substrate (substrate namely between the 3rd fleet plough groove isolation structure 13 and the second pad zone 61) closing on the second pad zone 61 is defined as the second miniature pad 62; Follow-up, the first above-mentioned miniature pad 51 and the second miniature pad 62 pairs of gate oxides 2 can be utilized to carry out testing electrical property.
Preferably, the size of the above-mentioned first miniature pad 51 and the second miniature pad 62 is all less than the size of normal weld pad (normal pad), as long as it can meet the demand (should be easy enough for manual probing) of follow-up measurement technique middle probe grafting, the size of the first miniature pad 51 as escribed above and the second miniature pad 62 is all greater than 10um × 10um for the length and width size on the surface tested, and is preferably chosen as (20 ~ 30um) × (20 ~ 30um).
Preferably, above-mentioned first miniature pad 51 and the second miniature pad 62 all can be square for the surface configuration measured, the the first miniature pad 51 be defined in above grid 3 is less than 30% of the upper surface area of grid 3 for the surface area measured, bring negative effect to avoid it to grid structure; Such as, a gate oxide test structure is of a size of 50um × 100um, then the size being formed in the first miniature pad 51 on grid is then less than 40um × 40um.
Preferably, in the present embodiment, testing electrical property structure is arranged first miniature pad 51 and the second miniature pad 62 all can be one or more, as long as test technology demand can be met, and not affecting the basis of the setting of samples devices structure, the quantity of miniature pad test can be arranged according to concrete technology demand.
It should be noted that; after preparing gate oxide 2 and grid 3; sidewall structure 7 (namely as shown in Figure 2 structure) also can be prepared on the sidewall of this gate oxide 2 and grid 3; to isolate grid 3 and gate oxide 2 and to protect; but short and sweet in order to figure; do not illustrate with sidewall structure 7 graph of a correspondence in Fig. 2 in FIG in the present embodiment, the grid 2 namely in Fig. 1 and the sidewall of gate oxide 3 are also provided with sidewall structure.
Embodiment two
Fig. 3 is the schematic flow sheet of the method preparing testing electrical property structure in the embodiment of the present application; As shown in Figures 1 to 3, a kind of preparation method of testing electrical property structure, can be applicable to prepare the testing electrical property structure in embodiment one, the method comprises:
First, provide a substrate 1, and some fleet plough groove isolation structures are set in this substrate 1; Preferably, can the first fleet plough groove isolation structure 11, second fleet plough groove isolation structure 12 and the 3rd fleet plough groove isolation structure 13 be set in this substrate 1, and the second above-mentioned fleet plough groove isolation structure 12 is between the first fleet plough groove isolation structure 11 and the 3rd fleet plough groove isolation structure 13, and substrate between the second fleet plough groove isolation structure 12 and the 3rd fleet plough groove isolation structure 13 can form pick-up area (pickup).
Further, gate regions 4 is set at above-mentioned substrate 1 and is positioned at the first test section 5 and the second test section 6 of these both sides, gate regions 4, and close in the region of gate regions 4 in the first test section 5 first pad zone 52 is set, close in the second test section 6 in the region of gate regions 4 and arrange the second pad zone 61, this first pad zone 52 and the second pad zone 61 all can be used for the conventional weld pad (pad) of follow-up preparation; The first above-mentioned fleet plough groove isolation structure 11 is across the first test section 5 and gate regions 4, second fleet plough groove isolation structure 12 closes on the second test section 6 and is arranged in the substrate 1 of gate regions 4,3rd fleet plough groove isolation structure 13 is arranged in the substrate 1 of the second test section 6 away from the outside of side, gate regions 4, and this second pad zone 61 also with between the second fleet plough groove isolation structure 12 has a distance preset, so that follow-up substrate 1 between this second fleet plough groove isolation structure 12 and the 3rd fleet plough groove isolation structure 13 defines the miniature pad for testing.
Secondly, a gate oxide 2 is deposited on the gate regions 4 and the first test section 5 of above-mentioned substrate 1, this gate oxide 2 covers the portion of upper surface being positioned at the upper surface of gate regions 4 substrate 1, the upper surface being positioned at the first fleet plough groove isolation structure of gate regions and part second fleet plough groove isolation structure 12, this gate oxide 2 also extends in the first test section 5 simultaneously, covers the upper surface being arranged in the first test section 5 first fleet plough groove isolation structure.
Afterwards, continue to prepare grid 3 (i.e. the upper surface of the above-mentioned gate oxide 2 of this grid 3 all standing) on the upper surface of above-mentioned gate oxide 2 after, the sidewall that side wall covers this grid 3 and gate oxide 2 is prepared.
Finally, can according to technique needs, the part of grid pole 3 being arranged in the first test section 5 is defined as the first miniature pad 51, this first miniature pad 51 closes on the first above-mentioned pad zone 52 and carries out predefine, simultaneously in the section substrate (being namely arranged in the section substrate of pick-up area) 1 being arranged in the second test section 6 and closing on the second pad zone 61 is defined as the second miniature pad 62; The first above-mentioned miniature pad 51 and the second miniature pad 62 pairs of gate oxides 2 are utilized to carry out testing electrical property.
Preferably, in the present embodiment, can on the Process ba-sis that tradition prepares the structure of grid, a segment distance is respectively extended in the two ends of grid 3, the first above-mentioned miniature pad 51 and the second miniature pad 62 is formed for definition, namely all extending a segment distance to a direction when preparing gate oxide 2 and grid 3, making it exceed a part outside follow-up preparation pad region, to form miniature pad district; Meanwhile, when forming fleet plough groove isolation structure in substrate 1 can in above-mentioned side in the opposite direction on extend one section of pick-up area, for the formation of pad miniature in successive substrates.
In addition, because the preparation method of testing electrical property structure in the present embodiment is the processing step that basis based on embodiment one is carried out, namely its testing electrical property structure prepared also comprises in above-described embodiment one all technical characteristics of setting forth, in order to make specification short and sweet, just will not tire out at this and state, but the technical scheme in the present embodiment comprises corresponding technical characteristic described in embodiment one.
Preferably, the size of the above-mentioned first miniature pad 51 and the second miniature pad 62 is all less than the size of normal weld pad (normal pad), as long as it can meet the demand (should be easy enough for manual probing) of follow-up measurement technique middle probe grafting, the size of the first miniature pad 51 as escribed above and the second miniature pad 62 is all greater than 10um × 10um for the length and width size on the surface tested, and is preferably chosen as (20 ~ 30um) × (20 ~ 30um).
Preferably, above-mentioned first miniature pad 51 and the second miniature pad 62 all can be square for the surface configuration measured, the the first miniature pad 51 be defined in above grid 3 is less than 30% of the upper surface area of grid 3 for the surface area measured, bring negative effect to avoid it to grid structure; Such as, a gate oxide test structure is of a size of 40um × 100um, then the size being formed in the first miniature pad 51 on grid is then less than 40um × 40um.
Preferably, define in testing electrical property structure in the present embodiment first miniature pad 51 and the second miniature pad 62 all can be one or more, as long as it can meet test technology demand, and not affecting on the basis of samples devices vibrational power flow, the quantity of above-mentioned miniature pad test can be arranged according to concrete technology demand.
Embodiment three
Based on the basis of embodiment one and embodiment two, based on above-mentioned testing electrical property structure, as shown in Figures 1 to 3, when carrying out testing electrical property to gate oxide 2, can utilize two probes respectively pad 51 miniature with above-mentioned first and the second miniature pad 62 be electrically connected, and then testing electrical property technique is carried out to this gate oxide 2.
In the present embodiment testing electrical property technique be on basis based on embodiment one and embodiment two on carry out, in order to make specification short and sweet, just will not tire out at this and state, but the technical scheme in the present embodiment comprises all technical characteristic described in embodiment one and embodiment two.
In addition, because the above-mentioned first miniature pad 51 is directly connected with the grid structure being arranged in gate regions 4, second miniature pad 62 is then directly define on the pick-up area of substrate 1, and then avoid, from substrate back (i.e. wafer rear), testing electrical property is carried out to gate oxide, structure namely in the application and preparation method thereof and test technology all can be applicable in the testing electrical property technique to NMOS or PMOS device
To sum up, owing to have employed technique scheme, testing electrical property structure recorded in the embodiment of the present application and preparation method thereof, testing electrical property technique, all can be applicable at interlayer dielectric layer and back-end process (Back End Of Line, be called for short BEOL) before, in the testing electrical property technique that gate oxide is carried out, namely by the gate oxide testing electrical property structure being formed with grid, prepare the miniature pad (mini-pad) be connected with gate oxide and substrate respectively, while greatly reducing measurement technology difficulty, can also under the prerequisite need not carrying out fragmentation (do not need broke thewafer) to wafer, realize carrying out testing electrical property to the gate oxide of nmos device and PMOS device, effectively to avoid to the damage that causes of test sample simultaneously, greatly enhance productivity, effective reduction testing cost.
By illustrating and accompanying drawing, giving the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.
For a person skilled in the art, after reading above-mentioned explanation, each middle change and correction undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (10)
1. a testing electrical property structure, is characterized in that, described structure comprises:
Substrate, is provided with gate regions, and is positioned at the first test section and second test section of these both sides, gate regions;
Gate oxide, covers the described substrate being positioned at described gate regions, and extends in described first test section of part;
Grid, covers on described gate oxide;
Wherein, the described grid extending to described first test section is defined as the first miniature pad, the described substrate that part is positioned at described second test section is defined as the second miniature pad, and utilizes described first miniature pad and described second miniature pad to carry out testing electrical property technique to described gate oxide.
2. testing electrical property structure as claimed in claim 1, it is characterized in that, be also provided with the first fleet plough groove isolation structure in described substrate, and this first fleet plough groove isolation structure is across described gate regions and described first test section;
Described first miniature pad is positioned on described first fleet plough groove isolation structure.
3. testing electrical property structure as claimed in claim 1, it is characterized in that, the second fleet plough groove isolation structure and the 3rd isolation structure is also provided with in described substrate, described second fleet plough groove isolation structure is arranged in described gate regions in the region closing on described second test section, and described 3rd fleet plough groove isolation structure is arranged in the substrate of described second test section away from the outside of side, described gate regions;
Wherein, described second miniature pad is arranged between described second fleet plough groove isolation structure and described 3rd fleet plough groove isolation structure.
4. testing electrical property structure as claimed in claim 1, is characterized in that, described first miniature pad and described second miniature pad are all greater than 10um × 10um for the length and width size on the surface tested.
5. testing electrical property structure as claimed in claim 4, is characterized in that, described first miniature pad and described second miniature pad are (20 ~ 30um) × (20 ~ 30um) for the length and width size on the surface tested.
6. testing electrical property structure as claimed in claim 1, it is characterized in that, described first miniature pad is less than 30% of described gate upper surface area for the area on the surface tested.
7. prepare a method for testing electrical property structure, it is characterized in that, for the preparation of the testing electrical property structure in the claims 1 ~ 6 described in any one, described method comprises:
There is provided the substrate that is provided with gate regions, the first test section and the second test section, and described first test section and the second test section lay respectively at the both sides of described gate regions;
On the gate regions of described substrate, prepare gate oxide and grid successively, and this gate oxide and described grid all extend in described first test section;
The described grid that definition is positioned at described first test section is the first miniature pad, and the section substrate that definition is positioned at described second test section is the second miniature pad;
Described first miniature pad and described second miniature pad is utilized to carry out testing electrical property technique to described gate oxide.
8. prepare the method for testing electrical property structure as claimed in claim 7, it is characterized in that, in described substrate, be also provided with the first fleet plough groove isolation structure, and this first fleet plough groove isolation structure is across described gate regions and described first test section;
Described first miniature pad is positioned on described first fleet plough groove isolation structure.
9. prepare the method for testing electrical property structure as claimed in claim 8, it is characterized in that, the second fleet plough groove isolation structure and the 3rd isolation structure is also provided with in described substrate, described second fleet plough groove isolation structure is arranged in described gate regions in the region closing on described second test section, and described 3rd fleet plough groove isolation structure is arranged in the substrate of described second test section away from the outside of side, described gate regions;
Wherein, described second miniature pad is arranged between described second fleet plough groove isolation structure and described 3rd fleet plough groove isolation structure.
10. a testing electrical property technique, is characterized in that, described technique comprises:
Testing electrical property structure described in any one in one the claims 1 ~ 6 is provided;
Two probes are utilized to be electrically connected with described first miniature pad and described second miniature pad, to carry out testing electrical property technique to described gate oxide respectively.
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| CN201510003666.7A CN104538382A (en) | 2015-01-05 | 2015-01-05 | Electrical performance test structure and manufacturing method and electrical performance testing process thereof |
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| US6472233B1 (en) * | 1999-08-02 | 2002-10-29 | Advanced Micro Devices, Inc. | MOSFET test structure for capacitance-voltage measurements |
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| CN101281898A (en) * | 2007-04-03 | 2008-10-08 | 中芯国际集成电路制造(上海)有限公司 | Structure for testing integrality of grid medium layer, forming method and test method thereof |
| KR20090033615A (en) * | 2007-10-01 | 2009-04-06 | 주식회사 동부하이텍 | Method for forming test pattern of gate ox integrity and test pattern structure for the gate ox integrity |
| CN102097413A (en) * | 2009-12-15 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Structure and method for testing integrity of grid oxide layer and dielectric layer |
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2015
- 2015-01-05 CN CN201510003666.7A patent/CN104538382A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6472233B1 (en) * | 1999-08-02 | 2002-10-29 | Advanced Micro Devices, Inc. | MOSFET test structure for capacitance-voltage measurements |
| CN101197348A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Multi-use polysilicon edge test structure |
| CN101281898A (en) * | 2007-04-03 | 2008-10-08 | 中芯国际集成电路制造(上海)有限公司 | Structure for testing integrality of grid medium layer, forming method and test method thereof |
| KR20090033615A (en) * | 2007-10-01 | 2009-04-06 | 주식회사 동부하이텍 | Method for forming test pattern of gate ox integrity and test pattern structure for the gate ox integrity |
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