CN102089974B - 用于优化电路中的频率性能的输入/输出模块的装置和方法 - Google Patents

用于优化电路中的频率性能的输入/输出模块的装置和方法 Download PDF

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Publication number
CN102089974B
CN102089974B CN200980127282.9A CN200980127282A CN102089974B CN 102089974 B CN102089974 B CN 102089974B CN 200980127282 A CN200980127282 A CN 200980127282A CN 102089974 B CN102089974 B CN 102089974B
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CN
China
Prior art keywords
pads
integrated circuit
signal
circuit die
voltage
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CN200980127282.9A
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English (en)
Chinese (zh)
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CN102089974A (zh
Inventor
林谷
Y-F·林
S·特兰
P·克霍斯库
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Altera Corp
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Altera Corp
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Publication date
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Publication of CN102089974A publication Critical patent/CN102089974A/zh
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/641—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
CN200980127282.9A 2008-07-13 2009-07-07 用于优化电路中的频率性能的输入/输出模块的装置和方法 Active CN102089974B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/172,247 US8138787B2 (en) 2008-07-13 2008-07-13 Apparatus and method for input/output module that optimizes frequency performance in a circuit
US12/172,247 2008-07-13
PCT/US2009/049822 WO2010008971A2 (en) 2008-07-13 2009-07-07 Apparatus and method for input/output module that optimizes frequency performance in a circuit

Publications (2)

Publication Number Publication Date
CN102089974A CN102089974A (zh) 2011-06-08
CN102089974B true CN102089974B (zh) 2015-08-12

Family

ID=41504357

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200980127282.9A Active CN102089974B (zh) 2008-07-13 2009-07-07 用于优化电路中的频率性能的输入/输出模块的装置和方法

Country Status (5)

Country Link
US (1) US8138787B2 (https=)
EP (1) EP2311190A4 (https=)
JP (1) JP5566381B2 (https=)
CN (1) CN102089974B (https=)
WO (1) WO2010008971A2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB201205427D0 (en) * 2012-03-28 2012-05-09 Yota Devices Ipr Ltd Display device and connector
KR20150026644A (ko) * 2013-09-03 2015-03-11 에스케이하이닉스 주식회사 반도체칩, 반도체칩 패키지 및 이를 포함하는 반도체시스템
US9503155B2 (en) * 2015-04-09 2016-11-22 Nxp B.V. Tuning asymmetry of a differential digital interface to cancel magnetic coupling
KR102777475B1 (ko) 2019-10-17 2025-03-10 에스케이하이닉스 주식회사 반도체 패키지

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1111824A (zh) * 1993-12-21 1995-11-15 株式会社东芝 半导体集成电路装置
US20030214344A1 (en) * 2002-05-20 2003-11-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor circuit device adaptable to plurality of types of packages
CN1819196A (zh) * 2005-01-27 2006-08-16 株式会社瑞萨科技 具有集中地配置了缓冲器或保护电路的布局的半导体集成电路
CN1832165A (zh) * 2004-12-10 2006-09-13 因芬尼昂技术股份公司 双列存储器模块的堆叠式dram存储器芯片

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WO1992011701A2 (en) * 1990-12-18 1992-07-09 Vlsi Technology Inc. Reduction of noise on power and ground inputs to an integrated circuit
US5406607A (en) * 1994-02-24 1995-04-11 Convex Computer Corporation Apparatus, systems and methods for addressing electronic memories
US5604710A (en) 1994-05-20 1997-02-18 Mitsubishi Denki Kabushiki Kaisha Arrangement of power supply and data input/output pads in semiconductor memory device
US5847936A (en) 1997-06-20 1998-12-08 Sun Microsystems, Inc. Optimized routing scheme for an integrated circuit/printed circuit board
JP3535797B2 (ja) * 2000-03-10 2004-06-07 日本電信電話株式会社 モノリシック集積回路の製造方法
US6603199B1 (en) 2000-11-28 2003-08-05 National Semiconductor Corporation Integrated circuit package having die with staggered bond pads and die pad assignment methodology for assembly of staggered die in single-tier ebga packages
US6591410B1 (en) 2000-12-28 2003-07-08 Lsi Logic Corporation Six-to-one signal/power ratio bump and trace pattern for flip chip design
JP3929289B2 (ja) * 2001-11-12 2007-06-13 株式会社ルネサステクノロジ 半導体装置
JP2003229448A (ja) * 2002-01-31 2003-08-15 Kinseki Ltd 半導体素子の電極構造とそれを用いた圧電発振器
US6972464B2 (en) 2002-10-08 2005-12-06 Great Wall Semiconductor Corporation Power MOSFET
TWI265600B (en) 2002-11-18 2006-11-01 Hynix Semiconductor Inc Semiconductor device and method for fabricating the same
US6998719B2 (en) 2003-07-30 2006-02-14 Telairity Semiconductor, Inc. Power grid layout techniques on integrated circuits
US7091614B2 (en) 2004-11-05 2006-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit design for routing an electrical connection
US7405473B1 (en) 2005-11-23 2008-07-29 Altera Corporation Techniques for optimizing electrical performance and layout efficiency in connectors with via placement and routing
WO2008130299A1 (en) * 2007-04-20 2008-10-30 Telefonaktiebolaget L M Ericsson (Publ) A printed board assembly and a method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1111824A (zh) * 1993-12-21 1995-11-15 株式会社东芝 半导体集成电路装置
US20030214344A1 (en) * 2002-05-20 2003-11-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor circuit device adaptable to plurality of types of packages
CN1832165A (zh) * 2004-12-10 2006-09-13 因芬尼昂技术股份公司 双列存储器模块的堆叠式dram存储器芯片
CN1819196A (zh) * 2005-01-27 2006-08-16 株式会社瑞萨科技 具有集中地配置了缓冲器或保护电路的布局的半导体集成电路

Also Published As

Publication number Publication date
JP5566381B2 (ja) 2014-08-06
WO2010008971A2 (en) 2010-01-21
JP2011528196A (ja) 2011-11-10
EP2311190A4 (en) 2011-09-21
CN102089974A (zh) 2011-06-08
WO2010008971A3 (en) 2010-04-22
US20100006904A1 (en) 2010-01-14
US8138787B2 (en) 2012-03-20
EP2311190A2 (en) 2011-04-20

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