CN102088021A - 具有肖特基二极管的沟槽mos装置及其制造方法 - Google Patents

具有肖特基二极管的沟槽mos装置及其制造方法 Download PDF

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CN102088021A
CN102088021A CN2010101402850A CN201010140285A CN102088021A CN 102088021 A CN102088021 A CN 102088021A CN 2010101402850 A CN2010101402850 A CN 2010101402850A CN 201010140285 A CN201010140285 A CN 201010140285A CN 102088021 A CN102088021 A CN 102088021A
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庄乔舜
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Abstract

在一个实施例中，本发明包括半导体装置。所述半导体装置包含第一半导体区、第二半导体区及沟槽区。所述第一半导体区具有第一导电率类型及第一导电率浓度。所述沟槽区包括与所述第一半导体区接触的金属层以形成金属-半导体结。所述第二半导体区邻近于所述第一半导体区且具有第二导电率类型及第二导电率浓度。所述第二半导体区与所述第一半导体区形成PN结，且所述沟槽区具有一深度使得所述金属-半导体结靠近于所述PN结。

Description

具有肖特基二极管的沟槽MOS装置及其制造方法
技术领域
本发明涉及沟槽金属氧化物半导体(MOS)装置，且特定来说涉及具有肖特基二极管的沟槽MOS装置及制造所述沟槽MOS装置的方法。
背景技术
除非本文另有指示，本章节中所描述的方法对于本申请案中的权利要求书来说并非现有技术，且即使包括在本章节中也不表示就是现有技术。
沟槽MOS装置通常用作功率集成电路中的晶体管。沟槽MOS装置可与常规PN二极管并联制造，以便在正向偏置时减小所述装置的接通电压。MOS晶体管的阈值可经设计而远远小于典型PN结的0.6V的接通电压。接通电压的减小转化为任何给定电流的较小电压降，且因此转化为所述装置的总功率节省。
在整流器应用中，沟槽MOS装置通常可具有慢的切换响应时间，使得在沟槽MOS装置响应并减小正向电压之前的一部分时间内所述PN结可在0.6V下完全偏置。所述切换的频率越高，此特性可越显著且可浪费越多的功率。
因此，需要改善的沟槽MOS装置。本发明通过提供具有肖特基二极管的沟槽MOS装置及用于制造所述沟槽MOS装置的方法解决这些及其它问题。
发明内容
在一个实施例中，本发明包括半导体装置。所述半导体装置包含第一半导体区、第二半导体区及沟槽区。所述第一半导体区具有第一导电率类型及第一导电率浓度。所述沟槽区包括与所述第一半导体区接触的金属层以形成金属-半导体结。所述第二半导体区邻近于所述第一半导体区且具有第二导电率类型及第二导电率浓度。所述第二半导体区与所述第一半导体区形成PN结，且所述沟槽区具有一深度使得所述金属-半导体结靠近于所述PN结。
以下详细说明及附图提供对本发明的性质及优点的更好理解。
附图说明
图1图解说明根据本发明的一个实施例的半导体装置。
图2A到2C图解说明根据本发明的一个实施例的用于制造半导体装置的方法。
图3图解说明根据本发明的一个实施例的具有多个沟槽MOS装置及肖特基二极管的半导体装置的截面。
具体实施方式
本文描述的是用于具有肖特基二极管的沟槽MOS装置的技术及用于制造所述沟槽MOS装置的方法。出于解释的目的，以下说明中陈述了众多实例及具体细节，以便提供对本发明的透彻理解。然而，所属领域的技术人员将明了，由权利要求书界定的本发明可包括这些实例中的一些或所有特征自身或与以下所描述的其它特征的组合，且可进一步包括本文所描述的特征及概念的修改及等效内容。
图1图解说明根据本发明的一个实施例的半导体装置100。半导体装置100可用作整流器，从而在正向偏置状态中使电流通过且在反向偏置状态中阻挡电流。半导体装置100包括集成在沟槽MOS装置102与沟槽MOS装置103之间的沟槽129。沟槽129可填充有金属以在所述沟槽的底部处形成肖特基二极管101，如以下更详细描述。沟槽MOS装置102及103在正向偏置状态中提供减小的接通电压，且肖特基二极管101在向正向偏置状态的转换期间提供减小的接通电压。通过维持低接通电压可在正向偏置状态及向所述正向偏置状态的转换两者中节约功率。
沟槽MOS装置102在正向偏置稳定状态中使电流通过。P+半导体区109可具有比P-半导体区111大的浓度，且因此可建立与金属层128的更好接触。金属层128可耦合到半导体装置100的阳极端子。当正向偏置时，电流可从P+半导体区109流到P-半导体区111。PN结131可被正向偏置且电流可从P-半导体区111流到n-epi区115。衬底116可接收此电流且可耦合到半导体装置100的阴极端子。P-延伸区113可修改PN结131的位置。
沟槽MOS装置102经配置以提供接通电压的减小。PN结131可具有0.6V的接通电压，所述电压可由与所述结并联定位的低阈值MOS装置减小。沟槽MOS装置102包括N+区106、P-区109及111、n-epi区115、栅极134。栅极134可包括导电材料，例如多晶硅。当经偏置而大于所述阈值时，栅极134可在P-区111内形成反转层。此反转层可沿栅极134的侧部分定位，超出电介质层114。此反转层可在小于0.2V的低阈值下起始且可提供接通电压的减小。
沟槽MOS装置103与沟槽MOS装置102类似地操作。沟槽MOS装置103包括栅极135、N+半导体区118、层间电介质(ILD)120、P+半导体区121、P-半导体区123、P-延伸区125、栅极氧化物层127、n-epi区115、n+衬底116及金属层128，其对应于沟槽MOS装置102的栅极134、N+半导体区106、层间电介质(ILD)107、P+半导体区109、P-半导体区111、P-延伸区113、栅极氧化物层114、n-epi区115、n+衬底116及金属层128。
肖特基二极管101提供具有低阈值的快速切换二极管，其可在转换期间减小接通电压。半导体装置100可切换为整流器且与所述PN结并联的低阈值MOS装置可不足够快速地响应。肖特基二极管101的接通电压可以是十分之几伏且可具有快速响应时间。肖特基二极管101形成于n-epi区115与金属层128之间的金属-半导体结之间。肖特基二极管101的位置可有助于在转换期间减小半导体装置100的接通电压。
肖特基二极管101的宽度139可由P-延伸区113及125调整。P-延伸113及125变得越宽，肖特基二极管101的宽度139越小。可减小宽度139以改善反向泄露。宽度139的减小也可增加肖特基二极管101的接通电压特性。
沟槽区129具有深度136，其与PN结131及132靠近地放置肖特基二极管101。PN结131从与沟槽104的下部侧的交点向与沟槽129的交点向上弯曲。P-延伸113调整PN结131与沟槽129的交点的放置且P-半导体区111界定PN结131与沟槽104及129的交点。P-半导体区111的宽度以及深度136可影响电流流动及肖特基101在转换期间可减小接通电压的速度。
半导体装置100还可包括额外沟槽MOS装置140到141。沟槽MOS装置140及141可分别形成为沟槽MOS装置102及103的补充结构且以类似方式起作用。沟槽MOS装置140包括栅极134、N+半导体区105、层间电介质(ILD)107、P+半导体区108、P-半导体区110、P-延伸区112、栅极氧化物层114、n-epi区115、n+衬底116及金属层128，其对应于沟槽MOS装置102的栅极134、N+半导体区106、层间电介质(ILD)107、P+半导体区109、P-半导体区111、P-延伸区113、栅极氧化物层114、n-epi区115、n+衬底116及金属层128。P-延伸112还可贡献于肖特基二极管137的宽度。PN结130可靠近于肖特基二极管137。
沟槽MOS装置141包括栅极135、N+半导体区119、层间电介质(ILD)120、P+半导体区122、P-半导体区124、P-延伸区126、栅极氧化物层127、n-epi区115、n+衬底116及金属层128，其对应于沟槽MOS装置103的栅极135、N+半导体区118、层间电介质(ILD)120、P+半导体区121、P-半导体区123、P-延伸区125、栅极氧化物层127、n-epi区115、n+衬底116及金属层128。P-延伸126可贡献于肖特基二极管138的宽度。PN结133可靠近于肖特基二极管138。
图2A到2C图解说明根据本发明的一个实施例的用于制造沟槽MOS装置的方法200。
在201处，可在驻留于n-型衬底区215顶上的n-epi区214的表面上沉积掩模氧化物210。可使用化学气相沉积(CVD)工艺来沉积掩模氧化物210。使用沟槽光(trenchphoto)来在掩模氧化物210中制作开口211。可以两个步骤植入P型材料212到213，首先通过提供高能量植入212，随后是较低能量植入213。在202处，可驱动P-本体以在n-epi区214内形成P-半导体区216及217。
在203处，可将沟槽218及219蚀刻到P-半导体区216及217中比P区216/217的深度深的深度。沟槽218将P-半导体区216分裂为区216a及216b。沟槽219将P-半导体区217分裂为区217a及217b。已移除掩模氧化物210且可添加栅极氧化物220。在204处，可添加多晶硅且然后对其进行回蚀刻以形成栅极220及221。在205处，可使用源光掩模222来提供源植入。在驱入所述源植入之后，可产生N+半导体区223到226。
在206处，可使用CVD工艺来提供ILD区227及228。另外，可使用接触光(contactphoto)来蚀刻穿过所述ILD。可通过添加P+植入且驱入所述植入来形成P+半导体区229到231。
在207处，蚀刻沟槽232到234。沟槽233具有深度d及宽度w。沟槽232及234也可具有类似深度及宽度。所述蚀刻可比P+区229到231深且切割穿过P+区229到231。此可产生P+区229b、230a、230b及231a。在208处，可添加P-材料的植入，以形成P-延伸区235到238。在209处，添加金属层239且在位置240到242处形成金属-半导体结。
图3图解说明根据本发明的一个实施例的使用多个沟槽MOS装置(例如，MOS装置305到312)的半导体装置300的截面。半导体装置300包括二极管301到304。二极管301包括集成于沟槽313内且位于沟槽MOS装置305与306之间的肖特基二极管317。二极管302包括集成于沟槽314内且位于沟槽MOS装置307与308之间的肖特基二极管318。二极管303包括集成于沟槽315内且位于沟槽MOS装置309与310之间的肖特基二极管319。二极管304包括集成于沟槽316内且位于沟槽MOS装置311与312之间的肖特基二极管320。半导体装置300使用多个沟槽来将多个肖特基二极管(例如，肖特基二极管317到320)及MOS装置(例如，沟槽MOS装置305到312)与多个PN结并联放置，以便在正向偏置状态中及在向所述正向偏置状态的转换期间减小二极管301到304的接通电压。通过维持低接通电压可在正向偏置状态及向所述正向偏置状态的转换两者中节约功率。
以上说明图解说明本发明的各种实施例连同可如何实施本发明的各方面的实例。以上实例及实施例不应被认为是仅有的实施例，且呈现所述实例及实施例旨在图解说明由以上权利要求书界定的本发明的灵活性及优点。基于以上揭示内容及以上权利要求书，其它布置、实施例、实施方案及等效内容对于所属领域的技术人员将是显而易见的且可在不背离由权利要求书界定的本发明的精神及范围的前提下使用。

Claims (13)

1.一种半导体装置，其包含：
第一半导体区，其具有第一导电率类型及第一导电率浓度；
第一沟槽，其包括与所述第一半导体区接触的金属层以形成金属-半导体结；及
第二半导体区，其邻近于所述第一半导体区及所述金属-半导体结，所述第二半导体区具有第二导电率类型及第二导电率浓度，
其中所述第二半导体区与所述第一半导体区形成PN结。
2.根据权利要求1所述的半导体装置，其进一步包含第二沟槽及所述第二沟槽内的导电材料，
其中所述第二半导体区在所述第一沟槽与所述第二沟槽之间。
3.根据权利要求2所述的半导体装置，其进一步包含所述导电材料与所述第二半导体区之间的电介质层，
其中所述导电材料及所述电介质层在所述沟槽内形成栅极，所述栅极在被偏置时在所述第二半导体层内形成反转层。
4.根据权利要求2所述的半导体装置，其中所述第二沟槽的深度比所述第一沟槽的深度大，且其中所述PN结从与所述第二沟槽的交点向与所述第一沟槽的交点向上弯曲。
5.根据权利要求3所述的半导体装置，其进一步包含所述第一半导体类型的第三半导体区，
其中所述第三半导体区邻近于所述第二半导体区及所述第一沟槽，且其中所述第一半导体区、所述第二半导体区、第三半导体区、所述电介质层及所述导电材料形成沟槽MOS装置。
6.根据权利要求1所述的半导体装置，其进一步包含所述第二半导体类型的第三半导体区，其邻近于所述第二半导体区及所述第一沟槽，
其中所述第三半导体区界定其中所述金属层与所述第一半导体区接触的宽度。
7.根据权利要求1所述的半导体装置，其进一步包含所述第二半导体类型及所述第二半导体浓度的第三半导体区，
其中所述第三半导体区与所述第一半导体区形成PN结，且
其中所述沟槽在所述第二半导体区与所述第三半导体区之间。
8.一种方法，其包含：
在第二导电率类型及第二导电率浓度的第二半导体区内形成第一导电率类型及第一导电率浓度的第一半导体区；
穿过所述第一半导体区蚀刻第一沟槽；及
在所述第一沟槽内添加金属层，使得所述金属层接触所述第二半导体区以形成金属-半导体结；
其中所述第一半导体区与所述第二半导体区形成PN结，且
其中所述第一沟槽具有一深度使得所述金属-半导体结邻近于所述PN结。
9.根据权利要求8所述的方法，其进一步包含：
蚀刻第二沟槽；及
在所述第二沟槽内添加导电材料，
其中所述第一半导体区在所述第一沟槽与所述第二沟槽区之间。
10.根据权利要求9所述的方法，其进一步包含：
在所述导电材料与所述第一半导体区之间添加电介质层，
其中所述导电材料及所述电介质层在所述沟槽内形成栅极，所述栅极在被偏置时在所述第一半导体区内形成反转层。
11.根据权利要求9所述的方法，其中所述第二沟槽的深度比所述第一沟槽的所述深度大，且其中所述形成所述第一半导体区包括形成弯曲边界，使得所述PN结从与所述第二沟槽的交点向与所述第一沟槽的交点向上弯曲。
12.根据权利要求8所述的方法，其进一步包含：
形成所述第二半导体类型的第三半导体区，
其中所述第三半导体区在所述第一半导体区上方且邻近于所述第一沟槽，且其中所述第三半导体浓度比所述第一半导体浓度大。
13.根据权利要求12所述的方法，其进一步包含：
邻近于所述第一半导体区及所述第一沟槽形成所述第一半导体类型的第四半导体区，以延伸所述PN结且减小所述金属-半导体结的宽度。
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