CN102088011B - 集成电路装置及其形成方法 - Google Patents

集成电路装置及其形成方法 Download PDF

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CN102088011B
CN102088011B CN2010102066433A CN201010206643A CN102088011B CN 102088011 B CN102088011 B CN 102088011B CN 2010102066433 A CN2010102066433 A CN 2010102066433A CN 201010206643 A CN201010206643 A CN 201010206643A CN 102088011 B CN102088011 B CN 102088011B
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interface
joins
layer
copper
crystal seed
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CN102088011A (zh
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林正忠
刘重希
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种集成电路装置及其形成方法。该集成电路装置包含：一第一铜层；一第二铜层设置于该第一铜层之上；以及，一相接界面介于该第一铜层及该第二铜层之间。该相接界面包含一平坦区域界面区及一交互成长界面区，其中该平坦区域界面区小于或等于该相接界面的50％。当平坦区域界面区占该相接界面总面积的50％或50％以下，该相接界面216(即铜-铜相接界面)即不会有剥离现象的发生。降低(或消除)膜层间的剥离现象可改善半导体装置的性能。

Description

集成电路装置及其形成方法
技术领域
本发明涉及一种集成电路装置，更特别涉及一种集成电路装置的相接界面。
背景技术
半导体集成电路(IC)工业近年来经历了快速成长。在集成电路演化的过程，功能密度(即每单位晶片区域的该互相连接装置的数量)逐渐增加，且几何尺寸(即可以使用一制造程序所得的最小的元件(或线))也逐渐减少。此按比例缩小的工艺提供了生产效率增加及降低伴生成本等好处。此外，该按比例缩小的工艺同样增加了集成电路制造及加工的复杂性。为了使以上所述的进步性实现，发展出新颖的集成电路制造及加工是必需的。
集成电路装置包含许多的材料层，每一材料层与另一材料层在一相接界面接触。该相接界面可以被施以不同的加工及制造步骤，且较佳是在集成电路装置的制造过程中仍维持该相接界面的完整性。举例来说，维持每一相接界面的完整性(即相接触的两膜层不会由任一者上剥离，而造成剥离的现象通常是由于界面具有空隙)以避免剥离是有需要的。在传统相接界面可以观察到，尤其是铜-铜相接界面(例如在两铜层间的相接界面)，易产生剥离，如此一来会降低整体集成电路装置的性能。因此，提供一相接界面结构，以用来解决界面剥离问题，是有必要的。
发明内容
本发明提供许多不同的实施例。一作为范例的集成电路装置可包含一第一铜层、一第二铜层设置于该第一铜层之上，及一相接界面介于该第一铜层及该第二铜层之间。该相接界面包含一平坦区域界面区及一交互成长界面区，其中该平坦区域界面区小于或等于该相接界面的50％。
另一作为范例的集成电路装置可包含一半导体基板，其包含一焊垫；一凸块结构位于该半导体基板上，并与该焊垫电性连结；及一铜晶种层设置于该基板的焊垫及该凸块结构之间。相接界面介于该凸块结构及该铜晶种层之间，其中没有氧化铜层设置于该相接界面处。
一可作为范例的集成电路装置的制造方式可包含：提供一具有一焊垫的基板；形成一铜晶种层于该焊垫之上；利用CF4/O2/N2等离子体进行一除渣工艺；移除一在除渣工艺中所形成于该铜晶种层之上的残留层；以及，在完成上述步骤后，形成一凸块结构于该铜晶种层之上。
当平坦区域界面区占该相接界面总面积的50％或50％以下，该相接界面216(即铜-铜相接界面)即不会有剥离现象的发生。降低(或消除)膜层间的剥离现象可改善半导体装置的性能。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合所附图式，作详细说明如下。
附图说明
图1A是显示本发明所述集成电路装置的一实施例的剖面图；
图1B是显示图1A所示的集成电路装置其两材料层的相接界面的放大剖面图；
图2A-图2B是显示发明所述集成电路装置的一实施例其两材料层的相接界面的剖面图；
图3A-图3B是显示发明所述集成电路装置的一实施例其两材料层的相接界面的剖面图。
并且，上述附图中的附图标记说明如下：
200～集成电路装置；
202～基板；
204～焊垫；
206～保护层；
208～扩散阻挡层；
210～衬底铜层(铜晶种层)；
212～沉积后铜层(铜柱、或凸块结构)；
214～区块；
216～相接界面；
216A～平坦区域界面区；以及
216B～交互成长界面区。
具体实施方式
本发明接下来将会提供许多不同的实施例以实施本发明中不同的特征。各特定实施例中的组成及设置将会在以下作描述以简化本发明。这些为实施例并非用于限定本发明。
本发明的公开提供许多不同的实施例或范例，由此实施本发明的不同特征(feature)。于后所公开特定的组成及排列范例用以简化本发明的说明。虽然本发明已以较佳实施例公开如上，然而其并非用以限定本发明。另外，本发明的公开在不同范例中重复使用了参考数值与字母。重复使用是基于简化及清晰的目的，并非用以限定不同的实施例或结构间的关系。此外，第一特征形成于第二特征之上，其中实施例包含有：第一特征与第二特征通过直接接触所形成，或者是第一特征及第二特征之间具有插入的额外特征，使得第一特征与第二特征不为直接接触。
此外，公开在各实施例中的参考数字以及字母是用以简洁地阐明本发明，并非限定实施例或者排列间的关系。
集成电路装置包含许多材料层，每一材料层与另一材料层在一相接界面接触。该相接界面可以被施以不同的加工及制造步骤，且较佳是在集成电路装置的制造过程中仍维持该相接界面的完整性。举例来说，维持每一相接界面的完整性(即相接触的两膜层不会由任一者上剥离，而造成剥离的现象通常是由于界面具有空隙)以避免剥离是有需要的。传统相接界面，尤其是铜-铜相接界面(例如在两铜层间的相接界面)(像是一铜晶种层及一铜层的相接界面(例如由电化学电镀工艺所得的铜层))易产生剥离，如此一来会降低整体集成电路装置的性能。
本发明定义出相接界面所应具有的条件以消除界面剥离，尤其是针对铜-铜相接界面。以下讨论的实施例是就一铜互连柱(即一凸块结构用以构装集成电路装置)及一衬底铜晶种层的铜-铜相接界面的条件进行描述。该实施例仅为一范例，且本领域普通技术人员当能知悉本发明所述的相接界面条件亦可施行于其他相接界面，尤其是铜-铜相接界面(常用于集成电路装置)。举例来说，该相接界面条件亦可应用在一铜互连结构。
请参照图1A，提供一具有各种材料层相接界面的集成电路装置200(或是称为半导体装置)。该材料层相接界面其中一者为一铜-铜相接界面(进一步描述如下)。在其他的集成电路装置200实施例中，该集成电路装置200亦可具有其他特征，而以下所述的该集成电路装置200的特征亦可被取代或是移除。
该集成电路装置200包含一基板202，该基板具有微电子单元形成于其上。该基板202为一含硅的半导体基板。或者，该基板202包含一元素的半导体，例如硅及/或锗晶体；一半导体化合物，像是碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、及/或锑化铟；一半导体合金，像是SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP；或是上述的组合。该合金半导体基板可为一具有渐差比例的SiGe，也就是Si及Ge的组成可由一特定比率(在同一膜层的一位置)至另一特定比率的组合(在同一膜层的另一位置)。该SiGe合金亦可形成于一硅基板之上。该SiGe基板可为一应变SiGe基板。此外，该半导体基板可为硅覆绝缘(SOI)基板。在某些范例中，该半导体基板可包含一掺杂的外延层。
该基板202可依设计需要(如此技术领域所知)包含各种的掺杂区域(例如，p型阱或n型阱)。该掺杂区域可掺杂p型掺质，例如：硼或BF2；n型掺质则可例如磷或砷、或是上述的组合。该掺杂区域可直接形成于该基板202之上，像是一p型阱结构、一p型阱结构、一双重阱结构、或使用一凸起结构。该基板202可进一步包含各种的有源区域，例如：设置有一N型金属氧化物半导体(NMOS)晶体管装置的区域、以及设置有一P型金属氧化物半导体(PMOS)晶体管装置的区域。
该基板202可进一步包含一复数隔离特征(未图示)，例如浅沟槽隔离(STI)特征或是硅局部氧化(LOCOS)特征。该隔离特征可定义及阻隔各种微电子单元(未图示)。在该基板202上的该各种微电子单元，举例来说，可包含晶体管(像是金属氧化物半导体场效应晶体管(MOSFET)、互补式金属氧化物半导体(CMOS)晶体管、双极性接面晶体管(BJT)、高压晶体管、高频晶体管、p-通道及/或n-通道场效应晶体管(PFETs/NFETs)等)；电阻；二极管；电容；电感器；熔断器；及其他合适的单元。各种不同的工艺可用被用于制造该等微电子单元，包含沉积、蚀刻、注入、微影工艺、退火、及/或其他合适的步骤。该微电子单元互相连结以形成该集成电路装置，例如一逻辑装置、存储装置(像是SRAM)、射频装置、输入/输出(I/O)装置、系统芯片(SoC)装置，其组合、及/或其他合适的装置。
该集成电路装置200可进一步包含一互连结构形成于该基板202之上。举例来说，该互连结构可包含内层介电(ILD)层、金属导线间介电(IMD)层、以及金属化层。在该互连结构的该ILD及/或IMD层可包含低介电常数(low-k)介电材料、未掺杂硅玻璃(USG)、氮化硅、氮氧化硅、其他合适的材料、及/或上述的组合。该低介电常数(low-k)介电材料的介电常数(k值)可约小于3.9、或是约小于2.8。在该互连结构的该金属化层可形成一金属线，其材质可例如铜、铜合金、及/或其他合适的材料。本领域普通技术人员可依据上述的教示在一基板202上实施该互连结构的工艺。
该基板202进一步包含一焊垫204。该焊垫204是一金属化层，其形成于一顶层内层介电层之上，可以为导电途径(conductive route)的一部分。该焊垫204可具有一露出的表面，该表面，如果需要的话，可被施以一平坦化工艺，例如一化学机械研磨(CMP)工艺。该焊垫204的材料可包含，但非限定，铜、铝、铜合金、银、金、镍、钨、移动传导材料、上述的合金、上述的叠层、其他合适的材料、及/或上述的组合。该焊垫204的剖面可具有任何合适的阶梯高度，以达到所需的结合性质。
一保护层206可被形成于该基板202之上，并被图形化以露出一部分的该焊垫204。该保护层206可由任何合适的材料所构成，举例来说，非有机材料(包含未掺杂硅玻璃(USG)、氮化硅、氮氧化硅、氧化硅、其他适合材料、及/或上述的组合。或者，该保护层206可为一聚合化层，例如环氧树脂、聚亚酰胺、苯并环丁烯(BCB)，聚苯并恶唑(PBO)、其他适合材料、及/或上述的组合。
一扩散阻挡层208及一晶种层210形成于该保护层206之上，并露出一部分的该焊垫204。亦可有其他膜层形成于该保护层之上。该扩散阻挡层208亦被称为一导电性粘着层。该扩散阻挡层208可由任何合适的材料所构成，举例来说，可为钛、氮化钛、钽、氮化钽、其他合适的阻挡材料、及/或上述的组合。该扩散阻挡层208可以任何合适的方式来加以形成，例如物理气相沉积或溅镀。
该晶种层210可以为任何合适的材料。在此实施例中，该晶种层210为一铜晶种层。该晶种层210亦可以为包含银、铬、镍、锡、金、及/或其他适合材料的铜合金。该晶种层210可以任何合适的方式来加以形成，例如物理气相沉积或溅镀。该晶种层210亦可被称为一第一铜层。
一凸块结构212形成于该基板202之上。如图1A所示，该凸块结构212形成于该焊垫204所露出的部分之上。在本实施例，该凸块结构212可为一互连柱。该凸块结构212可为一覆晶组合，用以提供所形成的倒装接合集成电路装置(即集成电路装置200)与另一基板(例如印刷电路板(PCB))的直接电性结合。该包含该扩散阻挡层208及晶种层210的凸块下金属(UBM)层可被视为该凸块结构的一部分，这是可被理解的。该凸块结构212可进一步包含一焊料层形成于该互连柱之上。该焊料层包含任何合适的材料，例如锡、锡银、锡-铅、锡金锌、锡锌、锡铋-铟、锡-铟、锡-金、锡铅、锡铜、锡锌铟、及/或锡银锑。
该凸块结构212包含任何合适的材料。在此实施例中，该互连柱为一金属柱，其由一具有焊料可湿性(solder wettability)的导电材料所构成。举例来说，该凸块结构212的材质可为铜，或是被称为铜柱、铜凸块、及/或铜块。该铜柱亦被称为一镀铜层及/或第二铜层。该铜柱以任何合适的方式来加以形成，例如一电化学电镀(ECP)工艺。
该集成电路装置200包含各种介于不同膜层的接合界面。举例来说，集成电路装置200包含一基板202/焊垫204接合界面、一基板202/保护层206接合界面、一焊垫204/保护层206接合界面、一焊垫204/扩散阻挡层208接合界面、一保护层206/扩散阻挡层208接合界面、一扩散阻挡层208/晶种层210接合界面、及一晶种层210/凸块结构212接合界面。在整个集成电路装置200的制造过程中，该接合界面的完整性必需被维持，以使装置的性能不会因为接合界面的因素(例如剥离)而降低。
该集成电路装置200被指出的区块214被用以突显介于该晶种层210及该凸块结构212的相接界面216(该晶种层210/凸块结构212的相接界面216)。更具体地说，在此实施例中，该集成电路装置200的区块214用以指出介于铜晶种层210及电化学电镀(ECP)铜柱/铜层(或凸块结构)212的相接界面(或者称为一第一铜层及一第二铜层的相接界面)。图1B为该区块214的放大示意图，用以突显介于两材料层的接界面216。该铜晶种层210及电化学电镀(ECP)铜柱/铜层(或凸块结构)212在数个地方相接触。
如上所述，在相接界面(尤其是铜-铜相接界面)，可观察到，会有剥离的现象产生，如此一来会降低装置的性能。基于上述，本发明提供一接合界面的最佳化条件，以避免在接合界面216产生剥离现象。此外，值得注意是所描述的介于铜晶种层210及电化学电镀(ECP)铜柱/铜层(或凸块结构)212的接合界面216仅为举例，并非企图用来限制本发明。本发明所述的相接界面接件可应用于其他相接界面，尤其是铜-铜相接界面。
请参照图2A及图2B，绘示介于铜晶种层210及电化学电镀(ECP)铜柱/铜层(或凸块结构)212(一沉积后铜层)的接合界面216的各种状态。图2A绘示介于一衬底铜层及一沉积后铜层间的一平坦区域界面，该平坦区域界面是指在第一铜层210与该第二铜层212间实质上没有交互成长发生，因此很容易界定出该第一铜层210与该第二铜层212。传统相接界面显示上述的性质。图2B绘示介于一衬底铜层及一沉积后铜层间的一交互成长界面区，该交互成长界面区指在第一铜层210与该第二铜层212间进行了实质的交互成长，因此不容易清楚界定出该第一铜层210及该第二铜层212。
本发明欲得到的相接界面216为包含平坦区域界面区及交互成长界面区的结合。更具体地说，在该相接界面216中，平坦区域界面区占该相接界面总面积的50％以下(小于50％)，以降低剥离现象的发生(及实质消除剥离现象)。当该平坦区域界面区占该相接界面总面积的50％以上时，该相接界面仍会发生剥离。该交互成长界面区指构成该相接界面的两膜层互相缠结，或是经晶粒间交互成长。该交互成长界面区可通过各种工艺来达成，举例来说，任何适合的退火或清洗工艺。
值得注意的是，在集成电路装置200的制造过程中，在将该电化学电镀(ECP)铜柱/铜层(或凸块结构)212沉积于该铜晶种层210(衬底铜层)上之前，一清洗(即等离子体除渣处理)工艺常被用来移除该铜晶种层210表面上的残留物。该除渣工艺可以利用一CF4/02/N2等离子体来达成。然而，在进行该除渣工艺后，一残留层，例如氧化铜及/或氟化铜层，可能会形成于该铜晶种层210之上。基于上述，当将该电化学电镀(ECP)铜柱/铜层(或凸块结构)212沉积于该铜晶种层210之上时，该残留层(氧化铜及/或氟化铜层)会位于该两铜层210及212间，避免(或阻碍)该两铜层210及212进行交互成长。于是，在该两铜层间的接互界面易有剥离现象发生。这是由于氧化铜及/或氟化铜层的存在会使平坦区域界面区占该相接界面的总面积的50％以上，导致剥离现象发生。因此，为得到具有较少平坦区域界面区的相接界面(尤其是指平坦区域界面区占该相接界面总面积的50％以下)，必需不能有氧化铜及/或氟化铜层存在于该相接界面。任何适合的工艺可被用来移除该氧化铜及/或氟化铜层。当该相接界面不存在有氧化铜及/或氟化铜层时，会促进该两铜层彼此间的晶粒间交互成长，得到较大面积的交互成长界面区。
请参照图3A及图3B，绘示符合本发明一实施例所述具有小于50％的平坦区域界面区的相接界面216(介于铜晶种层210(衬底铜层)及电化学电镀(ECP)铜柱/铜层(或凸块结构)212(沉积后铜层)间)。由图3A及图3B可知，该相接界面216具有平坦区域界面区216A及交互成长界面区216B。该平坦区域界面指在衬底铜层210与该沉积后铜层212间实质上没有交互成长发生，因此很容易界定出该衬底铜层210与该沉积后铜层212。该交互成长界面区指在该衬底铜层210与该沉积后铜层212间进行了实质的交互成长，因此不容易清楚界定出该第一铜层210及该第二铜层212。在图3A及图3B中，该相接界面216具有一长度，其中该平坦区域界面区所具有的长度小于或等于该相接界面长度的50％。图3A显示该相接界面216所具有的平坦区域界面区216A约占该相接界面216的50％；图3B显示该相接界面所具有的平坦区域界面区216A约占该相接界面216的50％以下，即约为该相接界面216总面积的46.6％。当平坦区域界面区占该相接界面总面积的50％或50％以下，该相接界面216(即铜-铜相接界面)即不会有剥离现象的发生。降低(或消除)膜层间的剥离现象可改善半导体装置的性能。可以理解的，不同的实施例具有不同的优点，然而没有特定的优点在任何实施例中是必然要求的。
虽然本发明已以数个较佳实施例公开如上，然而其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的范围为准。

Claims (11)

1.一种集成电路装置，包含：
一第一铜层；
一第二铜层设置于该第一铜层之上；
一相接界面介于该第一铜层及该第二铜层之间，其中该相接界面包含一平坦区域界面区及一交互成长界面区；以及
其中该平坦区域界面区小于或等于该相接界面的50％；
其中该平坦区域界面区包含一部分的相接界面，其中该一部分的相接界面为该第一铜层与该第二铜层相接触之处，且显示出实质上没有交互成长发生。
2.如权利要求1所述的集成电路装置，其中该交互成长界面区包含一部分的相接界面，其中该一部分的相接界面为该第一铜层与该第二铜层相接触之处，且显示出晶粒间交互成长。
3.如权利要求1所述的集成电路装置，其中没有氧化铜层设置于该相接界面处。
4.如权利要求1所述的集成电路装置，其中没有氟化铜层设置于该相接界面处。
5.一种集成电路装置，包含：
一半导体基板包含一焊垫；
一凸块结构位于于该半导体基板上，并与该焊垫电性连结；
一铜晶种层，设置于该基板的焊垫及该凸块结构之间；以及
一相接界面介于该凸块结构及该铜晶种层之间，其中没有氧化铜层设置于该相接界面处；其中，该相接界面包含一平坦区域界面区及一交互成长界面区，且该平坦区域界面区小于或等于该相接界面的50％，其中，该平坦区域界面区包含一部分的相接界面，其中该一部分的相接界面为该凸块结构与该铜晶种层相接触之处，且显示出实质上没有交互成长发生；并且，该交互成长界面区包含一部分的相接界面，其中该一部分的相接界面为该凸块结构与部分该铜晶种层交互成长处。
6.如权利要求5所述的集成电路装置，其中没有氟化铜层位于该相接界面处。
7.一种形成集成电路装置的方法，包含：
提供一具有一焊垫的基板；
形成一铜晶种层于该焊垫之上；
利用CF4/O2/N2等离子体进行一除渣工艺；
移除一在除渣工艺中所形成于该铜晶种层之上的残留层；以及
之后，形成一凸块结构于该铜晶种层之上，其中，一介于该凸块结构及该铜晶种层的相接界面包含一平坦区域界面区及一交互成长界面区，且该平坦区域界面区小于或等于该相接界面的50％，且显示出实质上没有交互成长发生。
8.如权利要求7所述的形成集成电路装置的方法，其中没有氧化铜层设置一介于该凸块结构及该铜晶种层的相接界面。
9.如权利要求7所述的形成集成电路装置的方法，其中没有氟化铜层设置一介于该凸块结构及该铜晶种层的相接界面。
10.如权利要求7所述的形成集成电路装置的方法，其中形成该凸块结构于该铜晶种层之上的步骤包含形成一铜柱于该铜晶种层之上。
11.如权利要求7所述的形成集成电路装置的方法，其中形成该凸块结构于该铜晶种层之上的步骤包含：
形成一铜柱于该铜晶种层之上；以及
形成一焊料层于该铜柱之上。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8493746B2 (en) 2009-02-12 2013-07-23 International Business Machines Corporation Additives for grain fragmentation in Pb-free Sn-based solder
US8128868B2 (en) * 2009-02-12 2012-03-06 International Business Machines Corporation Grain refinement by precipitate formation in PB-free alloys of tin
US8344506B2 (en) 2009-12-08 2013-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Interface structure for copper-copper peeling integrity
US9576933B1 (en) * 2016-01-06 2017-02-21 Inotera Memories, Inc. Fan-out wafer level packaging and manufacturing method thereof
TWI657721B (zh) 2018-04-02 2019-04-21 欣興電子股份有限公司 線路板、封裝結構及其製造方法
US11024593B2 (en) * 2018-09-28 2021-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Metal bumps and method forming same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6180505B1 (en) * 1999-01-07 2001-01-30 International Business Machines Corporation Process for forming a copper-containing film
US6333120B1 (en) * 1999-10-27 2001-12-25 International Business Machines Corporation Method for controlling the texture and microstructure of plated copper and plated structure
CN1647260A (zh) * 2001-02-09 2005-07-27 国际商业机器公司 用于输入/输出位置的共用球型限制冶金
TWI247369B (en) * 2000-08-11 2006-01-11 Taiwan Semiconductor Mfg Forming method of conductive bump

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6123825A (en) * 1998-12-02 2000-09-26 International Business Machines Corporation Electromigration-resistant copper microstructure and process of making
US6649507B1 (en) 2001-06-18 2003-11-18 Taiwan Semiconductor Manufacturing Company Dual layer photoresist method for fabricating a mushroom bumping plating structure
US20030116845A1 (en) * 2001-12-21 2003-06-26 Bojkov Christo P. Waferlevel method for direct bumping on copper pads in integrated circuits
US8344506B2 (en) 2009-12-08 2013-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Interface structure for copper-copper peeling integrity

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6180505B1 (en) * 1999-01-07 2001-01-30 International Business Machines Corporation Process for forming a copper-containing film
US6333120B1 (en) * 1999-10-27 2001-12-25 International Business Machines Corporation Method for controlling the texture and microstructure of plated copper and plated structure
TWI247369B (en) * 2000-08-11 2006-01-11 Taiwan Semiconductor Mfg Forming method of conductive bump
CN1647260A (zh) * 2001-02-09 2005-07-27 国际商业机器公司 用于输入/输出位置的共用球型限制冶金

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