CN105957843A - 导电通孔结构 - Google Patents

导电通孔结构 Download PDF

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Publication number
CN105957843A
CN105957843A CN201610405842.4A CN201610405842A CN105957843A CN 105957843 A CN105957843 A CN 105957843A CN 201610405842 A CN201610405842 A CN 201610405842A CN 105957843 A CN105957843 A CN 105957843A
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CN
China
Prior art keywords
conductive
hole
layer
contact pad
opening
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Pending
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CN201610405842.4A
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English (en)
Inventor
张国钦
谢玉宸
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN105957843A publication Critical patent/CN105957843A/zh
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Abstract

本发明涉及半导体器件的凸块结构。半导体器件的示例性结构包括衬底；位于该衬底上方的接触焊盘；在该衬底上方延伸并在该接触焊盘上方具有开口的钝化层，该开口具有第一宽度；在该开口内的导电通孔；和具有完全覆盖导电通孔的第二宽度的导电柱，其中第一宽度与第二宽度的比值是约0.15至0.55。本发明还提供了一种导电通孔结构。

Description

导电通孔结构
本申请是2011年10月19日提交的优先权日为2011年5月26日的申请号为201110324369.4的名称为“导电通孔结构”的发明专利申请的分案申请。
技术领域
本发明涉及集成电路制造，更具体而言，涉及具有导电通孔的半导体器件。
背景技术
现代集成电路(IC)确实是由数百万个有源器件(诸如二极管和晶体管)和无源器件(诸如电感器、电容器和电阻器)组成。这些器件最初彼此隔离，但是后来互相连接在一起形成功能电路。典型的互连结构包括横向互连(诸如金属线(线路系统))和纵向互连(诸如通孔和接触件)。互连对于现代IC的性能极限和密度的影响越来越大。在互连结构的顶部，在互连结构上形成接触焊盘，并使其暴露在相应芯片的顶表面以备IC封装。通过接触焊盘进行电连接以将芯片连接至封装基板或另一管芯。接触焊盘可以用于IC封装期间的引线接合或倒装芯片接合。
倒装芯片运用凸块来建立芯片的接触焊盘和封装基板之间的电接触。在结构上，凸块实际上包含凸块自身和位于凸块和接触焊盘之间的所谓凸块底部金属化(UBM)层。UBM层一般包含在接触焊盘上以该顺序布置的扩散阻挡层(或粘合层)和种子层。基于所用的材料，将凸块自身分类为焊料凸块、金凸块、铜柱凸块、和具有混合金属的凸块。最近，已提出了铜柱凸块技术。代替使用焊料凸块，通过铜柱凸块将电子元件连接到衬底上，这实现了凸块桥接可能性最小的优选间距，减少了电路的电容负载，并允许电子元件在更高的频率下运行。
然而，在IC制造中实现这些部件和工艺仍存在挑战。例如，由于来自铜柱的高应力，在集成电路之上的金属间介电(IMD)层和互连结构之间存在分层。因此，需要的是改进的凸块结构和凸块形成的方法。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种半导体器件，包括：衬底；位于所述衬底上方的接触焊盘；在所述衬底上方延伸并在所述接触焊盘上方具有开口的钝化层，所述开口具有第一宽度；在所述开口内的导电通孔；具有完全覆盖所述导电通孔的第二宽度的导电柱，其中所述第一宽度与所述第二宽度的比值是约0.15至0.55。
在该半导体器件中，其中所述钝化层包含非有机材料或聚合物层。
在该半导体器件中，其中所述钝化层具有位于所述接触焊盘上方的额外开口和在所述额外开口内的额外导电通孔。
在该半导体器件中，其中所述导电通孔包含铜或铜合金。
在该半导体器件中，其中所述导电通孔在与所述接触焊盘接触的点处较窄。
在该半导体器件中，其中所述导电通孔包括基本上垂直的侧壁。
在该半导体器件中，其中自上而下观察所述导电通孔的形状包括选自圆形、正方形和十字形中的至少一种。
在该半导体器件中，其中所述导电柱包含铜或铜合金。
在该半导体器件中，其中所述导电通孔的厚度与所述导电柱的厚度的比值是约0.33至0.55。
在该半导体器件中，其中所述导电通孔和所述导电柱是由相同材料形成。
在该半导体器件中，其中所述导电通孔和所述导电柱是由不同材料形成。
根据本发明的另一方面，提供了一种制造半导体器件的方法，包括下列步骤：提供具有接触焊盘的衬底；在所述接触焊盘上方形成第一感光层；图案化所述第一感光层以在一部分所述接触焊盘的上方形成第一开口；在 所述第一开口内电镀导电通孔；移除所述第一感光层；在所述衬底、所述接触焊盘和所述导电通孔上方形成钝化层，并通过研磨所述钝化层暴露出所述导电通孔；在所述导电通孔和所述钝化层上方形成第二感光层；图案化所述第二感光层以形成大于所述导电通孔且完全暴露出所述导电通孔的第二开口；在所述第二开口中电镀导电柱；以及移除所述第二感光层。
在该方法中，其中所述钝化层包含非有机材料或聚合物层。
在该方法中，其中所述导电通孔包含铜或铜合金。
在该方法中，其中所述导电通孔在与接触焊盘接触的点处较窄。
在该方法中，其中所述导电通孔包括垂直的侧壁。
在该方法中，其中自上而下观察所述导电通孔的形状所述导电通孔的形状包括选自圆形、正方形和十字形中的至少一种。
在该方法中，其中所述导电柱包含铜或铜合金。
在该方法中，其中所述导电通孔的厚度与所述导电柱的厚度的比值是约0.33至0.55。
在该方法中，其中所述导电通孔的第一宽度与所述导电柱的第二宽度的比值是约0.15至0.55。
附图说明
当结合附图进行阅读时，根据下面的详细描述可以最佳理解本公开。应该强调的是，根据产业中的标准实践，各种部件没有按比例绘制并仅用于例证的目的。实际上，为了清楚讨论起见，各种部件的尺寸可以被任意地增大或缩减。
图1是根据本公开的各个方面示出用于制造包括导电通孔的半导体器件的方法的流程图；
图2-9B根据本发明的各个方面示出了半导体器件的导电通孔在各个制造阶段的示意性横截面视图；和
图10根据本公开的各个方面示出了半导体器件的导电通孔的示意性自上而下视图。
具体实施方式
可以理解以下公开提供了许多个不同的用于实施本发明的不同特征的实施例或者实例。为简化本公开，组件和布置的具体实例在下面描述。当然，这些仅仅是实例，而不是意在限制本公开。例如，在随后的说明中第一个部件在第二个部件的上方或在第二个部件上的形成可以包括其中第一个部件和第二个部件以直接接触的方式形成的实施例，还可以包括其中其它部件可以在第一个部件和第二个部件之间形成，从而使第一个部件和第二个部件可以不直接接触的实施例。为了达到简明和清楚的目的，可以以不同的比例随意绘制各种部件。
图1是示出了根据本公开的各个方面的用于制造包含导电通孔304a或304b(在图4A到图9B中所示的)的半导体器件200的方法100的流程图。图2A-图9B显示了根据本公开的各个方面所述的半导体器件200的导电通孔304a或304b在各个制造阶段的示意性横截面视图。应该理解在图1的方法100之前、期间和之后可以提供其他工艺，以及某些其他工艺在本文中可能仅是简要说明。而且，简化图1到图9B是为了更好地理解本公开的发明概念。例如，虽然附图示出了半导体器件200的导电通孔304a或304b，但应该理解半导体器件200可能是集成电路(IC)封装的部分，该集成电路封装进一步包含若干其他组件诸如底部填充物(under-fill)、引线框架等。
参考图1和图2A，方法100开始于步骤102，在步骤102中，提供具有接触焊盘204的衬底202。衬底202可以包含硅衬底。衬底202可以可选地包含硅锗、镓砷或其他合适的半导体材料。衬底202可以进一步包括其他部件诸如各种掺杂区、埋层、和/或外延层。而且，衬底202可以是绝缘体上半导体，诸如绝缘体上硅(SOI)或蓝宝石上硅。在其他实施例中，衬底202可以包括掺杂的外延层、梯度半导体层，和/或可以进一步包括在不同类型的另一种半导体层之上的半导体层，诸如硅锗层上硅层。在其他实例中，化合物半导体衬底202可以包含多层硅结构或者硅衬底可以包含多层化合物半导体结构。
衬底202进一步包括多个隔离区(未显示)。隔离区可以采用隔离技 术，诸如硅的局部氧化(LOCOS)或浅沟槽隔离(STI)，来限定和电隔离各种微电子元件(未显示)。在本实施例中，隔离区包括STI。隔离区可以包含氧化硅、氮化硅、氧氮化硅、氟化物掺杂的硅酸盐玻璃(FSG)、低K介电材料、其他合适的材料、和/或其组合。隔离区以及在本实施例中的STI可以通过任何合适的工艺形成。作为一个实例，STI的形成可以包括通过传统的光刻工艺图案化半导体衬底202，在衬底202中蚀刻沟槽(例如，通过使用干法蚀刻、湿法蚀刻和/或等离子体蚀刻工艺)和用介电材料填充沟槽(例如，通过使用化学汽相沉积工艺)。在一些实施例中，经过填充的沟槽可以具有诸如用氮化硅或氧化硅填充的热氧化衬垫层的多层结构。
可以在衬底202中形成的各种微电子元件的实例包括晶体管(例如，p-沟道/n-沟道金属氧化物半导体场效应晶体管(pMOSFET/nMOSFET)、双极结型晶体管(BJT)、高压晶体管、高频晶体管等)；二极管；电阻器；电容器；电感器；保险丝和其他合适的元件。实施各种工艺以形成各种微电子元件，所述工艺包括沉积、光刻、注入、蚀刻、退火、和其他合适的工艺。使微电子元件互连以形成IC器件，诸如逻辑器件、存储器件(例如静态随机存取存储器或SRAM)、射频(RF)器件、输入/输出(I/O)器件、片上系统(SoC)器件、其组合和其他合适类型的器件。
衬底202进一步包含在集成电路之上的层间介电(ILD)层、金属间介电(IMD)层和互连结构。互连结构中的IMD层包括低K介电材料、未掺杂的硅酸盐玻璃(USG)、氟掺杂的硅酸盐玻璃(FSG)、碳掺杂的硅酸盐玻璃、氮化硅、氧氮化硅或其他常用的材料。低k介电材料的介电常数(k值)可以小于约3.9，或小于约2.3。互连结构中的金属线可以由铜或铜合金形成。本领域的技术人员将认识到形成互连结构的具体详情。
接触焊盘204是在顶层IMD层206中形成的顶部互连层，其为导电线路的一部分，并具有必要时通过平坦化工艺(诸如化学机械抛光(CMP))处理的暴露表面。接触焊盘204的合适材料可以包含但不限于例如铜(Cu)、铝(Al)、AlCu、铝合金、铜合金、或其他导电材料。在接合工艺中使用接触焊盘204以将相应芯片中的集成电路连接至外部部件。
应该注意在接触焊盘204上方的大体积导电柱对倒装芯片接合提供更高的机械强度和更低的电阻，但可能对IMD层和互连结构的界面传递高应力，从而导致IMD层和互连结构之间出现分层。
因此，下文参考图3A-9B所讨论的处理方法可以在接触焊盘204和导电柱之间使用小体积的导电通孔来为倒装芯片接合提供足够的机械强度和更低的电阻，而对IMD层和互连结构的界面传递低应力，因此可以避免与来自IMD层和互连结构之间的大体积导电柱的高应力相关的问题。这可以减少IMD层和互连结构之间的分层，并提升器件性能。
参考图3A和图3B，在接触焊盘204和IMD层206的上方形成第一导电层208a或208b。图3A和图3B显示了第一导电层(图3A中的208a和图3B中的208b)的不同实施例。在本公开的实施例中可以应用任何标准种子材料。在一个实施例中，第一导电层208a或208b通过物理汽相沉积(PVD)或溅射由铜形成。在另一个实施例中，第一导电层208a或208b可以由铜合金形成，该铜合金包含银、铬、镍、锡、金、及其组合。沉积第一导电层208a或208b直到厚度t1处于约0.4μm和0.6μm之间。
图1中的方法100继续到步骤104，在步骤104中，在第一导电层208a或208b上方形成第一感光层302a或302b。在一些实施例中，感光层302a或302b可以是干膜或光刻胶膜。可以通过传统沉积工艺在第一导电层208a或208b的上方施加感光层302a或302b。在一个实施例中，通过在第一导电层208a或208b上方层压干膜，从而具有约20μm至约30μm的厚度，形成感光层302a或302b。在另一个实施例中，通过在第一导电层208a或208b上方旋涂光刻胶膜以获得约20μm至约30μm的厚度，形成感光层302a或302b。应该理解可以对感光层302a或302b的厚度进行控制和选择以达到期望值，这尤其与待形成的导电通孔材料的柱体的厚度有关。
图1中的方法100继续到步骤106，在步骤106中，通过图案化第一感光层302a或302b以在一部分的接触焊盘204的上方形成第一开口402a或402b，产生图3A和图3B中的结构。图3A和图3B显示第一开口(图3A中的402a和图3B中的402b)的不同实施例。在一些垂直实施例中，第一开口402a包含垂直侧壁，其中第一感光层302a与第一导电层208a(在 图3A中显示)相接触。在一些楔形实施例中，通过不充分暴露(under-exposing)或不充分显影(under-developing)第一感光层302b形成楔形结构，因此第一开口402b包含向内的楔形，从而存在其中，第一感光层302b与第一导电层208b(在图3B中显示)相接触的锐接触角。在本实施例中，通过传统工艺图案化第一感光层302a或302b以在一部分接触焊盘204的上方形成第一开口402a或402b，从而暴露一部分的第一导电层208a或208b，用于限定导电通孔304a(在图4A到图9A中显示)或304b(在图4B到图9B中显示)的窗口。在一个实施例中，第一开口402a或402b的第一宽度W1在约40μm至45μm的范围内。在一些实施例中，经过图案化的第一感光层302a或302b在接触焊盘204上方具有额外开口。
图1中的方法100继续到步骤108，在步骤108中，通过在第一开口402a或402b中电镀导电通孔304a或304b而产生图4A和图4B中的结构。图4A和图4B显示导电通孔(图4A中的304a和图4B中的304b)的不同实施例。在本实施例中，通过合适的形成方法用导电通孔304a或304b部分地或全部地填充第一开口402a或402b。在本实施例中，使用第一导电层208a或208b作为种子层沿着第一开口402a或402b向上形成导电通孔304a或304b。
导电通孔304a或304b包括铜通孔，因此也被称为铜通孔304a或304b。铜通孔304a或304b意在基本上包括一种层，该层包含纯元素铜、含有不可避免的杂质的铜和含少量元素(诸如钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝或锆)的铜合金。在一些实施例中，导电通孔304a或304b和第一导电层208a或208b可以由相同的材料形成。形成方法可以包括溅射、印刷、电镀、化学镀和常用的化学汽相沉积(CVD)方法。在示例性实施例中，导电通孔304a或304b的厚度t2大于20μm。例如，导电通孔304a或304b的厚度为约20-30μm，但是该厚度可以更大或更小。
图1中的方法100继续到步骤110，在步骤110中，通过移除第一感光层302a或302b产生图5A和图5B中的结构。图5A和图5B显示了导电通孔(图5A中的304a和图5B中的304b)的不同实施例。在本实施例中，采用传统湿法蚀刻或干法蚀刻工艺可以移除第一感光层302a或302b。
然后，使用导电通孔304a或304b作为硬掩模，图5A和图5B还显示了在移除了一部分第一导电层208a或208b从而暴露出IMD层206和一部分的接触焊盘204之后的图4A和图4B中的衬底202。采用湿法蚀刻工艺实施移除一部分第一导电层208a或208b的步骤。例如，湿法蚀刻工艺包括在包含H3PO3和H2O2的溶液中移除一部分第一导电层208a或208b。
在垂直实施例中，可以将第一导电层208a移除直到剩余的第一导电层208a的外部边缘基本上与导电通孔304a的外部边缘对齐(在图5A中显示)。在结构上，导电通孔304a实际上包括导电通孔304a自身和位于导电通孔304a和接触焊盘204之间的剩余的第一导电层208a。而且，导电通孔304a包括基本上垂直的侧壁。
在楔形实施例中，可以将第一导电层208b移除直到剩余的第一导电层208b的外部边缘基本上与导电通孔304b的底部的外部边缘对齐(在图5B中显示的)。在结构上，导电通孔304b实际上包括导电通孔304b自身和位于导电通孔304b和接触焊盘204之间的剩余的第一导电层208b。而且，导电通孔304b在与接触焊盘204接触的点304p处较窄。
应该注意，由于在垂直实施例中剩余的第一导电层208a和导电通孔304a之间的接触面积减少或者由于在楔形实施例中剩余的第一导电层208b和导电通孔304b之间的接触面积减少，附加的蚀刻增加了接触电阻。
图1中的方法100继续到步骤112，在步骤112中，通过在衬底202、接触焊盘204和导电通孔304a或304b的上方形成钝化层306a或306b，并通过研磨钝化层306a或306b暴露出导电通孔304a或304b，而产生图6A和图6B中的结构，从而允许实施后续的导电柱凸块工艺。图6A和图6B显示了导电通孔(图6A中的304a和图6B中的304b)的不同实施例。在本实施例中，钝化层306a或306b在衬底202上方延伸，并在接触焊盘204上方具有开口306c或306d，开口306c或306d具有第一宽度W1(即，几乎与第一开口402a或402b的第一宽度W1相同)。因此，导电通孔304a或304b在钝化层306a或306b的开口内。在一些实施例中，钝化层306a或306b具有在接触焊盘204上方的额外开口和该额外开口内的其他导电通孔。
在一些实施例中，钝化层306由选自下列的非有机材料形成：未掺杂的硅酸盐玻璃(USG)、氮化硅、氧氮化硅、氧化硅、及其组合。可选地，钝化层由聚合物层形成，诸如环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)等，但是也可以使用其它相对较软的介电材料(通常是有机的)。在一个实施例中，可以采用化学汽相沉积(CVD)、高密度等离子CVD(HDP CVD)、次大气压CVD(SACVD)、物理汽相沉积(PVD)或旋涂工艺形成钝化层306。
参考图7A和图7B，在导电通孔304a或304b和钝化层306a或306b上方形成第二导电层308a或308b。图7A和图7B显示导电通孔(图7A中的304a和图7B中的304b)的不同实施例。在本发明的实施例中可以应用任何标准种子材料。在一个实施例中，第二导电层308a或308b由铜通过物理汽相沉积(PVD)或溅射形成。在另一个实施例中，第二导电层308a或308b可以由铜合金形成，该铜合金包含银、铬、镍、锡、金、及其组合。沉积第二导电层308a或308b，直到其厚度t3处于约0.4μm和0.6μm之间。
图1中的方法100继续到步骤114，在步骤114中，第二感光层502a或502b在第二导电层308a或308b上方形成，从而在导电通孔304a或304b和钝化层306a或306b的上方形成。第二感光层502a或502b可以是干膜或光刻胶膜。通过传统沉积工艺可以在第二导电层308a或308b上方施加第二感光层502a或502b。在一个实施例中，通过在第二导电层308a或308b上方层压干膜从而具有约55μm至约60μm的厚度，形成第二感光层502a或502b。在另一个实施例中，通过在第二导电层308a或308b上方旋转涂布光刻胶膜以获得约55μm至约60μm的厚度，形成第二感光层502a或502b。应该理解，可以对第二感光层502a或502b的厚度进行控制和选择以达到期望值，这尤其与待形成的导电柱凸块材料的柱体的厚度有关。
为了限定导电柱504a或504b(在图8A到图9B中显示)的窗口，图1中的方法100继续到步骤114，在步骤114中，通过图案化第二感光层502a或502b以形成大于且完全暴露导电通孔304a或304b的第二开口404a或404b，产生图7A和图7B中的结构。图7A和图7B显示了导电通孔(图7A中的304a和图7B中的304b)的不同实施例。在一个实施例中，第二 开口404a或404b的第二宽度W2处于约80μm至90μm的范围内。
图1中的方法100继续到步骤118，在步骤118中，通过在第二开口404a或404b中电镀导电柱504a或504b产生图8A和图8B中的结构。图8A和图8B显示了导电通孔(图8A中的304a和图8B中的304b)的不同实施例。在本实施例中，通过合适的形成方法，用导电柱504a或504b部分地或完全地填充第二开口404a或404b。在本实施例中，使用第二导电层308a或308b作为种子层，沿着第二开口404a或404b向上形成导电柱504a或504b。
导电柱504a或504b包含铜柱，所以也被称为铜柱504a或504b。铜柱504a或504b意在基本上包含一种层，该层包含纯元素铜、含有不可避免的杂质的铜和含少量元素(诸如钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝或锆)的铜合金。导电柱504a或504b和第二导电层308a或308b可以由相同材料形成。形成方法可以包括溅射、印刷、电镀、化学镀和常用的化学汽相沉积(CVD)方法。例如，实施电化学镀(ECP)以形成铜柱504a或504b。在示例性实施例中，导电柱504a或504b的厚度t4大于55μm。例如，导电柱504a或504b厚约55-60μm，但是该厚度可以更大或更小。
图1中的方法100继续到步骤120，在步骤120中，通过移除第二感光层502a或502b产生图9A和图9B中的结构。图9A和图9B显示了导电通孔(图9A中的304a和图9B中的304b)的不同实施例。在本实施例中，可以采用传统的湿法蚀刻或干法蚀刻工艺移除第二感光层502a或502b。
因此，使用导电柱504a或504b作为硬掩模，图9A和图9B也显示了在移除了一部分第二导电层308a或308b从而暴露出钝化层306a或306b之后的图8A和图8B中的衬底202。采用湿法蚀刻工艺实施移除一部分第二导电层308a或308b的步骤。例如，湿法蚀刻工艺包括在包含H3PO3和H2O2的溶液中移除一部分第二导电层308a或308b。
在本实施例中，可以移除第二导电层308a或308b直到剩余的第二导电层308a或308b的外部边缘基本上与导电柱504a或504b的外部边缘对齐。应该注意，由于剩余的第二导电层308a和导电柱504a之间或者剩余 的第二导电层308b和导电柱504b之间的接触面积减少，附加的蚀刻会增加接触电阻。在结构上，导电柱504a实际上包括导电柱504a自身和位于导电柱504a和导电通孔304a之间的剩余的第二导电层308a。在结构上，导电柱504b实际上包括导电柱504b自身和位于导电柱504b和导电通孔304b之间的剩余的第二导电层308b。
在本实施例中，导电柱504a或504b具有完全覆盖导电通孔304a或304b的第二宽度W2(即，几乎与第二开口404a或404b的第二宽度W2相同)，其中导电通孔304a或304b的第一宽度W1与导电柱504a或504b的第二宽度W2的比值是从约0.15至0.55，或者导电通孔304a或304b的开口306c或306d的第一宽度W1与导电柱504a或504b的第二宽度W2的比值是约0.15至0.55。在一些实施例中，导电通孔304a或304b的厚度t2与导电柱504a或504b的厚度t4的比值是约0.33至0.55。在至少一个实施例中，导电通孔304a或304b和导电柱504a或504b由相同材料形成。在至少一个实施例中，导电通孔304a或304b和导电柱504a或504b由不同材料形成。
图10显示了根据本发明的各个方面的半导体器件200的导电通孔304a或304b的示意性自上而下视图。导电通孔304a或304b的自上而下视图包括选自圆形304c、正方形304d和十字形304e的形状。
因此，半导体器件200包括衬底202；在衬底202上方的接触焊盘204；在衬底202上方延伸并在接触焊盘204上方具有开口306c或306d的钝化层306a或306b，该开口306c或306d具有第一宽度W1；在开口306c或306d内的导电通孔304a或304b；和具有完全覆盖导电通孔304a或304b的第二宽度W2的导电柱504a或504b，其中第一宽度W1与第二宽度W2的比值是约0.15至0.55。钝化层306a或306b可以具有在接触焊盘204上方的额外开口以及在该额外开口内的其他导电通孔。因此，申请人的方法可以减少IMD层和互连结构之间的分层，并提升器件性能。
然后，在形成半导体器件200后实施后续工艺，包括倒装芯片处理，以完成IC制造。
在至少一个实施例中，半导体器件包括衬底；位于该衬底上方的接触 焊盘；在该衬底上方延伸并在该接触焊盘上方具有开口的钝化层，该开口具有第一宽度；在该开口内的导电通孔；和具有完全覆盖导电通孔的第二宽度的导电柱，其中第一宽度与第二宽度的比值是约0.15至0.55。
在其他实施例中，半导体器件包括衬底；位于该衬底上方的接触焊盘；在该衬底上方延伸并在该接触焊盘上具有开口的钝化层，该开口具有第一宽度；在该开口内的导电通孔；以及具有完全覆盖导电通孔的第二宽度的导电柱，其中第一宽度与第二宽度的比值是约0.15至0.55，其中导电通孔的厚度与导电柱的厚度的比值是约0.33至0.55。
在又一些实施例中，用于制造半导体器件的方法包括下列步骤：提供具有接触焊盘的衬底；在该接触焊盘上形成第一感光层；图案化第一感光层以在一部分的该接触焊盘的上方形成第一开口；在该第一开口中电镀导电通孔；移除第一感光层；在该衬底、接触焊盘和导电通孔上方形成钝化层以及通过研磨该钝化层暴露出导电通孔；在该导电通孔和钝化层上方形成第二感光层；图案化第二感光层以形成大于该导电通孔且完全暴露出该导电通孔的第二开口；电镀该第二开口中的导电柱；以及移除该第二感光层。
虽然本公开已描述了优选的实施例，但应该理解本公开不限于所公开的实施例。相反，其意在涵盖各种修改和相似的布置(如对本领域中技术人员是显而易见的)。因此，附加的权利要求的范围应该与最广义的说明一致，从而包含所有这些修改和相似的布置。

Claims (7)

1.一种制造半导体器件的方法，包括下列步骤：
提供具有接触焊盘的衬底；
在所述接触焊盘上方形成第一导电层；
在所述第一导电层上方形成第一感光层；
图案化所述第一感光层以在一部分所述接触焊盘的上方形成第一开口，其中，所述第一开口的宽度小于所述接触焊盘的宽度；
在所述第一开口内电镀导电通孔；
移除所述第一感光层；
使用所述导电通孔作为掩模，移除部分所述第一导电层，直到剩余的所述第一导电层的外部边缘与所述导电通孔的外部边缘对齐；
在所述衬底、所述接触焊盘和所述导电通孔上方形成钝化层，并通过研磨所述钝化层暴露出所述导电通孔；
在所述导电通孔和所述钝化层上方形成第二导电层，其中，所述第二导电层宽于所述导电通孔；
在所述第二导电层上方形成第二感光层；
图案化所述第二感光层以形成大于所述导电通孔且完全暴露出所述导电通孔的第二开口；
在所述第二开口中电镀导电柱；以及
移除所述第二感光层；
其中，所述导电通孔的第一宽度与所述导电柱的第二宽度的比值是0.15至0.55，所述导电通孔的的厚度为20-30μm，所述导电柱的厚度为55-60μm，并且所述导电通孔的厚度与所述导电柱的厚度的比值是0.33至0.55。
2.根据权利要求1所述的方法，其中所述钝化层包含非有机材料或聚合物层。
3.根据权利要求1所述的方法，其中所述导电通孔包含铜或铜合金。
4.根据权利要求1所述的方法，其中所述导电通孔在与接触焊盘接触的点处较窄。
5.根据权利要求1所述的方法，其中所述导电通孔包括垂直的侧壁。
6.根据权利要求1所述的方法，其中自上而下观察所述导电通孔的形状，所述导电通孔的形状包括选自圆形、正方形和十字形中的至少一种。
7.根据权利要求1所述的方法，其中所述导电柱包含铜或铜合金。
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Application publication date: 20160921