CN102074487B - 半导体组装结构与其形成方法 - Google Patents
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Abstract
本发明提供一种半导体组装结构与其形成方法。方法包括清洁一包含铜的连接结构,且此连接结构形成于一基材之上;施加一冷锡到连接结构;施加一热锡到连接结构;以及旋转润洗(spin rising)与干燥(drying)连接结构。本发明可以减少位于柱状结构或凸块的铜-锡界面中的孔洞数目与尺寸。
Description
技术领域
本发明涉及一种半导体组装结构与其形成方法,尤其涉及一种降低铜-锡界面孔洞(voids)的半导体组装结构与其形成方法。
背景技术
随着半导体元件的尺寸持续降低,使用倒装芯片组装结构(flip chipassemblies)变得十分普及。倒装芯片组装结构(flip chip assemblies)借由在半导体芯片或集成电路的表面上形成外部电性垫片,以连接到焊料柱或凸块(solder pillars or bumps)。这些焊料柱或凸块接着利用焊接工艺(solderprocessing)连接到基材或载板(carrier)。焊料柱或凸块使得基材与芯片之间产生物理性与电性的连接。此外,一般会使用底部填充物(underfill),以填充介于基材与芯片之间的空隙,且此底部填充物围绕焊料柱或凸块,使得倒装芯片组装结构具有较佳的机械强度。
焊料柱或凸块一般包括铜,也可使用其他种类的焊料。此外,焊料柱或凸块一般会涂布或浸渍于锡中,以保护凸块免受外界环境因素的影响,例如腐蚀,并且有助于焊接工艺(solder processing)。然而,将焊料柱或凸块浸渍于锡中,于焊料柱或凸块内的铜与锡之间的界面通常会随机形成孔洞(voids)。这些孔洞一般的宽度为约200纳米。孔洞可能会减弱连接结构的机械强度,可能导致半导体芯片的脱层(delamination),并且可能导致裂缝(cracks)存在于焊料柱或凸块内,此裂缝会造成开路(open electrical circuits)。
孔洞的成因不是显而易见的。推论的成因之一在于,存在于铜锡界面的氧化铜或不规则表面,阻止锡与铜进行反应或键结,因而形成不规则孔洞。此外,于高温下沉积锡于铜之上,介于铜与锡之间的反应可能导致侧向剪切应力(lateral shear stresses),而侧向剪切应力会造成孔洞的形成。
发明内容
为了解决现有技术的问题,本发明提供一种半导体组装结构的形成方法,包括以下步骤:清洁形成于一基材上的一连接结构(connector),其中该连接结构包括铜;施加一冷锡到该连接结构;施加一热锡到该连接结构;以及旋转润洗(spin rising)与干燥(drying)该连接结构。
本发明另提供一种半导体组装结构(semiconductor assembly),包括:一半导体芯片;一垫片形成于该半导体芯片上;一铜连接结构物理性耦合到该垫片;一铜-锡化合物层形成于该铜连接结构之上,其中介于该铜-锡化合物层与该铜连接结构之间的一界面无宽度大于约100纳米的孔洞(voids)。
本发明也提供一种半导体组装结构,包括:一铜连接结构;一铜锡化合物层位于该铜连接结构的外侧表面上,其中该铜连接结构的外侧表面无宽度大于约100纳米的孔洞(voids);一第一锡层位于该铜-锡化合物层之上;以及一第二锡层位于该第一锡层之上。
本发明可以减少位于柱状结构或凸块的铜-锡界面中的孔洞数目与尺寸。
为让本发明的上述和其他目的、特征、和优点能更明显易懂,下文特举出优选实施例,并配合所附附图,作详细说明如下:
附图说明
图1为一流程图,用以说明本发明的流程。
图2A为一剖面图,用以说明本发明一优选实施例的半导体芯片的一部分。
图2B为一剖面图,用以说明本发明一优选实施例的倒装芯片组装结构。
图2C为一剖面图,用以说明本发明一优选实施例包括图2B的倒装芯片组装结构。
其中,附图标记说明如下:
5~预清洁(pre-clean)铜表面
10~微蚀刻(micro-etch)铜
15~浸泡于冷锡
20~浸泡于热锡
25~旋转润洗干燥(spin rinse dry)
30~退火(anneal)
50~半导体芯片
52~垫片
54~铜柱
56~铜-锡化合物
58~未反应锡
60~铜-锡界面
64~封装基材
100~芯片部分
102~倒装芯片组装结构
具体实施方式
下述实施例将会讨论特定的内容,称为倒装芯片组装(flip chipassembly)。然而,也可包含其他使用类似技术去接合或焊接一组装结构的其他实施例。
图1显示一实施例的工艺。首先提供包含铜的柱状结构或凸块(pillar orbump)。柱状结构或凸块(pillar or bump)可以直接设置于半导体芯片的电性垫片上,以应用于倒装芯片组装结构(flip chip assembly)或其他类似的应用。于步骤5中,对铜的柱状结构或凸块的表面进行预清洁(pre-clean)。可利用稀释的硫酸(H2SO4)或其他适合的化学品进行预清洁。也可借由将晶片或半导体芯片浸泡于硫酸或其他化学品的浴槽(bath)中进行预清洁,其中柱状结构或凸块位于晶片或半导体芯片的表面上。此外,也可将一批晶片垂直地浸泡于含有硫酸或其他化学品的桶槽(tank)中进行预清洁。预清洁的目的在于清洁铜的表面,并且移除可能形成于铜表面上的氧化铜。此外,预清洁也可浸湿铜表面,以避免孔洞形成于后续的铜锡界面间。
于步骤10中,可视需要(optional)对柱状结构或凸块进行微蚀刻(micro-etch)。进行微蚀刻的目的在于确保大致上(substantially)所有的氧化铜已从柱状结构或凸块的表面移除。可利用过硫酸钠(sodium persulfate)、硫酸(sulfuric acid)、上述的组合或类似的成分进行微蚀刻。
于步骤15中,将柱状结构或凸块浸泡到冷锡中,以进行预浸渍(pre-dip)。可借由将晶片或半导体芯片浸泡于温度接近室温的锡浴槽(bath)中进行浸渍,其中柱状结构或凸块位于晶片或半导体芯片的表面上,另言之,温度为约20℃-25℃。此外,也可将一批晶片垂直地浸泡于含有冷锡的桶槽(tank)中。冷锡可与还原剂混合,例如硫脲(thiourea),用以降低介于铜与锡之间的反应电位,进而促进化学反应。
于步骤20中,将柱状结构或凸块浸渍到热锡中,以进行大量沉积(bulkdeposition)。借由浸泡柱状结构或凸块到温度为约40℃-75℃的锡浴槽(bath)中以进行浸渍。此外,可将一批晶片垂直地浸泡于含有热锡的桶槽(tank)中。热锡可与还原剂混合,例如硫脲(thiourea),用以降低介于铜与锡之间的反应电位。
借由进行不同温度的浸渍反应,可以释放或减少介于铜与锡之间因化学反应所引起的应力。举例而言,相对在较高温度下沉积锡,在较低沉积温度与较低沉积速率下,锡原子具有较低的键结能量,因此,每一个锡原子较不易与多个铜原子形成键结。由于锡沉积于铜之上是较为致密的,因此,较少的应力存在于铜-锡界面间,因而可避免侧向剪切应力(lateral shear stresses)发生于铜与铜锡化合物之间。之后,在较高沉积温度与较高沉积速率下沉积锡到之前沉积的冷锡上,并没有任何明显的界面存在于冷锡与热锡之间。因此,此种热梯度可以避免在铜-锡界面之间形成孔洞。
于步骤25中,进行旋转润洗干燥(spin rinse dry),用以从柱状结构或凸块与晶片或半导体芯片中移除过量的锡,并且干燥已反应的铜与锡。可借由旋转晶片以及喷洒水到晶片上以进行旋转润洗干燥(spin rinse dry)。之后,施加氮气气流于晶片的表面上,以避免水渍残留(mark)于晶片上。于步骤30中,可视需要进行退火步骤,以使锡进一步与铜进行反应。可于温度为约100℃-250℃,一般为约150℃的环境下进行退火工艺。退火工艺可维持于30分钟~4小时。退火工艺可以更进一步释放于沉积工艺中由铜与锡之间的化学反应所引起的应力。
接着,可以进行其他后续的工艺。举例而言,如果先前并未执行切割晶片步骤,可从晶片上切割具有凸块或柱状结构形成于其上的半导体芯片。此外,利用柱状结构或凸块可以将半导体芯片焊接到基材或载板上,也可将底部填充物填充于芯片与基材之间且围绕柱状结构或凸块。不同的应用将会有不同的工艺步骤,且此处的步骤仅用以举例说明。
图2A显示依据本发明的一实施例的半导体芯片50的一芯片部分100。半导体芯片50包括垫片52与铜柱54。铜柱54被铜-锡化合物56与未反应锡58的薄层所包围。未反应锡58可与后续工艺步骤的其他材料反应,可见于最后的芯片或组装结构中。如上所述,铜-锡化合物56与锡层58来自于锡以双重温度沉积于铜柱54上。铜-锡化合物56的厚度取决于沉积工艺时,铜与锡的扩散与反应程度。在沉积工艺中,位于铜柱54与铜锡化合物56之间的铜-锡界面60仍可能产生孔洞,然而,于此实施例中,此孔洞的宽度大约为100纳米,小于公知技术的200纳米。
图2B显示半导体芯片50的一部分倒装芯片组装结构102,此时铜柱已耦合到封装基材64上。图2C显示一倒装芯片组装结构,其中包括显示于图2B中的倒装芯片组装结构102。于图2C中的倒装芯片组装结构中包括4个芯片部分100,且其对应的元件结构已显示于图2A与图2B中,虽然只有一个芯片部分100被特别列举。芯片部分102的数目仅为举例目的而列举,并未加以限制。
借由上述讨论的工艺,可以减少位于柱状结构或凸块的铜-锡界面中的孔洞数目与尺寸。首先,于预清洁步骤时,先移除铜表面上的氧化铜,同时浸湿铜表面。此预清洁步骤移除由氧化铜所引起的不规则孔洞,且避免气泡存在于铜上。利用不同的热梯度沉积锡于铜柱上,以释放铜-锡界面的应力,因而可降低孔洞的数目与尺寸。借由退火铜-锡化合物也可释放应力。虽然使用上述的步骤仍然会存在一些孔洞,但是比起公知的工艺与结构,孔洞的数目与宽度是被减少的。
虽然本发明已以数个优选实施例揭示如上,然其并非用以限定本发明,任何本领域技术人员,在不脱离本发明的精神和范围内,当可作任意的更动与润饰,因此本发明的保护范围当视所附的权利要求所界定的范围为准。
Claims (6)
1.一种半导体组装结构的形成方法,包括以下步骤:
清洁形成于一基材上的一连接结构,其中该连接结构包括铜;
施加一冷锡到该连接结构,其中该冷锡的温度为20℃-25℃;
施加一热锡到该连接结构,其中该热锡的温度为40℃-75℃;以及
旋转润洗与干燥该连接结构。
2.如权利要求1所述的半导体组装结构的形成方法,还包括微蚀刻该连接结构,其中该微蚀刻包括利用过硫酸钠、硫酸或上述的组合。
3.如权利要求1所述的半导体组装结构的形成方法,还包括退火该连接结构。
4.如权利要求1所述的半导体组装结构的形成方法,其中施加该冷锡到该连接结构包括浸泡该连接结构的表面到一冷锡浸泡液中,其中施加该热锡到该连接结构包括浸泡该连接结构的表面到一热锡浸泡液中。
5.如权利要求1所述的半导体组装结构的形成方法,其中该连接结构包括一铜凸块形成于一半导体基材上。
6.如权利要求1所述的半导体组装结构的形成方法,其中该冷锡与该热锡各自包括一还原剂,其中该还原剂包括一硫脲混合物。
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US12/891,487 US8679591B2 (en) | 2009-11-17 | 2010-09-27 | Method for reducing voids in a copper-tin interface and structure formed thereby |
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KR102635524B1 (ko) | 2018-09-18 | 2024-02-13 | 삼성디스플레이 주식회사 | 표시장치 및 이의 제조 방법 |
US11746433B2 (en) | 2019-11-05 | 2023-09-05 | Macdermid Enthone Inc. | Single step electrolytic method of filling through holes in printed circuit boards and other substrates |
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CN101233613A (zh) * | 2005-08-11 | 2008-07-30 | 德州仪器公司 | 具有改进的机械可靠性和热可靠性的半导体装置 |
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JP2002043352A (ja) * | 2000-07-27 | 2002-02-08 | Nec Corp | 半導体素子とその製造方法および半導体装置 |
JP4998704B2 (ja) * | 2007-01-22 | 2012-08-15 | 上村工業株式会社 | 置換錫合金めっき皮膜の形成方法、置換錫合金めっき浴及びめっき性能の維持方法 |
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TW200939368A (en) | 2008-03-10 | 2009-09-16 | Univ Nat Pingtung Sci & Tech | Processing method for copper pads of wafer |
JP2011521028A (ja) * | 2008-05-15 | 2011-07-21 | サウディ ベーシック インダストリーズ コーポレイション | 充填ポリプロピレン組成物から作製された耐引掻性成形物品 |
TWM368273U (en) | 2009-06-03 | 2009-11-01 | Flexium Interconnect Inc | Soldering pad capable of improving adhesive force |
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