CN102033971A - Design method of circuit patterns and rapid thermal annealing method of semiconductor device - Google Patents
Design method of circuit patterns and rapid thermal annealing method of semiconductor device Download PDFInfo
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- 238000010521 absorption reaction Methods 0.000 description 2
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Abstract
The invention provides a design method of circuit patterns and a rapid thermal annealing method of a semiconductor device. The design method comprises the following steps of: establishing a ternary corresponding relationship among electric parameters, an annealing temperature and STI pattern distribution densities of the device, and establishing a binary corresponding relationship between the electric parameters of the device and gate pattern lengths; obtaining the difference between the STI pattern distribution densities in a specific area and a target area; finding the difference between the electric parameters, which corresponds to the difference between the STI pattern distribution densities, according to the ternary corresponding relationship; finding the difference between the gate pattern lengths, which corresponds to the difference between the electric parameters, according to the binary corresponding relationship; and adjusting the gate pattern length in the specific area according to the difference between the gate pattern lengths. Relative to the traditional design method, the design method of the circuit patterns which is provided by the invention, does not need to add patterns in a virtual structure and can avoid the negative influence on the normal circuit performance after the virtual structure is added in the semiconductor device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly the rapid thermal annealing method of a kind of method for designing of circuit pattern and semiconductor device.
Background technology
Ic manufacturing technology all is to design earlier circuit pattern as required, make mask according to circuit pattern then, utilize a plurality of mask through technologies such as a series of deposits, exposure, etching and annealing successively, thereby in a wafer, finish the making of a plurality of chips of repeated arrangement simultaneously.Product for the multicore sheet, because different chips are based on separately application background, have different semiconductor structures, the circuit pattern that respective design goes out is variant with regard to each, makes that circuit pattern shows obvious unevenness in the effective coverage of entire wafer (field).
For example, the distribution density of active area and grid is all very little in the radio circuit chip, and active area or grid have bigger distribution density in the in-line memory circuit chip, on the other hand, even also can there be zone in the same chip with different active areas or grid distribution density.This species diversity of the distribution density of semiconductor structure such as active area or grid, may cause wafer being carried out rapid thermal anneal process (rapid thermal annealing, RTA) time, the difference that can cause the wafer local temperature, thereby the uniformity coefficient of the chip electric property that influence is finally made on entire wafer.
Publication number discloses the method that a kind of limited area of striding wafer in the rapid thermal anneal process process provides uniform temperature for the Chinese patent of 101454870A, specifically comprise:, determine first reflectivity in this first by the density of first structure in the first of measuring this limited area.Then, this method is determined second reflectivity in this second portion by the density of second structure in the second portion of measuring this limited area.Particularly, this first structure comprises diffusion fill shapes and polysilicon conductor filling shape (non-active pesudo-structure); And this second structure includes source circuit structure, more described then first reflectivity and second reflectivity, and the lap of diffusion fill shapes and polysilicon conductor filling shape makes first reflectivity and the second reflectivity balance in first structure by regulating.
Said method increases pesudo-structure in the chip (dummy gate or virtual active area) accordingly by increase filling shape in the specific region when circuit pattern designs, thereby various piece is to the reflectivity of RTA radiation on the balance entire wafer, and then improves the process uniformity of RTA.
Yet problem is, specific region for some circuit does not allow to increase described pesudo-structure (hereinafter referred to as virtual architecture) usually, for example, specific region in the radio circuit below the inductance and metal-dielectric-metal (metal-insulator-metal, MIM) specific region below the capacitor, reason are in these specific regions the electrical performance that virtual architecture may influence circuit to be set.
Summary of the invention
The problem that the present invention solves is how to provide non-uniform temperature phenomenon that a kind of rapid thermal annealing method reduces to avoid increasing the virtual architecture influence electrical to semiconductor device.
The problem that the present invention solves is the influence of non-uniform temperature phenomenon to avoid adopting virtual architecture electrical to semiconductor device that how to provide a kind of circuit pattern method for designing to reduce.
For addressing the above problem, the invention provides a kind of method for designing of circuit pattern, may further comprise the steps:
Set up the ternary corresponding relation between device electrical parameter, annealing temperature and the STI pattern distribution density, and, the binary corresponding relation of device electrical parameter and gate pattern length set up;
Obtain the difference of the STI pattern distribution density of specific region and target area;
Find the electrical parameter difference of the difference correspondence of described STI pattern distribution density according to described ternary corresponding relation;
Find the difference of gate pattern length of the difference correspondence of described electrical parameter according to described binary corresponding relation;
Adjust the gate pattern length of specific region by the difference of described gate pattern length.
The difference of the STI pattern distribution density of described acquisition specific region and target area may further comprise the steps:
Obtain the STI pattern distribution density D of target area
0
Obtain the STI pattern distribution density D of specific region
x
Calculate described D
xWith D
0Difference.
The STI pattern distribution density D of described acquisition target area
0May further comprise the steps:
Determine the target electrical parameter according to the designing requirement of semiconductor device;
By the ternary corresponding relation of described device electrical parameter, annealing temperature and STI pattern distribution density, find the pairing STI pattern distribution of target electrical parameter density, also be the STI pattern distribution density D of described target area
0
The STI pattern distribution density D of described acquisition specific region
xMay further comprise the steps:
Circuit pattern is divided into the zone of a plurality of repetitions;
Detect each regional active area pattern distribution density A respectively
xDistribution density P with gate pattern
x
According to formula D
x=(1-A
x) * (1-P
x) calculate each regional STI pattern distribution density;
Judge whether each regional STI pattern distribution density equals target area STI pattern distribution density; If not, then should the zone as described specific region.
Described specific region is the virtual architecture sensitizing range.
Described electrical parameter comprises saturation current or threshold voltage.
Ternary corresponding relation between described device electrical parameter, annealing temperature and the STI distribution density is a linear relationship.
The binary corresponding relation of described device electrical parameter and gate pattern length is a linear relationship.
The present invention also provides a kind of rapid thermal annealing method of semiconductor device, may further comprise the steps:
Set up the ternary corresponding relation between device electrical parameter, annealing temperature and the STI pattern distribution density, and, the binary corresponding relation of device electrical parameter and gate pattern length set up;
Obtain the difference of the STI pattern distribution density of specific region and target area;
Find the electrical parameter difference of the difference correspondence of described STI pattern distribution density according to described ternary corresponding relation;
Find the difference of gate pattern length of the difference correspondence of described electrical parameter according to described binary corresponding relation;
Adjust the gate pattern length of specific region by the difference of described gate pattern length;
Utilize adjusted gate pattern to make the grid of semiconductor device specific region;
Obtain the target annealing temperature of the STI pattern distribution density correspondence of described target area by described ternary corresponding relation, utilize this annealing temperature that semiconductor device is carried out annealing in process, reach the target electrical parameter.
Ternary corresponding relation between described device electrical parameter, annealing temperature and the STI pattern distribution density is a linear relationship.
Compared with prior art, technique scheme has the following advantages:
The method for designing of described circuit pattern, the distribution density that reflects AA pattern and Ploy pattern with the distribution density of STI pattern, and, according to having the ternary corresponding relation between the distribution density of STI pattern and device electrical parameter and the annealing temperature three, and, the binary corresponding relation of device electrical parameter and gate pattern length, adjust the length of the gate pattern of specific region, so that the electrical parameter value in this specific region is near the target electrical parameter, remedy unevenness by the distribution density of STI pattern in the entire circuit pattern, make mask by the circuit pattern that obtains like this, and then utilize above-mentioned mask to make semiconductor device, improve the temperature homogeneity of RTA technology, thereby obtain the homogeneity of excellent electrical property parameter.
With respect to traditional method for designing, circuit pattern method for designing provided by the invention does not need to add the pattern of virtual architecture, after can avoiding in semiconductor device increasing virtual architecture, and the adverse effect that normal circuit performance is brought.
Description of drawings
Shown in accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by physical size equal proportion convergent-divergent.
Fig. 1 is the process flow diagram of the method for designing of circuit pattern in the embodiment of the invention;
Fig. 2 is the partial structurtes synoptic diagram of semiconductor device in the embodiment of the invention;
Fig. 3 is the corresponding relation figure between saturated electric current and annealing temperature in the embodiment of the invention, the STI pattern distribution density;
Fig. 4 is the binary corresponding relation figure of saturated electric current and gate pattern length in the embodiment of the invention;
Fig. 5 is the partial schematic diagram of circuit pattern in the embodiment of the invention;
Fig. 6 is the rapid thermal annealing method flow diagram of semiconductor device in the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
A lot of details have been set forth in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here and implement, those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with synoptic diagram, when the embodiment of the invention is described in detail in detail; for ease of explanation; the sectional view of expression device architecture can be disobeyed general ratio and be done local the amplification, and described synoptic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Alleged herein " semiconductor device " refers generally to a plurality of integrated circuit (IC) chip (Die) on the wafer.Alleged herein " pattern " or " circuit pattern " are meant the figure (layout) that is used to make the mask (mask) that respectively goes on foot exposure technology, for example gate pattern, active area pattern etc.Alleged herein " semiconductor structure " is meant in esse various ingredients in the semiconductor device, for example grid, active area, shallow trench isolation from etc.
In traditional ic manufacturing process, the inhomogeneous meeting that circuit pattern distributes causes the non-uniform temperature phenomenon of rapid thermal anneal process, and then can directly influence the electric property of semiconductor device in the integrated circuit, cause the parameters such as threshold voltage, saturation current of the interior device of regional area can not reach desired value.
For example, the distribution density of active area and grid is all very little in the radio circuit chip, and active area or grid have bigger distribution density in the in-line memory circuit chip, on the other hand, even also can there be zone in the same chip with different active areas or grid distribution density.This species diversity of the distribution density of semiconductor structure such as active area or grid, may cause when wafer is carried out rapid thermal anneal process, the difference that can cause the wafer local temperature, thereby the uniformity coefficient of the chip electric property that influence is finally made on entire wafer.
The inventor discovers, because the mode (being called for short the RTA radiation) of the high-intensity radiation of light source heating of RTA process using, the various semiconductor structures of the uneven phenomenon of said temperature and wafer semiconductor-on-insulator device are to the absorption of RTA radiation and reflect relevant.For example, in the RTA technology that source/drain region hot activation or metal silicide form, active area (Active Area, AA) and grid (Ploy) often reflect described RTA radiation, and shallow channel isolation area (Shallow Trench Isolate STI) often absorbs described RTA radiation.
Different semiconductor device on the wafer, in the perhaps same semiconductor device, active area, grid requires to have nothing in common with each other according to product design from the distribution density that waits semiconductor structure in different zones with shallow trench isolation usually, so, setting under the same RTA radiation annealing temperature, AA, the chip temperature of Ploy high density and STI density regions, on the low side relatively owing to reflect stronger cause, otherwise, AA, the chip temperature of Ploy low-density and STI high-density region, higher relatively partially owing to absorb stronger cause, actual treatment temp inhomogeneous that has caused wafer semiconductor-on-insulator device thus, therefore the inhomogeneous activation and the diffusion that can influence impurity then of this RTA actual treatment temp can cause electrical parameter inhomogeneous.
The inventor further discovers, have objective corresponding relation between the electrical parameter of device and the RTA radiation annealing temperature three in the distribution density of STI and the semiconductor device, and in fact, the distribution density of the distribution density of STI and AA and Ploy is complementary,
Because the formation of semiconductor device depends on the design of circuit pattern in advance, based on this, the present invention is in the creationary notion of introducing STI pattern distribution density, the distribution density that reflects AA pattern and Ploy pattern with the distribution density of STI pattern, and, according to having the ternary corresponding relation between the distribution density of STI pattern and device electrical parameter and the annealing temperature three, and, the binary corresponding relation of device electrical parameter and gate pattern length, adjust the length of the gate pattern of specific region, so that the electrical parameter value in this specific region is near the target electrical parameter, remedy the unevenness of the distribution density of STI pattern, make mask by the circuit pattern that obtains like this, and then utilize above-mentioned mask to make semiconductor device, thereby improve the temperature homogeneity of RTA technology.
Describe a specific embodiment of circuit pattern method for designing of the present invention in detail below in conjunction with accompanying drawing.
Fig. 1 is the process flow diagram of the method for designing of circuit pattern in the present embodiment, and Fig. 2 is the partial schematic diagram of the circuit pattern of semiconductor device in the present embodiment, and Fig. 3 is a saturated electric current I in the present embodiment
DsatAnd corresponding relation figure between the annealing temperature, STI distribution density, Fig. 4 is a saturated electric current I in the present embodiment
DsatBinary corresponding relation figure with gate pattern length.
As shown in Figure 1, the method for designing of circuit pattern may further comprise the steps:
Step S1: set up the ternary corresponding relation between device electrical parameter, annealing temperature and the STI pattern distribution density, and, set up the binary corresponding relation of device electrical parameter and gate pattern length.
Concrete, as previously mentioned, the inventor is through discovering the objective ternary corresponding relation of existence between the electrical parameter of semiconductor device, annealing temperature and the STI pattern distribution density.Therefore, by setting up the database that concerns between electrical parameter, annealing temperature and the STI pattern distribution density three in advance, and go out described ternary corresponding relation collection of illustrative plates, for example Fig. 3 according to database simulation.
With reference to shown in Figure 3, the inventor discovers the saturation current I of device
DsatAnd have linear ternary corresponding relation between the STI pattern distribution density of the annealing temperature of RTA radiation, semiconductor device, and be signal only among the figure with limited embodiment, the left longitudinal axis is represented saturation current I
Dsat, the right longitudinal axis is represented the annealing temperature of RTA radiation, for example is peak temperature, transverse axis is represented STI pattern distribution density, as seen from Figure 3, is linear relationship substantially between the three.
When the design circuit pattern, according to above-mentioned ternary corresponding relation, according to required target saturation current I
DsatSet corresponding target STI pattern distribution density D
0,, design STI pattern and corresponding AA pattern and Ploy pattern then according to this target STI pattern distribution density and other designing requirements.In theory, according to foregoing circuit design producing semiconductor device, adopt target STI pattern distribution density D
0The annealing temperature T of corresponding RTA radiation
0(abbreviation annealing temperature), the target saturation current value I that can obtain to adhere to specification
Dsat
But this is an ideal situation, in fact, because semiconductor device is based on separately application background, corresponding semiconductor circuit structure also has nothing in common with each other, for example for the circuit pattern of COMS logical circuit or DRAM memory circuit, usually all include the source region pattern, gate pattern and STI pattern, with reference to shown in Figure 2, solid strip is represented the active area pattern, and the diagonal line hatches strip is represented gate pattern, clear area between them is the STI pattern, the circuit pattern of semiconductor device comprises in entire wafer: the rarefaction Isolate (representing with I among the figure) of active area pattern and gate pattern, and, the compact district Dense (representing with D among the figure) of active area pattern and gate pattern.Setting under the same RTA radiation annealing temperature, the chip temperature of compact district D is because to the stronger cause of RTA radiation reflex and on the low side relatively, otherwise, the chip temperature of rarefaction I, because to the stronger cause of RTA radiation absorption and higher relatively partially, caused actual annealing temperature inhomogeneous of wafer semiconductor-on-insulator device thus.
And the annealing temperature unevenness can influence the uniformity coefficient difference of the activation and the diffusion of each region doping ion, causes the inhomogeneous of semiconductor device electrical parameter on the entire wafer.Can adopt increases the difference that the virtual architecture method of patterning compensates STI pattern distribution density, makes being tending towards evenly of actual annealing temperature of semiconductor device, to improve the homogeneity of electrical parameter.But just as described in the background art, for example the zone below inductance and the metal-dielectric-metallic circuit is provided with virtual architecture in the radio circuit, may influence the electric property of circuit, and such zone can be called the virtual architecture sensitizing range.
In the present embodiment, do not need to be provided with described virtual architecture, but compensate the inhomogeneous of STI pattern distribution density by the method for adjusting gate pattern length.Adopt STI pattern distribution density to reflect the distribution density of AA pattern and Ploy pattern, be equivalent to, express the actual RTA temperature non of entire wafer semiconductor-on-insulator device with STI pattern distribution density D x.
Therefore, also to obtain the situation of STI pattern distribution density in the entire circuit pattern,,, promptly carry out following steps for follow-up adjustment provides reference frame to detect the unevenness of STI pattern.
Step S2: the difference DELTA D that obtains the STI pattern distribution density of specific region and target area.
In this step, obtain the STI pattern distribution density D of target area earlier
0, then obtain the STI pattern distribution density D of specific region
x, calculate both difference (D then
x-D
0).
Concrete, the STI pattern distribution density D of acquisition target area
0Step comprise:
Designing requirement according to semiconductor device, determine the target electrical parameter earlier, then by the electrical parameter of setting up among the step S1, annealing temperature and STI pattern distribution density ternary corresponding relation, obtaining pairing STI pattern distribution density, also is the STI pattern distribution density of described target area.For example check in target saturation current I by Fig. 3
Dsat(target) Dui Ying target area STI distribution density D
0In other words, to improve the homogeneity of STI pattern distribution be exactly that the STI pattern distribution density of expectation entire circuit pattern all tends to even equals described target area STI distribution density D to what is called
0
But, in fact not only have the target area in the circuit pattern, and also exist described specific region, the specific region in the present embodiment to refer to that STI pattern distribution density is not equal to described target area STI distribution density D in the circuit pattern usually
0The zone.And this specific region can't increase the pattern of virtual architecture, for example has the zone of RF circuit pattern or MIM condenser network pattern.
Concrete, the STI pattern distribution density D of acquisition specific region
xStep comprise:
In advance circuit pattern is divided into the zone of a plurality of repetitions, then detects each regional active area pattern distribution density A respectively
xDistribution density P with gate pattern
xAccording to formula D
x=(1-A
x) * (1-P
x) calculate each regional STI pattern distribution density D
xJudge whether each regional STI pattern distribution density equals target area STI pattern distribution density; If not, then should the zone as described specific region, its STI pattern distribution density D
xBe the STI pattern distribution density D of described specific region
xIf, process ends then.
Because the distribution density of active area pattern, gate pattern and STI pattern has determined the distribution density of corresponding active area, grid and STI in the practical semiconductor device, based on this, (1-A in the above formula
x) the expression active area is to the transmitance of RTA radiation, (1-P
x) the expression grid is to the transmitance of RTA radiation, also, the STI distribution density equals active area to the transmitance of RTA radiation and the grid structure product to the transmitance of RTA radiation.
At last, go out the STI pattern distribution density D of specific region by aforementioned calculation
xSTI pattern distribution density D with the target area
0Difference DELTA D=(D
x-D
0).
Step S3:, find the STI pattern distribution density D of specific region according to the ternary corresponding relation between device electrical parameter, annealing temperature and the STI pattern distribution density
xSTI pattern distribution density D with the target area
0The electrical parameter difference of difference DELTA D correspondence.
For example, referring to shown in Figure 3, find by curve among the figure according to the Δ D on the transverse axis that electrical parameter is saturation current I on the left longitudinal axis
DsatDifference DELTA ID.
Step S4:, find the difference DELTA CD of gate pattern length of the difference DELTA ID correspondence of described electrical parameter according to the binary corresponding relation of device electrical parameter and gate pattern length.
For example, referring to shown in Figure 4, the inventor discovers the saturation current I of device
DsatAnd have linear binary corresponding relation between the gate pattern length, and be signal only among the figure with limited embodiment, the longitudinal axis is represented gate pattern length C D, transverse axis is represented saturation current I
Dsat, as seen from Figure 4, be linear relationship substantially between the two.So, find the difference DELTA CD of the gate pattern length on the longitudinal axis by curve among the figure according to the Δ ID on the transverse axis.
Fig. 5 is the partial schematic diagram of circuit pattern in the present embodiment.Circuit pattern comprises a plurality of gate patterns 10 among Fig. 5, described gate pattern 10 be shaped as strip, and the size of each gate pattern 10, shape and spacing distance are all identical, and the mask of being made by described gate pattern 10 can form grid by exposure, etching in wafer.
Wherein, the length of described gate pattern is meant in the gate pattern that it has determined the length of raceway groove corresponding to the length of the critical size (CD) of grid.For example, the length of gate pattern 10 rectangle minor face a is the length of described gate pattern among Fig. 5.
Step S5: the gate pattern length of adjusting described specific region by the difference DELTA CD of described gate pattern length.
As shown in Figure 5, the gate pattern 10 usefulness solid lines before adjusting represent that adjusted gate pattern 10 ' dots, and as seen, gate pattern length increases to a ' by a.
In the present embodiment, because the curve among Fig. 3 is a monotone increasing, the STI pattern distribution density D of described specific region
xSTI pattern distribution density D greater than described target area
0, cause the saturation current ID of specific region
xSaturation current ID greater than the target area
0, and the curve among Fig. 4 is a monotone decreasing, the gate pattern length of specific region should increase on the basis of original length accordingly, to reduce specific region saturation current ID bigger than normal
x, make its saturation current ID near the target area
0Vice versa, repeats no more here.
The method for designing of the above circuit pattern, the distribution density that reflects AA pattern and Ploy pattern with the distribution density of STI pattern, and, according to having the ternary corresponding relation between the distribution density of STI pattern and device electrical parameter and the annealing temperature three, and, the binary corresponding relation of device electrical parameter and gate pattern length, adjust the length of the gate pattern of specific region, so that the electrical parameter value in this specific region is near the target electrical parameter, remedy unevenness by the distribution density of STI pattern in the entire circuit pattern, make mask by the circuit pattern that obtains like this, and then utilize above-mentioned mask to make semiconductor device, improve the temperature homogeneity of RTA technology, thereby obtain the homogeneity of excellent electrical property parameter.
With respect to traditional method for designing, the circuit pattern method for designing that present embodiment provides does not need to add the pattern of virtual architecture, after can avoiding in semiconductor device increasing virtual architecture, and the adverse effect that normal circuit performance is brought.
Describe a specific embodiment of the rapid thermal annealing method of semiconductor device of the present invention in detail below in conjunction with accompanying drawing.
Fig. 6 is the process flow diagram of the rapid thermal annealing method of semiconductor device in the present embodiment,
As shown in the figure, the rapid thermal annealing method of semiconductor device in the present embodiment may further comprise the steps:
Steps A 1: set up the ternary corresponding relation between device electrical parameter, annealing temperature and the STI pattern distribution density, and, set up the binary corresponding relation of device electrical parameter and gate pattern length.
Steps A 2: the difference that obtains the STI pattern distribution density of specific region and target area.
Steps A 3: the electrical parameter difference that finds the difference correspondence of described STI pattern distribution density according to described ternary corresponding relation.
Steps A 4: the difference of gate pattern length that finds the difference correspondence of described electrical parameter according to described binary corresponding relation.
Steps A 5: the gate pattern length of adjusting the specific region by the difference of described gate pattern length.
Steps A 6: utilize adjusted gate pattern to make the grid of semiconductor device specific region.In this step, make mask by comprising adjusted gate pattern at interior circuit pattern earlier, the design transfer of passing through then to expose mask arrives photoresist layer or hard mask layer, forms grid by etching at last.
Steps A 7: obtain the target annealing temperature of the STI pattern distribution density correspondence of described target area by described ternary corresponding relation, utilize this annealing temperature that semiconductor device is carried out annealing in process, reach the target electrical parameter.
Wherein, the ternary corresponding relation between described device electrical parameter, annealing temperature and the STI pattern distribution density is a linear relationship.The binary corresponding relation of described device electrical parameter and gate pattern length is a linear relationship.
The method for designing that the RTA method of present embodiment is actually by the circuit pattern of previous embodiment obtains making semiconductor device by circuit pattern after the circuit pattern, utilizes the target annealing temperature to carry out the process of RTA again.Therefore, steps A 1～A5 is all similar to last embodiment in the present embodiment, does not repeat them here.
The RTA method that adopts present embodiment to provide, adjust the length of the gate pattern of specific region in the circuit pattern design phase, so that the electrical parameter value in this specific region is near the target electrical parameter, remedy unevenness by the distribution density of STI pattern in the entire circuit pattern, make mask by the circuit pattern that obtains like this, and then utilize above-mentioned mask to make semiconductor device, improve the temperature homogeneity of RTA technology, thereby obtain the homogeneity of excellent electrical property parameter, and avoid using virtual architecture.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.In other embodiments of the invention, described electrical parameter can also be other electrical parameters of semiconductor devices such as threshold voltage.Active area described in the embodiment for example is the source region and the drain region of MOS device.
Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (10)
1. the method for designing of a circuit pattern is characterized in that, may further comprise the steps:
Set up the ternary corresponding relation between device electrical parameter, annealing temperature and the STI pattern distribution density, and, the binary corresponding relation of device electrical parameter and gate pattern length set up;
Obtain the difference of the STI pattern distribution density of specific region and target area;
Find the electrical parameter difference of the difference correspondence of described STI pattern distribution density according to described ternary corresponding relation;
Find the difference of gate pattern length of the difference correspondence of described electrical parameter according to described binary corresponding relation;
Adjust the gate pattern length of specific region by the difference of described gate pattern length.
2. the method for designing of circuit pattern according to claim 1 is characterized in that, the difference of the STI pattern distribution density of described acquisition specific region and target area may further comprise the steps:
Obtain the STI pattern distribution density D of target area
0
Obtain the STI pattern distribution density D of specific region
x
Calculate described D
xWith D
0Difference.
3. the method for designing of circuit pattern according to claim 2 is characterized in that, the STI pattern distribution density D of described acquisition target area
0May further comprise the steps:
Determine the target electrical parameter according to the designing requirement of semiconductor device;
By the ternary corresponding relation of described device electrical parameter, annealing temperature and STI pattern distribution density, find the pairing STI pattern distribution of target electrical parameter density, also be the STI pattern distribution density D of described target area
0
4. the method for designing of circuit pattern according to claim 2 is characterized in that, the STI pattern distribution density D of described acquisition specific region
xMay further comprise the steps:
Circuit pattern is divided into the zone of a plurality of repetitions;
Detect each regional active area pattern distribution density A respectively
xDistribution density P with gate pattern
x
According to formula D
x=(1-A
x) * (1-P
x) calculate each regional STI pattern distribution density;
Judge whether each regional STI pattern distribution density equals target area STI pattern distribution density; If not, then should the zone as described specific region.
5. according to the method for designing of each described circuit pattern of claim 1～4, it is characterized in that described specific region is the virtual architecture sensitizing range.
6. according to the method for designing of each described circuit pattern of claim 1～4, it is characterized in that described electrical parameter comprises saturation current or threshold voltage.
7. according to the method for designing of each described circuit pattern of claim 1～4, it is characterized in that the ternary corresponding relation between described device electrical parameter, annealing temperature and the STI distribution density is a linear relationship.
8. according to the method for designing of each described circuit pattern of claim 1～4, it is characterized in that the binary corresponding relation of described device electrical parameter and gate pattern length is a linear relationship.
9. the rapid thermal annealing method of a semiconductor device is characterized in that, may further comprise the steps:
Set up the ternary corresponding relation between device electrical parameter, annealing temperature and the STI pattern distribution density, and, the binary corresponding relation of device electrical parameter and gate pattern length set up;
Obtain the difference of the STI pattern distribution density of specific region and target area;
Find the electrical parameter difference of the difference correspondence of described STI pattern distribution density according to described ternary corresponding relation;
Find the difference of gate pattern length of the difference correspondence of described electrical parameter according to described binary corresponding relation;
Adjust the gate pattern length of specific region by the difference of described gate pattern length;
Utilize adjusted gate pattern to make the grid of semiconductor device specific region;
Obtain the target annealing temperature of the STI pattern distribution density correspondence of described target area by described ternary corresponding relation, utilize this annealing temperature that semiconductor device is carried out annealing in process, reach the target electrical parameter.
10. method according to claim 9 is characterized in that, the ternary corresponding relation between described device electrical parameter, annealing temperature and the STI pattern distribution density is a linear relationship.
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| CN2009101968926A CN102033971B (en) | 2009-09-29 | 2009-09-29 | Design method of circuit patterns and rapid thermal annealing method of semiconductor device |
| US12/877,877 US8392863B2 (en) | 2009-09-29 | 2010-09-08 | Method for circuit layout and rapid thermal annealing method for semiconductor apparatus |
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| CN2009101968926A CN102033971B (en) | 2009-09-29 | 2009-09-29 | Design method of circuit patterns and rapid thermal annealing method of semiconductor device |
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| CN102033971B CN102033971B (en) | 2012-12-26 |
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| CN113138527A (en) * | 2020-01-16 | 2021-07-20 | 中芯国际集成电路制造(上海)有限公司 | Mask, storage unit and SRAM device |
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| CN104915528B (en) * | 2015-07-15 | 2018-07-03 | 中国科学院微电子研究所 | Layout design method, layout design system and the production method of integrated circuit |
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| US6194285B1 (en) * | 1999-10-04 | 2001-02-27 | Taiwan Semiconductor Manufacturing Company | Formation of shallow trench isolation (STI) |
| CN1206724C (en) * | 2002-01-09 | 2005-06-15 | 中芯国际集成电路制造(上海)有限公司 | Method for mfg. mask type ROM in high density planar unit mode |
| KR100542395B1 (en) * | 2003-11-13 | 2006-01-11 | 주식회사 하이닉스반도체 | Method of manufacturing a NAND flash device |
| KR100621621B1 (en) * | 2003-12-19 | 2006-09-13 | 삼성전자주식회사 | Nonvolatile Memory Device Having Self-Aligned Gate Conductive Layer And Method Of Fabricating The Same |
| US7537941B2 (en) | 2006-06-07 | 2009-05-26 | International Business Machines Corporation | Variable overlap of dummy shapes for improved rapid thermal anneal uniformity |
| US7971158B2 (en) * | 2008-06-23 | 2011-06-28 | International Business Machines Corporation | Spacer fill structure, method and design structure for reducing device variation |
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| CN113138527A (en) * | 2020-01-16 | 2021-07-20 | 中芯国际集成电路制造(上海)有限公司 | Mask, storage unit and SRAM device |
| CN113138527B (en) * | 2020-01-16 | 2024-04-02 | 中芯国际集成电路制造(上海)有限公司 | Mask, memory cell and SRAM device |
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| Publication number | Publication date |
|---|---|
| CN102033971B (en) | 2012-12-26 |
| US8392863B2 (en) | 2013-03-05 |
| US20110078647A1 (en) | 2011-03-31 |
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