CN104915528B - Layout design method, layout design system and the production method of integrated circuit - Google Patents
Layout design method, layout design system and the production method of integrated circuit Download PDFInfo
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Abstract
The invention discloses a kind of layout design method of integrated circuit, layout design system and production method, including：The original dimension of the initial primary topology of integrated design circuit and each transistor of integrated circuit and, obtain the default value range of the relevant parameter of the domain effect of each transistor of integrated circuit；The original dimension of initial primary topology, each transistor to integrated circuit and the default value range of the domain effect relevant parameter of each transistor emulate before carrying out, to obtain the target layout design parameter for meeting default yield, target layout design parameter includes the target size of the target topology of integrated circuit and each transistor of integrated circuit, and the target value of the relevant parameter of the domain effect of each transistor of integrated circuit；According to target layout design parameter, design meets the target domain of the integrated circuit of default capabilities, ensure that the yield for making integrated circuit, the situation that design cycle when improving existing design domain is grown.
Description
Technical field
The present invention relates to technical field of integrated circuits, more specifically, are related to a kind of layout design side of integrated circuit
Method, layout design system and production method.
Background technology
Now, as the continuous of integrated circuit technique promotes to node technique, micron before transistor feature size also has
Grade rises to nanoscale.And further reducing due to transistor size, the characteristic of transistor in itself is by domain effect
The influence of (layout dependent effect) is more notable, such as is imitated by trap kindred effect and shallow trench isolation stress
The influence that should be waited, the making yield in turn resulting in integrated circuit are low.
Invention content
In view of this, the present invention provides a kind of layout design method of integrated circuit, layout design system and making sides
Method by during the layout design of integrated circuit, adding in the emulation of the relevant parameter of domain effect, obtains meeting default good
The target layout design parameter of rate, and then the target domain of the design integrated circuit according to target layout design parameter, with
Ensure follow-up making integrated circuit reaches expected yield.
To achieve the above object, technical solution provided by the invention is as follows：
A kind of layout design method of integrated circuit, including：
The initial ruler of each transistor of S1, the initial primary topology of the design integrated circuit and the integrated circuit
It is very little and, obtain the default value range of the relevant parameter of the domain effect of each transistor of the integrated circuit；
S2, the version to the initial primary topology of the integrated circuit, the original dimension of each transistor and each transistor
The default value range of figure effect relevant parameter emulates before carrying out, to obtain the target layout design parameter for meeting default yield,
The target layout design parameter includes the target topology of the integrated circuit and each transistor of the integrated circuit
Target size and, the target value of the relevant parameter of the domain effect of each transistor of the integrated circuit；
S3, according to the target layout design parameter, design meets the target domain of the integrated circuit of default capabilities.
Preferably, the default value range of the domain effect relevant parameter of each transistor to the integrated circuit
Emulation includes before carrying out：
Using machine learning method, to the default of the relevant parameter of the domain effect of each transistor of the integrated circuit
Numberical range is emulated, and carries out Monte Carlo statistical to multiple numerical value in the range of the default value of the relevant parameter
Analysis.
Preferably, the machine learning method is neural network algorithm or Gaussian process.
Preferably, the domain effect includes at least one of trap kindred effect and shallow trench isolation stress effect.
Preferably, the relevant parameter of the shallow trench isolation stress effect includes：The first boundary of gate regions to active area exists
The distance between first boundary of same direction SA, the gate regions the second boundary to the active area are the second of the same direction
The distance between two neighboring grid SD in the distance between boundary SB and the gate regions；
Wherein, the default value of the relevant parameter of the shallow trench isolation stress effect is ranging from：
SA=(1+ra) * SAO；
SB=(1+rb) * SBO；
SD=(1+rd) * SDO
Wherein, ra, rb and rd are that relevant parameter allows variation range, and SAO, SBO and SDO are the default of relevant parameter
Initial value.
Preferably, the step S3 includes：
S31, according to the target layout design parameter, design the initial domain of the integrated circuit；
S32, rule inspection and the comparison of domain schematic diagram are designed to the initial domain；
S33, the extraction initial domain and interconnection relevant parameter；
S34, post-simulation is carried out to the integrated circuit, judges whether the initial domain meets the default capabilities, if
It is that then the post-simulation terminates, and the initial domain is the target domain；If it is not, then enter step S35；
S35, judge whether the initial domain is unsatisfactory for the default capabilities within preset times, if so, returning
Step S31 redesigns the initial domain of the integrated circuit；If it is not, then return to step S1 redesigns the integrated circuit
The original dimension of each transistor of initial primary topology and the integrated circuit.
Correspondingly, the present invention also provides a kind of layout design system of integrated circuit, including：
Acquisition module, the acquisition module are used to design the initial primary topology of the integrated circuit and the integrated circuit
Each transistor original dimension and, obtain the relevant parameter of the domain effect of each transistor of the integrated circuit
Default value range；
Preceding emulation module, the preceding emulation module is for initial primary topology, each transistor to the integrated circuit
Original dimension and each transistor domain effect relevant parameter default value range carry out before emulate, it is pre- to obtain meeting
If the target layout design parameter of yield, the target topology of the target layout design parameter including the integrated circuit and
The target size of each transistor of the integrated circuit and, the domain effect of each transistor of the integrated circuit
The target value of relevant parameter；
And domain determining module, the domain determining module are used for according to the target layout design parameter, design is completely
The target domain of the integrated circuit of sufficient default capabilities.
Correspondingly, the present invention also provides a kind of production method of integrated circuit, the production method of the integrated circuit is adopted
With the target domain designed by the layout design method of above-mentioned integrated circuit, the integrated circuit is made.
Compared to the prior art, technical solution provided by the invention has at least the following advantages：
Layout design method, layout design system and the production method of a kind of integrated circuit provided by the invention, including：
The original dimension of each transistor of S1, the initial primary topology of the design integrated circuit and the integrated circuit and, obtain
Take the default value range of the relevant parameter of the domain effect of each transistor of the integrated circuit；S2, to the integrated electricity
The default value of the domain effect relevant parameter of the initial primary topology on road, the original dimension of each transistor and each transistor
Range emulates before carrying out, and to obtain the target layout design parameter for meeting default yield, the target layout design parameter includes
The target size of each transistor of the target topology of the integrated circuit and the integrated circuit and, it is described integrated
The target value of the relevant parameter of the domain effect of each transistor of circuit；S3, according to the target layout design parameter, if
Meter meets the target domain of the integrated circuit of default capabilities.
As shown in the above, technical solution provided by the invention, by during the layout design of integrated circuit, adding
Enter the emulation of the relevant parameter of domain effect, the target layout design parameter for meeting default yield is obtained, then according to target version
The guidance of G- Design parameter, design meet the target domain of the integrated circuit of default capabilities, to ensure follow-up making integrated circuit
Reach expected yield；In addition, before the target layout design (i.e. step S3) of integrated circuit, to the relevant parameter of domain effect
It is emulated, improves and the extension design period occur when considering domain effect during the design object domain (i.e. step S3)
Situation.
Description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention, for those of ordinary skill in the art, without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of flow chart of the layout design method of integrated circuit provided by the embodiments of the present application；
Fig. 2 is a kind of multiple transistor domains provided by the embodiments of the present application；
Fig. 3 is the flow chart of the layout design method of another integrated circuit provided by the embodiments of the present application；
Fig. 4 is a kind of structure diagram of the layout design system of integrated circuit provided by the embodiments of the present application.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without making creative work
Embodiment shall fall within the protection scope of the present invention.
As described in background, further reducing due to transistor size, the characteristic of transistor in itself is by domain
The influence of effect (layout dependent effect) is more notable, such as should by trap kindred effect and shallow trench isolation
The influence of stress effect etc., the making yield in turn resulting in integrated circuit are low.
Based on this, the embodiment of the present application provides a kind of layout design method of integrated circuit, passes through the version in integrated circuit
During G- Design, the emulation of the relevant parameter of domain effect is added in, obtains the target layout design parameter for meeting default yield,
And then the target domain of the design integrated circuit according to target layout design parameter, to ensure follow-up making integrated circuit
Reach expected yield.Specifically, with reference to shown in Fig. 1 and Fig. 3, to the layout design side of integrated circuit provided by the embodiments of the present application
Method is described in detail.
Wherein, refering to what is shown in Fig. 1, for a kind of flow of the layout design method of integrated circuit provided by the embodiments of the present application
Figure, layout design method include：
The original dimension of each transistor of S1, the initial primary topology of integrated design circuit and integrated circuit and, obtain
Take the default value range of the relevant parameter of the domain effect of each transistor of integrated circuit.
Specifically, before the domain of integrated design circuit, it is first determined the default yield of designed integrated circuit, then
The original dimension of the initial primary topology of integrated circuit and each transistor of integrated circuit is determined on the basis of default yield,
And determine the default value range of the relevant parameter of the domain effect of each transistor of integrated circuit.
Wherein, domain effect provided by the embodiments of the present application is included in trap kindred effect and shallow trench isolation stress effect
It is at least one.Wherein, the relevant parameter of trap kindred effect includes source region boundary to the distance on well region boundary；And shallow trench isolation
The relevant parameter of stress effect includes the first boundary of gate regions to distance of the active area between the first boundary of the same direction, grid
In polar region the second boundary to distance of the active area between the second boundary of the same direction and gate regions between two neighboring grid
Distance.
It illustrates by taking shallow trench isolation stress effect as an example, with specific reference to shown in Fig. 2, is carried for the embodiment of the present application below
A kind of multiple transistor domains supplied, wherein, the relevant parameter packet of shallow trench isolation stress effect provided by the embodiments of the present application
It includes：10 first boundary of gate regions to distance SA of the active area 20 between the first boundary of the same direction, 10 second side of gate regions
In boundary to distance SB of the active area 20 between the second boundary of the same direction and gate regions 10 between two neighboring grid 11
Distance SD；
Wherein, the default value of the relevant parameter of shallow trench isolation stress effect is ranging from：
SA=(1+ra) * SAO；
SB=(1+rb) * SBO；
SD=(1+rd) * SDO
Wherein, ra, rb and rd are that relevant parameter allows variation range, and SAO, SBO and SDO are the default of relevant parameter
Initial value.Wherein, the preset initial value of SAO, SBO and SDO provided by the embodiments of the present application can be determined according to design experiences
Or fixation is set as certain value；And the variation range of ra, rb and rd can be not less than -0.5 and no more than 0.5.
S2, it is emulated before being carried out to integrated circuit.
The original dimension of initial primary topology, each transistor to integrated circuit and the domain effect phase of each transistor
The default value range of related parameter emulates before carrying out, to obtain the target layout design parameter for meeting default yield, target domain
The target size of the target topology of design parameter including integrated circuit and each transistor of integrated circuit and, integrate
The target value of the relevant parameter of the domain effect of each transistor of circuit.
Wherein, the domain of the original dimension to the initial primary topology of integrated circuit, each transistor and each transistor
The default value range of effect relevant parameter emulates before carrying out, that is, adjustment determines the topological structure and transistor of integrated circuit
Size and, the numerical value of the domain effect relevant parameter of scan transistor, at the same to after adjustment all data carry out before imitate
Very, until obtaining meeting the target layout design parameter of default yield, i.e., until obtaining target topology, transistor
Until the target value of the relevant parameter of target size and the domain effect of transistor.
Specifically, the embodiment of the present application emulates before being carried out to the default value range of the domain effect relevant parameter of transistor
Including：Using machine learning method, to the default value model of the relevant parameter of the domain effect of each transistor of integrated circuit
It encloses and is emulated, and Monte Carlo statistical analysis is carried out to multiple numerical value in the range of the default value of relevant parameter.Optionally,
Machine learning method provided by the embodiments of the present application is neural network algorithm or Gaussian process；In addition, in other implementations of the application
In example, machine learning method may be the machine learning method different from the above-mentioned type.
The default value range of the relevant parameter of the domain effect to each transistor of integrated circuit is exemplified below
It is emulated：
Where it is assumed that integrated circuit includes m transistor, and each transistor includes n parameter, and m and n are not
Positive integer less than 1 then ties up scanning emulation for k=m*n；Wherein, discrete several numbers are taken to the numberical range of each parameter
Value, and can be to be scanned from minimum value to maximum value to the direction that the numerical value of each parameter scans.For example, with reference to Fig. 2 institutes
The multiple transistor domains shown, for some transistor, only consider the relevant parameter of its shallow trench isolation stress effect
SA and SB is then two-dimensional scan；Wherein, SA takes three numerical value, and SB takes five numerical value, and then multiple numerical value of SA and SB are carried out
Monte Carlo statistical analysis, to obtain the simulation result of yield.
S3, according to target layout design parameter, design meets the target domain of the integrated circuit of default capabilities.
Wherein, refering to what is shown in Fig. 3, the stream of the layout design method for another integrated circuit provided by the embodiments of the present application
Cheng Tu, wherein, step S3 provided by the embodiments of the present application includes：
S31, according to target layout design parameter, the initial domain of integrated design circuit；
S32, rule inspection and the comparison of domain schematic diagram are designed to initial domain；
S33, the initial domain of extraction and interconnection relevant parameter；
S34, post-simulation is carried out to integrated circuit, judges whether initial domain meets default capabilities, if so, post-simulation knot
Beam, and initial domain is target domain；If it is not, then enter step S35；
S35, judge whether initial domain is unsatisfactory for default capabilities within preset times, if so, return to step S31 weights
The initial domain of new integrated design circuit；If it is not, then return to step S1 redesigns the initial primary topology sum aggregate of integrated circuit
Into the original dimension of each transistor of circuit.
As shown in the above, the layout design method of integrated circuit provided by the embodiments of the present application, since step S2 is defeated
The target layout design parameter gone out carries yield information, therefore instructs subsequent design target version with the target layout design parameter
Figure, can be with the design process of optimization aim domain, and can integrally shorten the design cycle of target domain.
Correspondingly, the embodiment of the present application additionally provides a kind of layout design system of integrated circuit, refering to what is shown in Fig. 4, being
A kind of structure diagram of the layout design system of integrated circuit provided by the embodiments of the present application, wherein, layout design system packet
It includes：
Acquisition module 100, acquisition module is for the initial primary topology of integrated design circuit and each crystalline substance of integrated circuit
The original dimension of body pipe and, obtain the default value model of the relevant parameter of the domain effect of each transistor of integrated circuit
It encloses；
Preceding emulation module 200, preceding emulation module be used for the initial primary topology of integrated circuit, each transistor it is initial
The default value range of the domain effect relevant parameter of size and each transistor emulates before carrying out, to obtain meeting default yield
Target layout design parameter, the target topology of target layout design parameter including integrated circuit and integrated circuit it is each
The target size of transistor and, the target value of the relevant parameter of the domain effect of each transistor of integrated circuit；
And domain determining module 300, domain determining module are used for according to target layout design parameter, design meets pre-
If the target domain of the integrated circuit of performance.
Correspondingly, the embodiment of the present application additionally provides a kind of production method of integrated circuit, the production method of integrated circuit
Using the target domain designed by the layout design method of above-mentioned integrated circuit, integrated circuit is made.
Layout design method, layout design system and the production method of a kind of integrated circuit provided by the embodiments of the present application,
Including：The original dimension of each transistor of S1, the initial primary topology of the design integrated circuit and the integrated circuit, with
And obtain the default value range of the relevant parameter of the domain effect of each transistor of the integrated circuit；S2, to the collection
The original dimension of initial primary topology, each transistor into circuit and the domain effect relevant parameter of each transistor it is default
Numberical range emulates before carrying out, to obtain the target layout design parameter for meeting default yield, the target layout design parameter
The target size of each transistor of target topology and the integrated circuit including the integrated circuit and, it is described
The target value of the relevant parameter of the domain effect of each transistor of integrated circuit；S3, joined according to the target layout design
Number, design meet the target domain of the integrated circuit of default capabilities.
As shown in the above, technical solution provided by the embodiments of the present application passes through the layout design mistake in integrated circuit
Cheng Zhong adds in the emulation of the relevant parameter of domain effect, obtains the target layout design parameter for meeting default yield, then basis
The guidance of target layout design parameter, design meet the target domain of the integrated circuit of default capabilities, to ensure that follow-up make collects
Reach expected yield into circuit；In addition, before the target layout design (i.e. step S3) of integrated circuit, to the phase of domain effect
Related parameter is emulated, and improves and lengthening occurs when considering domain effect during the design object domain (i.e. step S3) and set
Count the situation in period.
The foregoing description of the disclosed embodiments enables professional and technical personnel in the field to realize or use the present invention.
A variety of modifications of these embodiments will be apparent for those skilled in the art, it is as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and the principles and novel features disclosed herein phase one
The most wide range caused.
Claims (6)
1. a kind of layout design method of integrated circuit, which is characterized in that including：
The original dimension of each transistor of S1, the initial primary topology of the design integrated circuit and the integrated circuit, with
And obtain the default value range of the relevant parameter of the domain effect of each transistor of the integrated circuit；Wherein, the version
Figure effect include at least one of trap kindred effect and shallow trench isolation stress effect and, the shallow trench isolation stress
The relevant parameter of effect includes：The first boundary of gate regions to distance SA of the active area between the first boundary of the same direction, institute
State phase in gate regions the second boundary to distance SB of the active area between the second boundary of the same direction and the gate regions
The distance between adjacent two grids SD；
Wherein, the default value of the relevant parameter of the shallow trench isolation stress effect is ranging from：
SA=(1+ra) * SAO；
SB=(1+rb) * SBO；
SD=(1+rd) * SDO
Wherein, ra, rb and rd are that relevant parameter allows variation range, and SAO, SBO and SDO are the default initial of relevant parameter
Numerical value；
S2, the domain of the initial primary topology of the integrated circuit, the original dimension of each transistor and each transistor is imitated
The default value range of relevant parameter is answered to be emulated before carrying out, it is described to obtain the target layout design parameter for meeting default yield
Target layout design parameter includes the mesh of the target topology of the integrated circuit and each transistor of the integrated circuit
Dimensioning and, the target value of the relevant parameter of the domain effect of each transistor of the integrated circuit；
S3, according to the target layout design parameter, design meets the target domain of the integrated circuit of default capabilities.
2. the layout design method of integrated circuit according to claim 1, which is characterized in that described to the integrated circuit
Each transistor domain effect relevant parameter default value range carry out before emulation include：
Using machine learning method, to the default value of the relevant parameter of the domain effect of each transistor of the integrated circuit
Range is emulated, and carries out Monte Carlo statistical analysis to multiple numerical value in the range of the default value of the relevant parameter.
3. the layout design method of integrated circuit according to claim 2, which is characterized in that the machine learning method is
Neural network algorithm or Gaussian process.
4. the layout design method of integrated circuit according to claim 1, which is characterized in that the step S3 includes：
S31, according to the target layout design parameter, design the initial domain of the integrated circuit；
S32, rule inspection and the comparison of domain schematic diagram are designed to the initial domain；
S33, the extraction initial domain and interconnection relevant parameter；
S34, post-simulation is carried out to the integrated circuit, judges whether the initial domain meets the default capabilities, if so,
The post-simulation terminates, and the initial domain is the target domain；If it is not, then enter step S35；
S35, judge whether the initial domain is unsatisfactory for the default capabilities within preset times, if so, return to step
S31 redesigns the initial domain of the integrated circuit；If it is not, then return to step S1 redesigns the initial of the integrated circuit
The original dimension of each transistor of topological structure and the integrated circuit.
5. a kind of layout design system of integrated circuit, which is characterized in that including：
Acquisition module, the acquisition module be used for design the integrated circuit initial primary topology and the integrated circuit it is every
The original dimension of a transistor and, obtain the domain effect of each transistor of the integrated circuit relevant parameter it is pre-
If numberical range；Wherein, the domain effect includes at least one of trap kindred effect and shallow trench isolation stress effect, with
And the relevant parameter of the shallow trench isolation stress effect includes：The first boundary of gate regions is to active area the of the same direction
The distance between one boundary SA, the gate regions the second boundary to the active area between the second boundary of the same direction away from
From the distance between two neighboring grid in SB and gate regions SD；
Wherein, the default value of the relevant parameter of the shallow trench isolation stress effect is ranging from：
SA=(1+ra) * SAO；
SB=(1+rb) * SBO；
SD=(1+rd) * SDO
Wherein, ra, rb and rd are that relevant parameter allows variation range, and SAO, SBO and SDO are the default initial of relevant parameter
Numerical value；
Preceding emulation module, the preceding emulation module be used for the initial primary topology of the integrated circuit, each transistor just
The default value range of the domain effect relevant parameter of beginning size and each transistor emulates before carrying out, default good to obtain meeting
The target layout design parameter of rate, the target topology of the target layout design parameter including the integrated circuit and described
The target size of each transistor of integrated circuit and, the correlation of the domain effect of each transistor of the integrated circuit
The target value of parameter；
And domain determining module, the domain determining module are used for according to the target layout design parameter, design meets pre-
If the target domain of the integrated circuit of performance.
6. a kind of production method of integrated circuit, which is characterized in that the production method of the integrated circuit using claim 1~
Target domain designed by the layout design method of integrated circuit described in 4 any one, makes the integrated circuit.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN109740277B (en) * | 2019-01-11 | 2023-10-27 | 中国科学院微电子研究所 | Integrated circuit layout design optimization method and system |
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| CN112149379A (en) * | 2020-08-14 | 2020-12-29 | 全芯智造技术有限公司 | Method and apparatus for simulating an integrated circuit and computer readable medium |
| CN112069750B (en) * | 2020-08-14 | 2024-06-14 | 上海华虹宏力半导体制造有限公司 | Layout verification method, device, equipment and storage medium |
| CN117321601A (en) * | 2021-06-23 | 2023-12-29 | 华为技术有限公司 | Layout generation method and device of integrated circuit |
| CN113239651B (en) * | 2021-07-12 | 2021-09-17 | 苏州贝克微电子有限公司 | Artificial intelligence implementation method and system for circuit design |
| CN114021505B (en) * | 2022-01-06 | 2022-05-17 | 青岛展诚科技有限公司 | Method and system for generating integrated circuit FinFET complex three-dimensional structure description file |
| CN114899187A (en) * | 2022-05-09 | 2022-08-12 | 成都海光微电子技术有限公司 | Layout design method, system and device, circuit layout and storage medium |
| CN115358178B (en) * | 2022-08-11 | 2023-04-07 | 山东大学 | Circuit yield analysis method based on fusion neural network |
| CN117272910B (en) * | 2023-11-22 | 2024-02-23 | 江山季丰电子科技有限公司 | Modularized design method and device for aging circuit board of integrated circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102955883A (en) * | 2012-11-12 | 2013-03-06 | 清华大学 | Field effect transistor model parameter correction method taking shallow trench isolation into account |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102033971B (en) * | 2009-09-29 | 2012-12-26 | 中芯国际集成电路制造(上海)有限公司 | Design method of circuit patterns and rapid thermal annealing method of semiconductor device |
-
2015
- 2015-07-15 CN CN201510416102.6A patent/CN104915528B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102955883A (en) * | 2012-11-12 | 2013-03-06 | 清华大学 | Field effect transistor model parameter correction method taking shallow trench isolation into account |
Non-Patent Citations (4)
| Title |
|---|
| 基于TIA/EIA-899的MLVDS驱动器关键技术的研究;曹成成;《中国优秀硕士学位论文全文数据库 信息科技辑》;20150415(第4期);第I135-101页 * |
| 深亚微米IP模块设计中必须考虑的制造工艺的影响;359705716;《http：//www.eetop.cn/blog/html/06/519906-28674.html》;20120702;第1-9页 * |
| 集成电路热载流子失效预警技术研究;王彬;《中国优秀硕士学位论文全文数据库 信息科技辑》;20150115(第1期);第I135-155页 * |
| 集成电路版图设计报告;shengshidadian;《https://wenku.baidu.com/view/c822a969561252d380eb6ecb.html》;20110727;第1-9页 * |
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