CN112069750B - Layout verification method, device, equipment and storage medium - Google Patents
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
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Abstract
The application discloses a verification method, a device, equipment and a storage medium of a layout, which comprise the following steps: measuring the pattern size of a parameter pattern in the layout, wherein the pattern size is obtained based on physical parameters, and the physical parameters are physical quantities obtained by simulating devices in the layout; calculating according to the size of the graph to obtain physical parameters; and verifying the layout according to the physical parameters. According to the application, the physical parameters are obtained by measuring the pattern sizes of the parameter patterns in the layout according to the pattern size calculation, and the layout is verified, and the pattern sizes are obtained by the physical quantities obtained by simulating devices in the layout, so that the problem that the accuracy of verifying the integrated circuit layout is low due to the fact that the accuracy of obtaining the physical parameters by measuring the pattern calculation of the devices is low in the related art is solved, and the accuracy of verifying the layout is improved.
Description
Technical Field
The present application relates to the field of integrated circuit manufacturing technologies, and in particular, to a layout verification method, device, apparatus, and storage medium.
Background
In the design process of integrated circuit layout, the layout of the device needs to be identified by utilizing an electronic design automation (electronic design automation, EDA) program, and the identified parameters are subjected to layout logic diagram verification (layout versus schematics, LVS) or design rule check (design rule check, DRC) to determine whether the layout is correct or not.
In the related art, when DRC or LVS is performed by EDA, identification of parameters, which may be the length and width of a channel of a transistor, the length and width of a resistor, and the like, is generally performed by using the geometry of a layout.
However, for physical parameters of devices (especially more complex devices), such as capacitance values, inductance values, and the like, it is difficult to obtain more correct physical parameters through graphic computation on the layout by the EDA program, so that the accuracy of verification of the integrated circuit layout is low.
Disclosure of Invention
The application provides a verification method, device, equipment and storage medium of a layout, which can solve the problem of lower accuracy of the verification method of non-geometric parameters in the layout provided in the related technology.
On one hand, the embodiment of the application provides a verification method of a layout, which is executed by EDA program and comprises the following steps:
Measuring the pattern size of a parameter pattern in the layout, wherein the pattern size is calculated based on physical parameters, and the physical parameters are values of physical quantities obtained by simulating devices in the layout;
Calculating according to the graph size to obtain the physical parameters;
and verifying the layout according to the physical parameters.
Optionally, for any physical parameter to be verified in the layout, there are at least two parameter graphs corresponding to one physical parameter.
Optionally, the parameter graph is a rectangle, the rectangle includes a first side and a second side that are perpendicular to each other, and the side length of the first side corresponds to the number split in the physical parameter.
Optionally, the set of side lengths of the first side of the parameter graph corresponds to a number before the decimal point and a number after the decimal point in the physical parameter.
Optionally, the set of side lengths of the second side of the parameter pattern includes a constant corresponding to each parameter pattern.
Optionally, the calculating the physical parameter according to the graph size includes:
For any physical parameter to be verified in the layout, calculating the area of each parameter graph corresponding to the physical parameter;
And adding the area of each parameter graph to the product of the weight value of each parameter graph to obtain the physical parameter.
Optionally, the side length of the second side is an integer multiple of the lattice point of the layout.
On the other hand, the embodiment of the application provides a verification device, which is used for verifying physical parameters to be verified in a layout through an EDA program, wherein the physical parameters are values of physical quantities obtained by simulating devices in the layout, and the device comprises:
The measuring module is used for measuring the pattern size of the parameter pattern in the layout, and the pattern size is calculated based on physical parameters;
the processing module is used for calculating the physical parameters according to the graph size; and verifying the layout according to the physical parameters.
In another aspect, an embodiment of the present application provides a computer device, where the device includes a processor and a memory, where the memory stores at least one instruction or program, where the instruction or program is loaded and executed by the processor to implement a method for verifying a layout as set forth in any one of the above.
In another aspect, an embodiment of the present application provides a computer readable storage medium, where at least one instruction or program is stored, where the instruction or program is loaded and executed by a processor to implement a method for verifying a layout as described in any one of the above.
The technical scheme of the application at least comprises the following advantages:
The physical parameters are obtained according to the figure size calculation by measuring the figure size of the parameter figures in the layout, and the layout is verified, and the figure size is obtained by the physical quantity obtained by simulating the devices in the layout, so that the problem that in the related art, the accuracy of verifying the integrated circuit layout is low due to the fact that the accuracy of obtaining the physical parameters through the figure calculation of the measured devices is low is solved, and the accuracy of verifying the layout is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method of verifying a layout provided by an exemplary embodiment of the present application;
FIG. 2 is a schematic diagram of a parameter graph provided by an exemplary embodiment of the present application;
FIG. 3 is a schematic diagram of splitting physical parameters provided by an exemplary embodiment of the present application;
FIG. 4 is a schematic diagram of a parameter graph matrix provided by an exemplary embodiment of the present application;
FIG. 5 is a block diagram of an authentication device provided by an exemplary embodiment of the present application;
FIG. 6 is a block diagram of a computer device provided in an exemplary embodiment of the application.
Detailed Description
The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
Referring to FIG. 1, which shows a flowchart of a method for verifying a layout provided by an exemplary embodiment of the present application, the method may be performed by a computer device via an EDA program, the method comprising:
step 101, measuring the pattern size of a parameter pattern in the layout, wherein the pattern size is calculated based on physical parameters, and the physical parameters are values of physical quantities obtained by simulating devices in the layout.
The layout comprises at least one physical quantity to be measured. For example, the layout comprises a device 1, and the physical quantity to be measured is the capacitance of the device 1; or the layout comprises a device 1 and a device 2, wherein the physical quantity to be measured is the capacitance of the device 1 and the inductance of the device 2; or the layout comprises a device 1 and a device 2, and the physical quantity to be measured is the capacitance and the inductance of the device 1; or the layout comprises a device 1 and a device 2, wherein the physical quantity to be measured is the capacitance and the inductance of the device 1, and the capacitance and the inductance of the device 2; or the layout comprises a device 1 and a device 2, wherein the physical quantity to be measured is the capacitance and inductance of the device 1, and the breakdown voltage of the device 2.
By way of example, the layout includes two types of devices, namely a memory cell device of a flash memory (hereinafter referred to as "flash memory") and a logic device, wherein the physical quantity to be measured in the memory cell device includes a capacitance of a metal interconnection structure, an inductance of the metal interconnection structure, a threshold voltage, a breakdown voltage, and the like, and the physical quantity to be measured in the logic device includes a capacitance of the metal interconnection structure, an inductance of the metal interconnection structure, a threshold voltage, a breakdown voltage, and the like.
The device in the layout is simulated, and physical parameters such as an inductance value, a threshold voltage value, a breakdown voltage value and the like of a metal interconnection structure of the memory cell device can be obtained, and a capacitance value, an inductance value, a threshold voltage value, a breakdown voltage value and the like of a metal interconnection structure of the logic device can be obtained. Based on the physical parameters obtained by the simulation, the graph size of the parameter graph which needs to be inserted into the layout can be calculated.
For example, when the capacitance value obtained by simulation is 1.2 picofarads (pF), the size of the parameter pattern corresponding to the capacitance value may be set to 1.2, for example, it may be a square with a side length of 1.2 micrometers, a rectangle with a side length of 1.2 micrometers, a circle with a radius or diameter of 1.2 micrometers, a rectangle with a major axis or a minor axis of 1.2 micrometers, and if there is a limit to the size of the pattern, the pattern may be scaled down or enlarged.
Correspondingly, in the above example, if the parameter pattern is square, the side length of the parameter pattern is measured to be 1.2 micrometers; if the parameter graph is rectangular, measuring to obtain that the side length of the side, which is used for being related to the physical parameter, in the parameter graph is 1.2 micrometers; if the parameter pattern is circular, measuring to obtain the radius or diameter of the parameter pattern to be 1.2 micrometers; if the parameter pattern is elliptical, the major or minor axis of the parameter pattern is measured to be 1.2 microns.
And 102, calculating to obtain physical parameters according to the size of the graph.
And after the parameter graph is measured to obtain the corresponding graph size, the physical parameter can be obtained according to the graph size calculation. For example, in the above example, if the parameter pattern is square, the pattern size related to the physical parameter in the parameter pattern is a side length, the side length of the parameter pattern is measured to be 1.2 micrometers, and the physical parameter corresponding to the parameter pattern is the capacitance value of the interconnection structure, the capacitance value of the interconnection structure is determined to be 1.2 picofarads; if the parameter graph is square, the graph size related to the physical parameter in the parameter graph is the side length, the side length of the parameter graph is measured to be 0.0012 micrometers, the physical parameter corresponding to the parameter graph is the capacitance value of the interconnection structure, the graph size is the reduced size, the reduction ratio is 1000, and the graph size is multiplied by the reduction ratio (0.0012 multiplied by 1000=1.2), so that the capacitance value of the interconnection structure is 1.2 picofarads.
And step 103, verifying the layout according to the physical parameters.
For example, in the above example, the capacitance of the interconnect structure is calculated to be 1.2 picofarads, and then whether the capacitance value meets LVS or DRC is detected, so as to implement verification of the physical parameter.
Optionally, in an embodiment of the present application, at least one of a capacitance, a resistance, an inductance, a voltage, and a current of a physical quantity to be measured, and the physical parameter to be verified includes at least one of a capacitance value, a resistance value, an inductance value, a voltage value, and a current value.
In summary, in the embodiment of the application, the physical parameters are obtained by measuring the pattern size of the parameter pattern in the layout according to the pattern size calculation to verify the layout, and the pattern size is obtained by the physical quantity obtained by simulating the devices in the layout, so that the problem that the accuracy of verifying the integrated circuit layout is low due to the fact that the accuracy of obtaining the physical parameters by measuring the pattern calculation of the devices in the related art is low is solved, and the accuracy of verifying the layout is improved.
In an alternative embodiment, for any physical parameter in the layout that needs to be verified, there are at least two parameter graphs corresponding to one physical parameter, and the graph size of each parameter graph corresponds to the number split among the physical parameters.
If the physical parameter is complex and is difficult to embody in one parameter graph, the physical parameter can be split, and two or more parameter graphs are used for corresponding to the physical parameter.
For example, the physical parameters to be verified include a capacitance value, which is 13.14 picofarads, and the capacitance value can be divided into a parameter pattern with a pattern size of 13 micrometers corresponding to 13.14 (for example, a square with a side length of 13 micrometers, a circle with a radius or a diameter of 13 micrometers, an ellipse with a major axis or a minor axis of 13 micrometers, etc.) and a parameter pattern with a pattern size of 14 micrometers (for example, a square with a side length of 14 micrometers, a circle with a radius or a diameter of 14 micrometers, an ellipse with a major axis or a minor axis of 14 micrometers, etc.), corresponding to which, when the computer device obtains the pattern sizes of the two parameter patterns through EDA program measurement, the capacitance value can be calculated according to the corresponding coefficients of the two pattern sizes (the corresponding coefficient with a coefficient of 1,0.14 corresponding to the coefficient of 100).
In an alternative embodiment, the parameter patterns are rectangles, the rectangles comprise a first side and a second side which are perpendicular to each other, for any physical parameter to be verified in the layout, there are at least two parameter patterns corresponding to one physical parameter, and the side length of the first side of each parameter pattern corresponds to the number split in the physical parameter.
Referring to fig. 2, a schematic diagram of a parameter graph provided by an exemplary embodiment of the present application is shown. Illustratively, as shown in fig. 2, the parameter graph 200 is rectangular, and includes a first side a and a second side b perpendicular to each other, where a side length C x of the first side a corresponds to the number of the split physical parameters. Illustratively, the physical parameters in the layout that need to be verified include at least two reference patterns 200 shown in FIG. 2.
Optionally, in the embodiment of the present application, the set formed by the side lengths of the first edge of the parameter graph corresponds to a number before the decimal point and a number after the decimal point of the physical parameter. For example, the physical parameter is a capacitance value of 13.14 picofarads, the capacitance value corresponds to two reference patterns as shown in fig. 2, and the set of side lengths of the first sides of the two reference patterns is { C 1,C2 }, where C 1 corresponds to 13 before the decimal point and C 2 corresponds to 0.14 after the decimal point.
Optionally, referring to fig. 2, in an embodiment of the present application, the set of the side lengths W x of the second side of the parameter patterns includes a constant corresponding to each parameter pattern. As described above, in the application, the pattern size of the parameter pattern needs to be reduced or enlarged, and the constant corresponds to the reduced or enlarged value. For example, the physical parameter is a capacitance value of 24.14 picofarads, the capacitance value corresponds to two reference patterns as shown in fig. 2, the set of side lengths of the first edges of the two reference patterns is { C 1,C2 }, where C 1 is 3, which corresponds to the number 24 before the decimal point, C 2 is 14, which corresponds to the number 0.14 after the decimal point, the set of side lengths of the first edges of the two reference patterns is { W 1,W2 }, where W 1 is 8, which corresponds to the reduced value of the number 24 before the decimal point, and W 2 is 100, which corresponds to the value amplified by the number 0.14 after the decimal point. Optionally, the side length of the second side is an integer multiple of the lattice point of the layout.
Optionally, in the embodiment of the present application, in step 102, "calculating the physical parameter according to the graphic size" includes, but is not limited to: for any physical parameter to be verified in the layout, calculating the area of each parameter graph corresponding to the physical parameter; and adding the area of each parameter graph to the product of the weight value of each parameter graph to obtain the physical parameter.
By way of example, the physical parameters may be calculated by:
wherein P is a physical parameter, n is the number of parameter graphs corresponding to the physical parameter P, x is the serial number of any parameter graph in the n parameter graphs, M x is the weight corresponding to the xth parameter graph, and S x is the area of the xth parameter graph.
Optionally, the product of the constant corresponding to the parameter pattern and the weight value thereof is a reduced or amplified value of the corresponding number. For example, if the parameter pattern is a rectangle having a side length of a first side of C x and a side length of a second side of W x and the corresponding weight value is M x, W x·Mx is a reduced or enlarged value of the number corresponding to the parameter pattern.
The solution of the present application will be described in an exemplary embodiment:
Referring to fig. 3, a schematic diagram of splitting physical parameters in a verification method of a layout according to an exemplary embodiment of the present application is shown. As shown in fig. 3, in this embodiment, the physical parameter C t is the capacitance value of the interconnect structure, C t = 159.1432 picofarads.
159.1432 Can be split into four groups of numbers including the numbers 100 and 59 before the decimal point and the numbers 0.14 and 0.0032 after the decimal point, the numbers before the decimal point obtained by splitting can be reduced or amplified to a certain extent to adapt to the lattice limit of the layout, for example, 100 can be divided by 10000 to obtain C i2 =0.01, 59 can be divided by 100 to obtain C i1 =0.59, C p2 =0.14 can be obtained, and the number 0.0032 can be multiplied by 100 to obtain C p1 =0.32. Through the splitting mode, the C t can be split into four numbers C i2、Ci1、Cp2, C p1,Ci2 and C i1 which respectively correspond to the numbers 1 and 59 before the decimal point, and the numbers C p2 and C p1 which respectively correspond to the numbers 0.14 and 0.0032 after the decimal point.
Referring to fig. 4, which shows a schematic diagram of a parameter pattern formed according to the number split by the physical parameter C t, as shown in fig. 4, the parameter patterns forming the resulting rectangle are a parameter pattern 201, a parameter pattern 202, a parameter pattern 203, and a parameter pattern 204, respectively. Wherein, the side lengths of the first sides a1, a2, a3 and a4 of the parameter graph 201, the parameter graph 202, the parameter graph 203 and the parameter graph 204 are C p1、Cp2、Ci1 and C i2 (the unit can be micrometer or nanometer); the side lengths of the second sides b1, b2, b3, and b4 of the parameter pattern 201, the parameter pattern 202, the parameter pattern 203, and the parameter pattern 204 are 0.005, 0.5, 0.005, and 0.5 (the unit may be micrometers or nanometers), respectively, which are predetermined constants.
According to the above embodiment, after the computer device measures the pattern sizes (i.e., the side lengths of the first side and the second side of each parameter pattern) of the parameter pattern 201, the parameter pattern 202, the parameter pattern 203, and the parameter pattern 204, the area of each parameter pattern is calculated, and the physical parameter is calculated according to the area of each parameter pattern and the weight corresponding to each parameter pattern, which may be specifically calculated by:
Ct＝(Ci2×0.5+Ci1×0.005)×20000+(Cp2×0.5+Cp1×0.005)×2
it will be readily seen that in this embodiment, the product of the side length and the weight of the second side is equal to the scaled down or scaled up value of the number of physical parameter splits.
Referring to fig. 5, there is shown a block diagram of a verification apparatus provided in an exemplary embodiment of the present application, the apparatus being configured to perform a verification method of any one of the layouts described above by means of an EDA program, the apparatus comprising:
A measurement module 501 for performing the steps of step 101 and other implicit measuring steps.
A processing module 502 for performing steps 102 and 103, as well as other implicit processing and/or computing steps.
Referring to FIG. 6, a block diagram of a computer device is shown provided in accordance with an exemplary embodiment of the present application. The apparatus includes: a processor 601 and a memory 602.
The processor 601 may be a central processor (central processing unit, CPU), a network processor (network processor, NP) or a combination of CPU and NP. The processor 601 may further comprise a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (comple 6 programmable logic device, CPLD), a field-programmable gate array (FPGA) GATE ARRAY, generic array logic (GENERIC ARRAY logic, GAL), or any combination thereof.
The memory 602 is connected to the processor 601 through a bus or other manner, and at least one instruction, at least one program, a code set, or an instruction set is stored in the memory 602, and the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by the processor 601 to implement the verification method of the layout provided in the above embodiment. The memory 602 may be volatile memory (volatile memory), non-volatile memory (non-volatile memory), or a combination thereof. The volatile memory may be a random-access memory (RAM), such as a static random-access memory (static random access memory, SRAM), a dynamic random-access memory (dynamic random access memory, DRAM). The non-volatile memory may be a read-only memory (read only memory image, ROM), such as a programmable read-only memory (programmable read only memory, PROM), an erasable programmable read-only memory (erasable programmable read only memory, EPROM), an electrically erasable programmable read-only memory (ELECTRICALLY ERASABLE PROGRAMMABLE READ-only memory, EEPROM). The nonvolatile memory may also be a flash memory (flash memory), a magnetic memory such as a magnetic tape (MAGNETIC TAPE), a floppy disk (floppy disk), or a hard disk. The non-volatile memory may also be an optical disc.
The present application also provides a computer readable storage medium having stored therein at least one instruction, at least one program, a set of codes or a set of instructions, the at least one instruction, the at least one program, the set of codes or the set of instructions being loaded and executed by the processor to implement a method of verifying a layout as described in any one of the embodiments above.
The application also provides a computer program product which, when run on a computer, causes the computer to execute the verification method of the layout provided by the method embodiments.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the application.
Claims (10)
1. A method of verifying a layout, the method being performed by an EDA program, comprising:
measuring the pattern size of a parameter pattern in the layout, wherein the pattern size is calculated based on physical parameters, the physical parameters are values of physical quantities obtained by simulating devices in the layout, and the physical parameters comprise at least one of capacitance values, resistance values, inductance values, voltage values and current values;
Calculating according to the graph size to obtain the physical parameters;
and verifying the layout according to the physical parameters.
2. A method according to claim 1, wherein for any physical parameter in the layout that needs to be verified, there are at least two of the parameter patterns for one physical parameter.
3. The method of claim 2, wherein the parameter pattern is a rectangle, the rectangle including a first side and a second side perpendicular to each other, the side length of the first side corresponding to the number of splits in the physical parameter.
4. A method according to claim 3, wherein the set of side lengths of the first side of the parameter pattern corresponds to a number preceding a decimal point and a number following a decimal point in the physical parameter.
5. The method of claim 4, wherein the set of side lengths of the second side of the parameter pattern comprises a corresponding constant for each of the parameter patterns.
6. The method of claim 5, wherein said calculating said physical parameter from said graphic size comprises:
For any physical parameter to be verified in the layout, calculating the area of each parameter graph corresponding to the physical parameter;
And adding the area of each parameter graph to the product of the weight value of each parameter graph to obtain the physical parameter.
7. The method of claim 4, wherein the side length of the second side is an integer multiple of a lattice point of the layout.
8. A verification apparatus, wherein the apparatus is configured to verify, by means of an EDA program, a physical parameter to be verified in a layout, the physical parameter being a value of a physical quantity obtained by simulating a device in the layout, the apparatus comprising:
The measuring module is used for measuring the pattern size of the parameter pattern in the layout, wherein the pattern size is calculated based on physical parameters, and the physical parameters comprise at least one of a capacitance value, a resistance value, an inductance value, a voltage value and a current value;
the processing module is used for calculating the physical parameters according to the graph size; and verifying the layout according to the physical parameters.
9. A computer device, characterized in that it comprises a processor and a memory in which at least one instruction or program is stored, which is loaded and executed by the processor to implement a method of verifying a layout according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that at least one instruction or program is stored in the storage medium, which is loaded and executed by a processor to implement a method of verifying a layout according to any one of claims 1 to 7.
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| CN101464916A (en) * | 2007-12-21 | 2009-06-24 | 北京中电华大电子设计有限责任公司 | Device attribute computing method for integrated circuit layout |
| CN109145414A (en) * | 2018-08-06 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | A kind of method and system improving post-layout simulation results exhibit accuracy |
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