JP2004086318A - Device for generating equivalent circuit model for simulation, circuit simulation system, method for generating equivalent circuit model for simulation, control program, and readable recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve accuracy of signal delay simulation also considering a wiring capacity between a dummy pattern and signal wiring in examining circuit operation. <P>SOLUTION: A layout processing means 261 arranges the dummy pattern which does not function as a circuit in layout design processing data. A load information extracting means 262 extracts load information existing between the dummy pattern, and other wiring arranged in the periphery and a conductor and semiconductor of a substrate. A load information providing means 263 provides load information existing in a periphery of the extracted dummy pattern to a connection node corresponding to circuit connection information. A potential information adding means 264 adds information indicating a power supply potential or a ground potential to a node corresponding to a connection point of the dummy pattern among the provided load information. A circuit simulation device 3 executes the signal delay simulation by using the equivalent circuit model for simulation considering the dummy pattern obtained in the above way. <P>COPYRIGHT: (C)2004,JPO

Description

次に、この電位分布Φを用いて図３（ａ）のガウス数値積分公式（数１；ガウスの定理）により導体Ａ，Ｂ表面の電荷量Ｑを計算し（電荷量算出処理）、電荷量Ｑと電位差（Ｖ１−Ｖ２）の関係より配線容量Ｃを求める。同様に、信号配線と信号配線間および、信号配線と基板間などについても配線容量を求める（容量値算出処理）。
【００６６】
これらの計算方法を用いてステップＳ３でダミーパターンＤＰと信号配線間、信号配線と信号配線間および信号配線と基板間の配線容量を求める。即ち、このステップＳ３ではデータとしてプロセス層間構造情報を入力とし、配線容量値を出力とする。
（ダミーパターンＤＰを考慮した等価回路モデル作成処理；負荷情報付与処理）上記ステップＳ３の配線容量計算処理で求めたダミーパターンＤＰと信号配線間、信号配線と信号配線間、信号配線と基板間の負荷情報としての各配線容量を設計回路図データ（ステップＳ１；回路を構成するトランジスタや基本素子の接続関係を記述したデータ）にマージ（合併、融合）させて、シミュレーション用等価回路モデルを作成する（負荷情報付与処理）。図４（ａ）〜図４（ｄ）にその考え方を具体例としてタイプ２の信号遅延回路（メタル第２層Ｍ２が信号配線層のケース）の場合で示している。
【００６７】
図４（ａ）では、図１１の信号配線回路（タイプ２の信号遅延回路；メタル第２層が信号配線）と同等の回路レイアウトの平面図を示している。図４（ａ）の回路レイアウトから、基本論理ゲートＡ，Ｂ間を接続する信号配線をその配線抵抗Ｒｉｎｔと配線容量Ｃｉｎｔで置きかえることにより図４（ｂ）の等価回路モデルを得ている。
【００６８】
この場合の配線抵抗については物理式Ｒｉｎｔ＝ρ＊（Ｌｉｎｔ／Ｗｉｎｔ）（ρ；メタル材料のシート抵抗値、Ｌｉｎｔ：信号配線長、Ｗｉｎｔ：信号配線幅）で計算する。
【００６９】
また、配線容量Ｃｉｎｔについては、図４（ｃ）の信号配線のＸ−Ｘ’断面に対応して上記配線容量計算処理で求めたダミーパターンＤＰと信号配線間容量間、信号配線と信号配線間および、信号配線と基板間の配線容量を用いて図４（ｃ）の等価回路モデルを作成する。より詳しくは、配線容量Ｃｉｎｔについては、図４（ｃ）に示した信号配線の断面に対応した各配線容量が回路動作に及ぼす影響を正確にシミュレーションするため、図４（ｄ）に示すように、ステップＳ４で、Ｍ２層信号配線とＭ２層信号配線間（Ｃｐ２２，Ｃｐ２３）、Ｍ３層ダミーパターンとＭ１層ダミーパターン間（Ｃ３１）、Ｍ３層ダミーパターンと基板間（Ｃ３）、Ｍ１層ダミーパターンと基板間（Ｃ１）、Ｍ３層ダミーパターンとＭ２層信号配線間（Ｃｔ，Ｃｔ’）、Ｍ１層ダミーパターンとＭ２層信号配線間（Ｃｂ，Ｃｂ’）などの全ての配線容量を含むシミュレーション用等価回路モデルを作成する。つまり、このステップＳ４では、データとしてステップＳ１の設計回路図データとステップＳ３の配線容量値データとを入力とし、図４（ｄ）のシミュレーション用等価回路モデルを出力とする。
（ダミーパターンＤＰに対する電圧設定処理；電位情報付加処理）
ダミーパターンＤＰを用いる最近の微細加工の多層配線プロセスでは、一般的に信号配線幅は０．５ｕｍ以下であるのに対して、ダミーパターンＤＰのサイズは１０ｕｍ×１０ｕｍ以上と非常に大きい。このことから半導体チップ上に配置されたダミーパターンＤＰを実質的に平行板と見なすことができる。これら平行板の配線容量は（上下の異層へ向かう）底面成分が支配的であり、同層へ向かう側面成分はそれに比べて小さく約１／１０以下である。言い換えると、ダミーパターンＤＰは同層にある他の信号配線などに及ぼす影響は小さいが、上下の異層にある信号配線などに及ぼす影響は大きく、信号配線をシールドする効果を持っている。即ち、図７でも説明したように、電源／グランド面と等価と見なすことができる。これは、文献『「ＶＬＳＩシステム設計」回路と実装の基礎　第４章』または、文献”ＡＳＨＯＫＫ．　ＧＯＥＬ，’Ｈｉｇｈ−Ｓｐｅｅｄ　ＶＬＳＩ　Ｉｎｔｅｒｃｏｎｎｅｃｔｉｏｎｓ：　Ｍｏｄｅｌｉｎｇ，Ａｎａｌｙｓｉｓ　ａｎｄ　Ｓｉｍｕｌａｔｉｏｎ’，ＷＩＬＥＹ−ＩＮＴＥＲＳＣＩＥＮＣＥＰＵＢＬＩＣＡＴＩＯＮ，１９９４”などに詳しく記載されている。このことを利用して上記処理で作成したシミュレーション用等価回路モデルの各ダミーパターンに対応する全ノード（図４（ｄ）の斜線の○印）についてその電圧を電源電圧値Ｖｄｄまたはグランド電圧レベル（０Ｖ）の何れかに固定する。どちらに固定しても信号遅延の回路シミュレーション結果は同じであるので（シミュレーション結果に影響なし）、通常、取り扱い易いグランド電圧レベル（０Ｖ）に固定する。
【００７０】
さらに繰り返して説明するが、ダミーパターンＤＰは周囲を全て層間絶縁膜で囲まれているフローティング状態であるため、上記等価回路モデル作成処理（図２のステップＳ４）で作成した等価回路モデルにおいてダミーパターンＤＰに対応するノード（図４（ｄ）の斜線の○印）には配線容量のみが接続されている。前述のようにダミーパターンＤＰは図７で前述したように平行板として信号配線をシールドする効果を持っているので、ダミーパターンＤＰを電源／グランド面と見なし、各ダミーパターンＤＰに対応するこれらノードを電源／グランドと同一電位に固定する。具体的には、上記ステップＳ４で生成されたシミュレーション用等価回路モデルに対して、電源名（通常はＶｄｄ）またはグランド名（通常はＧＮＤ）をこれらノードに名前として与える（電位情報付加処理）。また、ダミーパターンＤＰを電源と見なした場合とグランドと見なした場合とで信号遅延の回路シミュレーション結果は変わらないので（シミュレーション結果は同じで影響なしである）、ここでは取り扱い易いグランド０Ｖを設定する（図２のステップＳ５）。即ち、このステップＳ５の電位情報付加処理では、ステップＳ４で生成されたシミュレーション用等価回路モデルに対して電源名またはグランド名を付加する。
（信号遅延シミュレーション処理；信号遅延時間計算処理）
上記処理で作成したシミュレーション用等価回路モデルとダミーパターンＤＰに対する設定電圧を用いて、回路シミュレータによる直流解析（バイアス点を求める）と過渡解析（回路動作の時間応答）を行う。その結果得られた回路動作を示す波形グラフ（回路の入出力、内部ノードの電圧の時間変化）から注目する信号についてその信号遅延時間を求める。
【００７１】
即ち、前述のステップＳ４の等価回路モデル作成処理で作成した等価回路モデル（図４（ｄ））と前述のステップＳ５のダミーパターンＤＰの電圧設定処理によるダミーパターンＤＰの設定電圧を用いて、回路シミュレーション（直流解析、過渡解析）を実行する（ステップＳ６）。ステップＳ６の実行後に得られた回路動作を示す波形グラフ（回路の入出力、内部ノードの電圧の時間変化）から信号遅延時間を求める（ステップＳ７）。
【００７２】
本実施形態として、上記タイプ１，２の信号遅延回路について実際に製造した信号遅延回路の各信号配線層の信号遅延における実測値と本発明のシミュレーション値Ｓｉｍとの比較結果を図５に示している。図５において、ダミーパターンＤＰを考慮したことにより実測値とシミュレーション値Ｓｉｍとがほぼ一致していることが判る（シミュレーション値Ｓｉｍと実測値の誤差約３％以内）。特に、タイプ１のＭ３信号配線の遅延回路については、図１３に示したようにダミーパターンＤＰの影響を考慮する前はシミュレーション値Ｓｉｍと実測値との誤差が−１３．６％であったのに対して、本発明による考慮後は誤差＋２．６％でほぼ一致するまで精度が大幅に改善されている。
【００７３】
以上により、本実施形態によれば、ダミーパターンＤＰを考慮した精度良い回路シミュレーションが可能である。シミュレーション値Ｓｉｍと実測値との誤差とが約３パーセント以内であった。特に、ダミーパターンＤＰを考慮しなかった場合にシミュレーション値Ｓｉｍと実測値の誤差が大きかったタイプ１の遅延回路については、誤差が−１３．６パーセントから＋２．６パーセントへ大幅に改善できている（図５と図１３を参照）。本発明の回路シミュレーション手法により半導体集積回路の設計精度が向上するので非常に効果がある。本発明のシミュレーション手法は高い設計精度が要求されるシステムＬＳＩやフラッシュメモリなどの半導体集積回路の開発・設計に適用可能である。また、設計精度を向上することで試作回数削減や開発期間の短縮化などのコストダウンの経済的効果も大いにある。
【００７４】
特に、半導体集積回路のプロセスが微細化されると配線負荷が信号遅延時間に及ぼす影響が顕著になるので、本発明は高集積化された半導体集積回路に適用することにより絶大な効果を奏するものである。
【００７５】
【発明の効果】
以上のように、本発明によれば、シミュレーション用等価回路モデルは、該各接続ノードに付加される負荷情報として、回路的に機能しないダミー配線とその周辺に配置される他の配線、基板の導体および半導体との間に存在する負荷情報を含むため、回路動作の検証を行う際に、ダミーパターンと信号配線間の配線容量をも考慮したシミュレーション用等価回路モデルを用いることにより、信号遅延などの回路シミュレーションの高精度化を図ることができる。
【図面の簡単な説明】
【図１】本発明の一実施形態における回路シミュレーションシステムの要部ハード構成を示すブロック図である。
【図２】図１の回路シミュレーションシステムによる各処理手順を示すフローチャートである。
【図３】（ａ）および（ｂ）は電磁界方程式を用いた本発明の数値解析による配線容量計算処理を説明するための図である。
【図４】信号遅延測定回路において複数の同層信号配線が隣接並行して走るタイプ２の説明図であって、（ａ）はダミーパターンを含む信号配線負荷を形成するレイアウト例の平面図、（ｂ）は（ａ）の信号配線負荷が付加される位置を論理回路レベルで示した回路図、（ｃ）は（ａ）のＸ−Ｘ’断面構成と同時に示す負荷容量の等価回路図、（ｄ）はダミーパターンを考慮に入れた本発明の等価回路モデルを示す図である。
【図５】信号遅延時間における本発明のシミュレーション値と実測値の比較結果を示す図であって、（ａ）は遅延回路タイプ１を示す図、（ｂ）は遅延回路タイプ２を示す図である。
【図６】従来の半導体集積回路に用いるダミーパターンの概要説明図であって、（ａ）は段差の発生メカニズムを説明するための半導体装置の積層断面図、（ｂ）はダミーパターンの挿入による平坦化を説明するための半導体装置の積層断面図、（ｃ）はダミーパターンに起因する寄生容量を含む信号配線周辺の容量形成を説明するための半導体装置の積層状態を示す斜視図である。
【図７】従来の半導体集積回路に用いるダミーパターンの物理的効果の概要説明図であって、（ａ）はダミーパターン幅が信号配線幅よりも非常に大きい場合のシールド効果の概要説明図、（ｂ）はダミーパターンの同層信号配線への影響を説明するための図である。
【図８】多層配線プロセスによる層間構造を持つ従来の半導体チップの断面構成図である。
【図９】ダミーパターンが信号配線に及ぼす影響を説明するための図である。
【図１０】従来の信号遅延測定回路において単一信号配線が走るタイプ１の説明図であって、（ａ）は信号配線負荷が付加される位置を論理回路レベルで示した回路図、（ｂ）は信号配線負荷を形成するレイアウト例の平面図、（ｃ）は（ｂ）のＸ−Ｘ’断面構成と負荷容量の等価回路とを同時に示す図、（ｄ）は信号遅延回路の信号配線幅を示す図である。
【図１１】従来の信号遅延測定回路において複数の同層信号配線が隣接並行して走るタイプ２の説明図であって、（ａ）は信号配線負荷が付加される位置を論理回路レベルで示した回路図、（ｂ）は信号配線負荷を形成するレイアウト例の平面図、（ｃ）は（ｂ）のＸ−Ｘ’断面構成と負荷容量の等価回路とを同時に示す図、（ｄ）は信号遅延回路の信号配線幅および線間隔を示す図である。
【図１２】従来の信号遅延回路における測定評価手法の説明図であって、（ａ）および（ｂ）は基本論理ゲートの段数が異なる場合の２種類の信号遅延回路図、（ｃ）は（ａ）の信号遅延回路の入力信号と出力信号の遅延時間を示す信号波形図、（ｄ）は（ｂ）の信号遅延回路の入力信号と出力信号の遅延時間を示す信号波形図である。
【図１３】信号遅延時間における従来のシミュレーション値と実測値の比較結果を示す図であって、（ａ）は遅延回路タイプ１を示す図、（ｂ）は遅延回路タイプ２を示す図である。
【符号の説明】
１　　回路シミュレーションシステム
２　　シミュレーション用等価回路モデル生成装置
２１　　ＲＯＭ
２２　　ＲＡＭ
２３　　データベース
２４　　入力操作部
２５　　表示部
２６　　制御部
２６１　　レイアウト処理手段
２６２　　負荷情報抽出手段
２６２Ａ　　電位勾配算出手段
２６２Ｂ　　電荷量算出手段
２６２Ｃ　　容量値算出手段
２６３　　負荷情報付与手段
２６４　　電位情報付加手段
３　　回路シミュレーション装置[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention is applied to, for example, circuit design of a system LSI or a flash memory LSI, and generates a simulation equivalent circuit model used in a semiconductor integrated circuit design technique (circuit simulation technique) of a multilayer wiring process for flattening an interlayer structure. TECHNICAL FIELD The present invention relates to an equivalent circuit model generation device for use, a circuit simulation system using the same, a simulation equivalent circuit model generation method, a control program for executing this procedure, and a readable recording medium storing the control program.
[0002]
[Prior art]
In recent years, the influence of parasitic wiring capacitance (hereinafter simply referred to as wiring capacitance) on signal delay time (hereinafter simply referred to as signal delay) has become extremely large with the miniaturization of semiconductor integrated circuit processes. The signal delay time is a time during which an electric signal is transmitted inside the semiconductor integrated circuit. It is said that about 60% or more of the leading-edge process in which the minimum processing size of the semiconductor integrated circuit is 0.25 μm or less is caused by the wiring capacitance. The dependence between the signal delay and the wiring capacitance is described in the document "DENNIS SYLVESTER,""Impact of Small Process Geometries on Microarchitectures in Systemon Chip", "Procedures of E.P.I.E. Have been.
[0003]
Particularly, in a semiconductor integrated circuit device (hereinafter, referred to as a semiconductor chip) using a recent multilayer wiring process, unevenness which causes disconnection due to a step of a signal wiring due to the density of signal wiring in the semiconductor chip is prevented, and reliability is improved. In order to improve the performance, the interlayer structure is flattened by disposing a dummy pattern (metal layer wiring pattern in a floating state) in a metal layer in an empty region in the semiconductor chip. Since these placement locations depend on the density of signal wiring on the semiconductor chip after layout, dummy patterns are placed as post-processing based on the placement rules defined by the design rules after the layout is completed. As a result, a wiring capacitance is newly generated between the signal wirings for the dummy pattern.
[0004]
Here, FIG. 6A shows the mechanism of the generation of the above-described step, FIG. 6B shows the flattening by inserting the dummy pattern, and FIG. 6B shows the formation of the capacitance around the signal wiring including the parasitic capacitance caused by the dummy pattern. 6 (c).
[0005]
That is, FIG. 6A shows a cross-sectional view of a semiconductor chip in which three layers of metal wirings M1 to M3 are wired in the depth direction, and the three layers of metal wirings are concentrated near both ends in the drawing. The central portion shows a state in which the wiring density, which has only the second-layer metal wiring ML, is low. In this sparse portion, in particular, since the metal wiring does not exist in the first layer directly below the metal wiring ML, if the interlayer insulating film material is uniformly deposited on the substrate (Substrate), the sparse portion above and below the wiring portion Depression occurs. This becomes a step H, and the step H easily causes disconnection of the second-layer metal wiring ML.
[0006]
In FIG. 6B, in order to avoid the generation of the step H, a cross section in the case where a dummy wiring pattern not used for signal transmission (this is called a dummy pattern DP) is formed in a region where wiring density is low. As shown in the figure, the provision of the dummy patterns DP at the upper and lower positions of the metal wiring ML eliminates the depression in the interlayer insulating film, so that the step H does not occur. As described above, by arranging the dummy pattern DP in the empty region for uniform density, the step H due to the wiring density is eliminated, and the disconnection due to the step H of the second-layer metal wiring ML does not occur. However, the dummy pattern DP serves as an electrode, and a parasitic capacitance is added around the signal wiring.
[0007]
FIG. 6C shows the parasitic capacitance around the signal wiring in the case where the dummy pattern DP is provided. In addition to the parasitic capacitance Cp between the signal wirings of the metal M2 layer, the dummy capacitance DP and the dummy pattern DP of the metal M3 layer are shown. A parasitic capacitance Ct is added between the signal wiring of the metal M2 layer (different layers) and a parasitic capacitance Cb is added between the dummy pattern DP of the metal M1 layer and the signal wiring of the metal M2 layer (different layers). ing. The wiring capacitances Ct and Cb between the dummy pattern DP and the signal wiring ML are the wiring capacitance Cp between the signal wiring ML and another signal wiring, and the wiring capacitance between the signal wiring ML and the substrate (Substrate). Similar to (not shown), this affects circuit performance such as signal delay and circuit operation speed.
[0008]
For example, as an example of an experiment in which the effect of the presence or absence of a dummy pattern DP on signal delay was examined by trial evaluation of an actual test circuit, reference was made to Nakabayashi, Moat, et al., "Influence of dummy pattern of interlayer CMP on signal delay and its effect. Circuit Simulation Method ", 62nd Annual Meeting of the Japan Society of Applied Physics, September 2001", reports that the presence of the dummy pattern DP increases the signal delay by up to about 20%.
[0009]
[Problems to be solved by the invention]
However, in the current circuit design, when the wiring capacitance is extracted after the layout and the circuit operation is verified by circuit simulation, only the wiring capacitance between each signal wiring functioning as a circuit and between the signal wiring and the board is considered. At present, the wiring capacitance between the dummy pattern DP and the signal wiring cannot be considered. For this reason, there is a major problem that it is not possible to accurately estimate circuit performance such as signal delay.
[0010]
References relating to the wiring capacity of the multilayer wiring process include "Modeling and Extraction of Interconnect Capacitances for Multilayer VLSI Circuits" (IEEECAD VOL. 15, NO. 1, NO. 1, 1996, etc.). Although this document discusses a calculation method for a wiring capacitance between signal wirings and between a signal wiring and a substrate, the handling of the dummy pattern DP is not considered at all here. The same applies to other documents, and a circuit simulation method or the like that takes into account the dummy pattern DP has not been established yet, and is one of the important issues in circuit design technology using a multilayer wiring process. .
[0011]
As described above, the dummy pattern DP for maintaining the planarization of the interlayer structure in the multilayer wiring process is not an actual signal wiring functioning as a circuit, and is not connected to any part surrounded by the interlayer insulator. Despite being in a floating state, wiring capacitances Ct and Cb are formed between signal wirings (in particular, upper and lower different layers) with an interlayer insulating film interposed therebetween, which greatly affects signal delay.
[0012]
Here, the effect of the signal delay will be described in detail with reference to FIG.
[0013]
FIGS. 7A and 7B are schematic explanatory diagrams of a physical effect of a dummy pattern used in a conventional semiconductor integrated circuit. FIG. 7A is a schematic explanatory diagram of a shielding effect when a dummy pattern width is much larger than a signal wiring width. (B) is a diagram for explaining the effect of the dummy pattern on the same-layer signal wiring.
[0014]
FIG. 7A shows that when the dummy pattern width is much larger than the signal wiring width, the dummy pattern DP can be approximated to a parallel plate having a shielding effect, and FIG. 7B shows the dummy pattern DP. Indicates that even if it is approximated as a parallel plate, it does not significantly affect the signal wiring of the same layer adjacent in the horizontal direction.
[0015]
For example, when the width of the signal wiring ML is 0.50 μm or less and the width of the dummy pattern DP is 10 μm or more, the dummy pattern DP has a width that is about two digits larger than the width of the signal wiring arranged in a different layer. In such a case, if a potential difference occurs between the two as shown in FIG. 7A, the electric lines of force drawn from the signal wiring corresponding to the wiring capacitance are all absorbed by the dummy pattern DP. That is, since the electric lines of force coming out of the signal wiring are shielded by the upper and lower dummy patterns DP acting as parallel plates, the dummy pattern DP is equivalent to a power supply or a ground having a shielding effect with a small fluctuation of potential with respect to the signal wiring. This has an effect equivalent to the capacitance that the effective width of the signal wiring directly contributes to. In FIG. 6C, the effective capacitance is represented by wiring capacitances Ct and Cb between different layers according to the relationship between the wiring layers on which both are arranged. On the other hand, as shown in FIG. 7 (b), for a signal wiring which is horizontally adjacent to the dummy pattern DP and is arranged in the same layer, only the side portions of both sides contribute to the capacitance. The effect of the layer on other signal lines is very small. In FIG. 6B, this capacitance is represented by the wiring capacitance Cp in the same layer. In the actual measurement, the wiring capacitance Cp in the same layer is about 1/10 of the wiring capacitance Cb between different layers (Cp ≒ Cb / 10).
[0016]
However, since these dummy patterns DP are in a floating state and the absolute value of the potential is not determined, a method of calculating the wiring capacitance formed between the dummy pattern DP and the signal wiring has not been established. A simulation equivalent circuit model taking into account the wiring capacitance formed between the dummy pattern DP and the signal wiring has not been established.
[0017]
The initial voltage required for performing the transient analysis (time response analysis of the circuit) for obtaining the signal delay in the semiconductor circuit cannot be set, and the circuit simulation cannot be performed while the dummy pattern DP is in a floating state (the circuit simulation is not performed). The solution cannot be found due to the limitations of the solution). For this reason, in the current back annotation (which means that the wiring capacitance is extracted after the completion of the circuit diagram creation and layout, and the circuit simulation is performed again after adding the wiring capacitance information), the dummy pattern DP has a signal delay. However, there is a problem that the signal delay cannot be considered and the signal delay cannot be accurately estimated.
[0018]
Here, since the dummy pattern DP cannot be considered in advance with respect to the signal delay, the degree of influence of the dummy pattern DP on the current estimation accuracy of the signal delay in the semiconductor integrated circuit will be quantitatively examined.
[0019]
First, an example 1 of the effect of signal delay due to the dummy pattern DP will be described. As described above, the dummy pattern DP greatly affects the signal wiring in the different layer. In other words, the signal wiring is greatly affected by the dummy pattern DP of the different layer. In the first case, a semiconductor chip having an interlayer structure manufactured by using a multilayer wiring process will be considered in order to easily explain the influence of the dummy pattern DP on the signal wiring.
[0020]
FIG. 8 is a sectional configuration diagram of a semiconductor chip having an interlayer structure by a multilayer wiring process.
[0021]
As shown in FIG. 8, signal wirings M1 to M5 formed of five layers of metal material are stacked on a semiconductor substrate (Substrate) via respective interlayer insulating films SiO2, respectively. Further, PIQ, SIN, and PSG are respectively laminated as protective films.
[0022]
Here, the relative dielectric constants of SiO2, PSG, SIN, and PIQ are 4.1, 4.2, 6.3, and 3.4, respectively, the thickness of each interlayer insulating film SiO2 is 1100 nm for each layer, and the metal wirings M1 to M1 are formed. The thickness of M5 is 550 nm, 750 nm, 750 nm, 750 nm, and 900 nm, respectively, and the total thickness of the protective film having a laminated structure of PIQ, SIN, and PSG is 4450 nm.
[0023]
In a semiconductor chip having such an interlayer structure, a single signal wiring is provided in the metal second layer (M2), and dummy patterns are provided in the upper metal third layer (M3) and the lower metal first layer (M1). Consider the simple case where there is a DP. FIG. 9 schematically shows this, and the description will be made with reference to this schematic diagram.
[0024]
In FIG. 9, attention is paid to the M2 signal wiring, and its wiring capacity is obtained based on the electromagnetic field theory generally known in the literature such as “Baifukan“ Introduction to Physics ”, Chapter 2”.
[0025]
If there is a dummy pattern DP, the wiring capacitance Cm2 of the M2 signal wiring is the capacitance of the wiring capacitance Ct between the M3 dummy pattern DP and the M2 signal wiring, and the wiring capacitance Cb between the M2 signal wiring and the M1 dummy pattern DP. Can be represented by the sum of Therefore, when the width of the M2 signal wiring is 0.36 μm and the width of the dummy pattern DP is 10 μm (similar to FIG. 8), Ct = 0.0662 [fF / um] and Cb = 0.0665 [fF / um]. ], Cm2 = Ct + Cb = 0.1327 [fF / um].
[0026]
If there is no dummy pattern DP, the wiring capacitance Cm2 'of the M2 signal wiring is simply represented by only the wiring capacitance Cb' between the M2 signal wiring and the substrate, so that Cm2 '= Cb', which is a typical value. Is 0.0766 [fF / um].
From the obtained relationship of Cm2 ′ <Cm2, the wiring capacitance Cm2 ′ adopted in the conventional back annotation and not considering the dummy pattern DP is significantly smaller than the actual wiring capacitance Cm2 after the dummy pattern DP is arranged. I understand. In other words, the signal delay is proportional to the wiring capacitance (and the resistance value). That is, since it is determined by the time constant RC of the wiring, the back annotation is conventionally performed while the signal delay is underestimated as compared with the actual case. In this case 1, for the sake of simplicity, a simple case in which the M3 dummy pattern DP and the M1 dummy pattern DP are respectively provided on the upper and lower layers of the single M2 signal wiring is considered. The same applies to a case where a plurality of wirings are adjacently arranged, a case where a signal wiring is in an arbitrary metal layer, and a case where a dummy pattern DP exists only in one of an upper layer and a lower layer of a signal wiring. Can be said.
[0027]
Next, an example 2 of the influence of the signal delay due to the dummy pattern DP will be described. Consider a signal delay measuring circuit (hereinafter, referred to as a delay circuit) for the purpose of actual signal delay evaluation. In this delay circuit, as shown in FIGS. 10 and 11, basic logic gates are connected in even-numbered stages, and the output of the basic logic gate in each stage is loaded with a signal wiring. The load due to the signal wiring includes two typical signal wiring types often used in actual semiconductor integrated circuits.
[0028]
One is a type in which a single signal wiring runs as shown in FIG. 10, and the case where the influence of the interlayer capacitance or the capacitance to the substrate is dominant (hereinafter referred to as type 1), and the other is a type as shown in FIG. In this case, there is a case where a plurality of same-layer signal wirings run adjacently in parallel and the influence of capacitance between these adjacent signal wirings is larger (hereinafter referred to as type 2).
[0029]
10 and 11, (a) is a circuit diagram showing, at a logic circuit level, a position where a load (wiring RC load) due to signal wiring is added, and (b) is a plan view of a layout example for forming the wiring RC load. (C) is a diagram simultaneously showing the XX ′ cross-sectional configuration example of (b) and an equivalent circuit of the load capacitance (when the metal second layer is a signal wiring), and (d) is the signal wiring width of the signal delay circuit FIG. Further, a total of six cases (2 × 3 = 6) in three cases, which one of the signal wiring layers is M1, M2, and M3, is considered. For each delay circuit, two types having different numbers of chain stages are prepared, and the signal delay per chain stage is measured and evaluated by taking the difference in signal delay. Here, the first stage of the chain is a portion from the input of a certain basic logic gate to the input of the next basic logic gate including the wiring RC load as shown in FIG. . This specific measurement method is shown in FIG.
[0030]
As shown in FIGS. 12A and 12B, first, two types of signal delay circuits having the same configuration except that the number of stages of the basic logic gates (the number of stages is an even number) are different. Here, FIG. 12A has an even-numbered stage number N1, and FIG. 12B has an even-numbered stage number N2, and each stage number is N2> N1.
[0031]
Next, the delay time of each signal delay circuit (the time from when a signal is input to the input PAD to when the signal is output to the output PAD) is measured. In the case of the signal delay circuit of FIG. 12A, as shown in FIG. 12C, after the pulse signal having the amplitude Vdd is input, the output signal rises after the delay time tr1 and falls after the delay time tf1.
[0032]
In the case of the signal delay circuit shown in FIG. 12B, as shown in FIG. 12D, after the pulse signal having the amplitude Vdd is input, the output signal rises after the delay time tr2 and falls after the delay time tf2. Thus, the signal delay time per one stage of the chain can be easily calculated from the following equation.
[0033]
Signal delay time per chain = (total signal delay time−total signal delay time 1) / (N2−N1) where the total signal delay time is an average value of rising delay time and falling delay time. ,
Total signal delay time 1 = (tr1 + tf1) / 2
Total signal delay time 2 = (tr2 + tf2) / 2
And
[0034]
As described above, in order to determine the signal delay time per stage, first, two types of signal delay circuits having the same configuration and having different even stages are prepared. Next, the total signal delay time from input to output is measured for each signal delay circuit. Further, the signal delay time per stage can be obtained by dividing the difference between all the signal delay times by the difference in the number of stages.
[0035]
Next, the wiring capacitance between the signal wiring and the signal wiring and between the signal wiring and the substrate are determined by a generally known electromagnetic field theory assuming that the dummy pattern DP does not exist without considering the dummy pattern DP as in the conventional back annotation. Using this wiring capacitance, a signal delay is further obtained by circuit simulation.
[0036]
FIG. 13 shows a comparison result between the measured value of the signal delay time of each signal wiring layer (M1, M2, M3) and the current circuit simulation value for both types 1 and 2 circuits shown in FIGS. In both the type 1 (FIG. 13 (a)) and the type 2 (FIG. 13 (b)), the delay time is larger in the actual measurement value than in the current circuit simulation value. , M3. The error of the current circuit simulation value with respect to the actually measured value reaches a maximum of -13.6% in the case of type 1. From these results, when comparing the signal delay value (with dummy pattern) actually measured from the delay circuit actually manufactured and the signal delay value (without considering the dummy pattern) by the current circuit simulation method, they do not match, and in any case, the actual measurement is not performed. The value is larger, and it can be seen that the effect of the dummy pattern DP cannot be ignored. In particular, in the case of the type 1 M3 signal wiring, there is an actual measurement error of -13.6% as described above. Considering the necessity of accurately estimating the signal delay in the back annotation with the improvement of the performance of the semiconductor integrated circuit in the future, the error -13.6% is large. For example, according to the document “TSMC Technology 'Device Modeling', the error is at least It is necessary to keep it within a few percent.
[0037]
The present invention has been made in view of the above circumstances, and is a simulation capable of improving the accuracy of a signal delay simulation in consideration of a wiring capacitance between a dummy pattern and a signal wiring when verifying a circuit operation. For generating an equivalent circuit model for simulation for generating an equivalent circuit model for use, a circuit simulation system using the same, a method for generating an equivalent circuit model for simulation, a control program for executing this procedure, and a readable recording medium storing the control program The purpose is to do.
[0038]
[Means for Solving the Problems]
The simulation equivalent circuit model generation device of the present invention is a simulation equivalent circuit model generation device that generates a simulation equivalent circuit model including circuit connection information to be subjected to a circuit simulation and load information added to each connection node, The equivalent circuit model for simulation uses, as load information added to each connection node, load information existing between a dummy wiring that does not function as a circuit and other wirings arranged around the dummy wiring, a conductor of the substrate, and a semiconductor. The above-described object is achieved.
[0039]
Preferably, in the simulation equivalent circuit model generating apparatus of the present invention, the layout design processing is performed in accordance with the circuit design data obtained in the circuit design processing, and the layout design data obtained in the layout design processing does not function as a circuit. Layout processing means for arranging dummy wirings, and load information including capacitance values existing between the dummy wirings arranged by the layout processing means and other wirings, conductors of the substrate, and semiconductors arranged around the dummy wirings are extracted. Load information extracting means, load information providing means for providing load information existing around the dummy wiring extracted by the load information extracting means to a corresponding connection node of the circuit connection information, and load information provided by the load information providing means Information indicating the power supply potential or the ground potential is added to the node corresponding to the connection point of the dummy wiring. And a potential information adding means.
[0040]
Further preferably, the load information extracting means in the simulation equivalent circuit model generating apparatus according to the present invention, when extracting the capacitance value between the dummy wiring and the conductor and the semiconductor around the dummy wiring, from the load information, The potential of the dummy wiring which is to be the electrode portion of the capacitor is set to the ground potential or the power supply potential together with the physical shape information obtained from the above and the process parameter to be subjected to the circuit simulation, and the potential gradient near the electrode portion surface of the capacitor is calculated. A potential gradient calculating means, a charge amount calculating means for calculating a charge amount on the electrode portion surface from the potential gradient calculated by the potential gradient calculating means, and a potential difference between the charge amount and the electrode portion calculated by the charge amount calculating means. A capacitance value calculating means for calculating a capacitance value.
[0041]
A circuit simulation system according to the present invention is capable of executing a circuit simulation using a simulation equivalent circuit model generated by the simulation equivalent circuit model generation device according to any one of claims 1 to 3. This achieves the above object.
[0042]
A method for generating an equivalent circuit model for simulation according to the present invention is a method for generating an equivalent circuit model for simulation including circuit connection information to be subjected to circuit simulation and load information added to each connection node. A first step of arranging a dummy wiring which does not function as a circuit in the layout design data obtained by the layout design processing, and a dummy wiring and other wirings arranged around the dummy wiring; A second step of extracting load information including a capacitance value existing between the conductor and the semiconductor of the substrate; and loading the load information existing around the dummy wiring extracted in the second step to a corresponding connection node of the circuit connection information. A third step of providing, and of the load information provided in the third step, the connection of the dummy wiring. Those having a fourth step of adding information to the node corresponding to the point showing a power supply potential or ground potential, the objects can be achieved.
[0043]
Preferably, in the second step of the method for generating an equivalent circuit model for simulation of the present invention, when extracting the capacitance value between the dummy wiring and the surrounding conductor and semiconductor from the load information, Setting the potential of the dummy wiring to be the electrode portion of the capacitor to the ground potential or the power supply voltage together with the obtained physical shape information and the process parameter to be subjected to the circuit simulation, and calculating a potential gradient near the surface of the electrode portion of the capacitor Calculating a charge amount on the surface of the electrode unit from the potential gradient; and calculating a capacitance value from the calculated charge amount and a potential difference between the electrode units.
[0044]
A control program according to the present invention causes a computer to execute each processing procedure in the simulation equivalent circuit model generating method according to claim 5, thereby achieving the above object.
[0045]
The readable recording medium of the present invention is readable by a computer in which the control program according to claim 7 is recorded, thereby achieving the above object.
[0046]
With the above configuration, according to the present invention, in designing a semiconductor integrated circuit using a multilayer wiring process, when a wiring capacity is extracted after layout is completed and circuit operation is verified by circuit simulation, the conventional signal wiring In addition to the wiring capacitance between the signal wiring and the board, the wiring capacitance formed between the dummy pattern and the signal wiring, which could not be considered in the past, is accurately extracted and reflected in the circuit simulation. It is possible to improve the accuracy of a circuit simulation such as a signal delay operation.
[0047]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the circuit simulation system of the present invention will be described with reference to the drawings.
[0048]
FIG. 1 is a block diagram illustrating a hardware configuration of a main part of a circuit simulation system according to an embodiment of the present invention.
[0049]
In FIG. 1, a circuit simulation system 1 includes a simulation equivalent circuit model generation device 2 that generates a simulation equivalent circuit model in consideration of a dummy pattern, and a circuit simulation such as a signal delay simulation using the simulation equivalent circuit model. And a circuit simulation device 3 that can be executed.
[0050]
The simulation equivalent circuit model generation device 2 includes a ROM 21, a RAM 22, and a database 23 as storage units, an input operation unit 24, a display unit 25 having a display screen, and a control unit 26 that controls each unit. .
[0051]
The ROM 21 stores a control program such as a simulation equivalent circuit model generation control program and various data such as various display screen information and table information.
[0052]
The RAM 22 functions as a work memory for temporarily storing necessary data such as a control program and various data when the control unit 26 operates.
[0053]
The database 23 stores various data for generating an equivalent circuit model for simulation.
[0054]
The input operation unit 24 is configured by an input device such as a keyboard and a mouse, and is capable of inputting various input commands such as a start command and an end command of a control program for generating an equivalent circuit model for simulation.
[0055]
The display unit 25 displays various screen information such as an initial screen for simulation equivalent circuit model generation processing, various selection screens, and a result screen on the display screen.
[0056]
The control unit 26 is constituted by a CPU (Central Processing Unit), and based on the control program and various data thereof, performs circuit design processing, layout design processing according to the circuit design processing data, and further layout design processing data. A layout processing unit 261 for arranging a dummy pattern (dummy wiring) that does not function in a circuit, and a load for extracting load information existing between the dummy pattern and other wirings and conductors of the substrate and the semiconductor arranged around the dummy pattern Information extracting means 262, load information providing means 263 for providing load information existing around the extracted dummy pattern to a connection node corresponding to the circuit connection information, and a node corresponding to the connection point of the dummy pattern in the provided load information Potential information adding means 264 for adding information indicating a power supply potential or a ground potential to By having to generate an equivalent circuit model for simulation considering dummy pattern.
[0057]
The load information extracting unit 262 is configured to determine, from among the extracted load information, a capacitance value between the dummy pattern DP and a conductor and a semiconductor around the dummy pattern DP by using physical shape information obtained from layout design data and a process parameter to be subjected to circuit simulation. At the same time, the potential of the dummy pattern DP serving as an electrode of the capacitor is set to the ground potential or the power supply potential, and a potential gradient calculating means 262A for calculating a potential gradient near the electrode portion surface of the capacitor; And a capacitance value calculation unit 262C for calculating a capacitance value based on a potential difference between the calculated charge amount and the electrode unit.
[0058]
Like the simulation equivalent circuit model generation device 2, the circuit simulation device 3 is configured by a computer having a control unit (CPU), and based on the circuit simulation control program and various data thereof, the simulation equivalent circuit model generation device Various circuit simulations such as a signal delay simulation can be executed using the simulation equivalent circuit model from Step 2.
[0059]
With the above configuration, a procedure for generating a simulation equivalent circuit model in consideration of a dummy pattern and a circuit simulation procedure such as a signal delay operation using the simulation equivalent circuit model will be sequentially described below.
[0060]
FIG. 2 is a flowchart showing each processing procedure by the circuit simulation system 1 of FIG. The processing flow is shown on the left side of FIG. 2, and the data flow input / output in each step of the processing flow is shown on the right side.
(Advance preparation processing; circuit design processing, layout design processing, and dummy pattern placement processing)
As shown in FIG. 2, when the circuit design processing and the layout design processing in step S1 are completed, in step S2, the circuit design of the semiconductor integrated circuit was followed in order to consider the dummy pattern DP in the back annotation. On the layout data after the layout design is completed, a dummy pattern DP is arranged in a wiring sparse region for flattening a layer. More specifically, the location of the dummy pattern DP is determined according to the density of the signal wiring in the semiconductor chip according to the placement rule specified by the design rule, and the dummy pattern DP is placed on the layout data. Thereby, design circuit diagram data and layout data are generated.
[0061]
Next, the following process parameters representing the interlayer structure are prepared in order to obtain the wiring capacitance as the load information. Here, as a specific example, for example, the same process parameters as those of the interlayer structure shown in FIG. 8 may be used. That is, the following parameters and their values may be used.
Insulation film thickness 1100nm
Dielectric constant of insulating film 4.1 (SiO2)
Wiring height 550 nm (M1), 750 mn (M2 to M4), 900 nm (M5)
(Load information extraction processing; potential gradient calculation processing, charge amount calculation processing, and capacitance value calculation processing)
The layout position, shape, wiring layer of the dummy pattern and signal wiring obtained from the layout data generated in step S2, the wiring layer, and the process parameters prepared in the above preparatory process are used as input information. And the like, and calculate the wiring capacitance based on the electromagnetic field theory known. Utilizing that this wiring capacitance is determined only by the shape / positional relationship between the conductor and the insulator (interlayer insulating film) and the dielectric constant of the insulator, the above-mentioned wiring capacitance including between the dummy pattern and the signal wiring is obtained.
[0062]
The outline of the calculation procedure of the wiring capacitance is shown in FIGS. 3 (a) and 3 (b). The calculation procedure (potential gradient calculation processing, charge amount calculation processing, and capacitance value calculation processing) will be described.
[0063]
The dummy pattern DP is a conductor because it is made of a metal material like the signal wiring. In other words, between the dummy pattern DP and the signal wiring, as shown in FIG. 3A, an insulator C made of an interlayer insulating film is interposed between the conductor A of the signal wiring and the conductor B of the dummy pattern DP to form a laminated structure. Has become.
[0064]
In this structure, by using the potential Φ = V1 = 1V in the conductor A and the potential Φ = V2 = 0V in the conductor B as boundary conditions, the Laplace equation and the electric field equation shown in the following (Equation 1) are used. The equation is solved using the boundary element method BFM or the finite element method FEM (for example, described in detail in the literature “Science Co., Ltd.“ Finite Element Method and Boundary Element Method ”) and the like, and the potential in the direction perpendicular to the conductor surface is solved. The differential coefficient of Φ (the electric field E perpendicular to the conductor surface) is calculated (potential gradient calculation processing). That is, although the potential of the conductor B is originally in a floating state, it can be regarded as a power supply or a ground plane as described later. Therefore, the ground potential is set to 0 V with respect to the positive conductor A. As a result, a potential distribution Φ in the insulator is obtained.
[0065]
(Equation 1)

Next, the electric charge Q on the surfaces of the conductors A and B is calculated by the Gaussian numerical integration formula (Equation 1; Gauss's theorem) of FIG. The wiring capacitance C is obtained from the relationship between Q and the potential difference (V1-V2). Similarly, the wiring capacitance is obtained between the signal wiring and the signal wiring, between the signal wiring and the substrate, and the like (capacity value calculation processing).
[0066]
In step S3, the wiring capacitance between the dummy pattern DP and the signal wiring, between the signal wiring and the signal wiring, and between the signal wiring and the substrate is obtained by using these calculation methods. That is, in this step S3, the process interlayer structure information is input as data, and the wiring capacitance value is output.
(Equivalent circuit model creation processing taking into account dummy pattern DP; load information addition processing) Between dummy pattern DP and signal wiring, between signal wiring and signal wiring, between signal wiring and board obtained in wiring capacitance calculation processing in step S3. Each wiring capacitance as load information is merged (merged or merged) with design circuit diagram data (step S1; data describing connection relations of transistors and basic elements constituting the circuit) to create an equivalent circuit model for simulation. (Load information providing process). FIGS. 4A to 4D show the concept in a case of a type 2 signal delay circuit (the case where the second metal layer M2 is a signal wiring layer) as a specific example.
[0067]
FIG. 4A shows a plan view of a circuit layout equivalent to the signal wiring circuit of FIG. 11 (type 2 signal delay circuit; the second metal layer is a signal wiring). From the circuit layout of FIG. 4A, the equivalent circuit model of FIG. 4B is obtained by replacing the signal wiring connecting the basic logic gates A and B with the wiring resistance Rint and the wiring capacitance Cint.
[0068]
The wiring resistance in this case is calculated by the physical formula Rint = ρ * (Lint / Wint) (ρ: sheet resistance value of metal material, Lint: signal wiring length, Wint: signal wiring width).
[0069]
The wiring capacitance Cint corresponds to the area between the dummy pattern DP and the capacitance between the signal wirings and the distance between the signal wirings and the signal wiring, which are obtained by the above wiring capacitance calculation processing corresponding to the cross section XX ′ of the signal wiring in FIG. Then, an equivalent circuit model of FIG. 4C is created using the wiring capacitance between the signal wiring and the substrate. More specifically, as to the wiring capacitance Cint, as shown in FIG. 4D, in order to accurately simulate the effect of each wiring capacitance corresponding to the cross section of the signal wiring shown in FIG. In step S4, between the M2 layer signal wiring and the M2 layer signal wiring (Cp22, Cp23), between the M3 layer dummy pattern and the M1 layer dummy pattern (C31), between the M3 layer dummy pattern and the substrate (C3), and in the M1 layer dummy pattern For simulation including all wiring capacitances such as between the semiconductor substrate and the substrate (C1), between the M3 layer dummy pattern and the M2 layer signal wiring (Ct, Ct '), between the M1 layer dummy pattern and the M2 layer signal wiring (Cb, Cb'). Create an equivalent circuit model. That is, in step S4, the design circuit diagram data in step S1 and the wiring capacitance value data in step S3 are input as data, and the simulation equivalent circuit model in FIG. 4D is output.
(Voltage setting process for dummy pattern DP; potential information addition process)
In a recent microfabricated multilayer wiring process using the dummy pattern DP, the signal wiring width is generally 0.5 μm or less, while the size of the dummy pattern DP is very large, 10 μm × 10 μm or more. From this, the dummy pattern DP arranged on the semiconductor chip can be regarded as a substantially parallel plate. The wiring capacitance of these parallel plates is dominated by the bottom component (toward different layers above and below), and the side component to the same layer is smaller than that and is about 1/10 or less. In other words, the dummy pattern DP has a small effect on other signal wires and the like in the same layer, but has a large effect on signal wires and the like in upper and lower different layers, and has an effect of shielding the signal wires. That is, as described in FIG. 7, it can be regarded as equivalent to the power / ground plane. This is described in the literature "Chapter 4 of" VLSI System Design "Circuits and Basics of Implementation" or in the literature "ASHOKK. Has been described. Utilizing this, the voltage of all the nodes (shown by hatched circles in FIG. 4D) corresponding to each dummy pattern of the simulation equivalent circuit model created in the above process is changed to the power supply voltage value Vdd or the ground voltage level ( 0V). Since the circuit simulation result of the signal delay is the same regardless of which one is fixed (the simulation result is not affected), the ground voltage level (0 V) that is easy to handle is usually fixed.
[0070]
As will be described repeatedly, since the dummy pattern DP is in a floating state in which the entire periphery is surrounded by the interlayer insulating film, the dummy pattern DP is not included in the equivalent circuit model created in the above-described equivalent circuit model creation processing (step S4 in FIG. 2). Only the wiring capacitance is connected to the node corresponding to the DP (the hatched circle in FIG. 4D). As described above, since the dummy pattern DP has the effect of shielding the signal wiring as a parallel plate as described above with reference to FIG. 7, the dummy pattern DP is regarded as a power / ground plane, and these nodes corresponding to the respective dummy patterns DP Is fixed to the same potential as the power supply / ground. Specifically, a power supply name (usually Vdd) or a ground name (usually GND) is given to these nodes as names for the simulation equivalent circuit model generated in step S4 (potential information addition processing). In addition, since the circuit simulation result of the signal delay does not change between the case where the dummy pattern DP is regarded as the power supply and the case where the dummy pattern DP is regarded as the ground (the simulation result is the same and has no influence), here, the ground 0V which is easy to handle is used. It is set (step S5 in FIG. 2). That is, in the potential information adding process in step S5, a power supply name or a ground name is added to the simulation equivalent circuit model generated in step S4.
(Signal delay simulation processing; signal delay time calculation processing)
Using the simulation equivalent circuit model created in the above process and the set voltage for the dummy pattern DP, a DC analysis (obtaining a bias point) and a transient analysis (time response of circuit operation) are performed by a circuit simulator. A signal delay time of a signal of interest is obtained from a waveform graph (a circuit input / output, a time change of an internal node voltage) showing a circuit operation obtained as a result.
[0071]
That is, using the equivalent circuit model (FIG. 4D) created in the equivalent circuit model creation process in step S4 and the setting voltage of the dummy pattern DP by the voltage setting process for the dummy pattern DP in step S5 described above, A simulation (DC analysis, transient analysis) is executed (step S6). A signal delay time is obtained from a waveform graph (circuit input / output, time change of internal node voltage) showing the circuit operation obtained after execution of step S6 (step S7).
[0072]
As the present embodiment, FIG. 5 shows a comparison result between an actually measured value of a signal delay of each signal wiring layer of a signal delay circuit actually manufactured for the signal delay circuits of the types 1 and 2 and a simulation value Sim of the present invention. I have. In FIG. 5, it can be seen that the measured value and the simulated value Sim are almost the same due to the consideration of the dummy pattern DP (the error between the simulated value Sim and the actually measured value is within about 3%). In particular, in the case of the delay circuit of the type 1 M3 signal wiring, the error between the simulation value Sim and the actually measured value was -13.6% before considering the effect of the dummy pattern DP as shown in FIG. On the other hand, after the consideration according to the present invention, the accuracy is greatly improved until the values almost match with an error of + 2.6%.
[0073]
As described above, according to the present embodiment, accurate circuit simulation can be performed in consideration of the dummy pattern DP. The error between the simulated value Sim and the actually measured value was within about 3%. In particular, in the case of the type 1 delay circuit in which the error between the simulation value Sim and the actually measured value was large when the dummy pattern DP was not considered, the error was significantly improved from -13.6% to + 2.6%. (See FIGS. 5 and 13). The circuit simulation technique of the present invention is very effective because the design accuracy of a semiconductor integrated circuit is improved. The simulation method of the present invention is applicable to the development and design of semiconductor integrated circuits such as system LSIs and flash memories that require high design accuracy. Also, by improving the design accuracy, there is a great economic effect of cost reduction such as reduction of the number of trial productions and shortening of the development period.
[0074]
In particular, when the process of the semiconductor integrated circuit is miniaturized, the influence of the wiring load on the signal delay time becomes remarkable. Therefore, the present invention exerts a great effect by being applied to a highly integrated semiconductor integrated circuit. It is.
[0075]
【The invention's effect】
As described above, according to the present invention, the equivalent circuit model for simulation includes, as load information added to each connection node, a dummy wiring that does not function as a circuit and other wirings arranged around the dummy wiring and the board. Since it includes load information that exists between conductors and semiconductors, when verifying circuit operation, the equivalent circuit model for simulation that also takes into account the wiring capacitance between the dummy pattern and signal wiring is used to reduce signal delay and other factors. Circuit simulation can be made more accurate.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a main hardware configuration of a circuit simulation system according to an embodiment of the present invention.
FIG. 2 is a flowchart showing each processing procedure by the circuit simulation system of FIG. 1;
FIGS. 3A and 3B are diagrams for explaining wiring capacitance calculation processing by numerical analysis of the present invention using an electromagnetic field equation.
4A and 4B are explanatory diagrams of Type 2 in which a plurality of same-layer signal wirings run in parallel in the signal delay measurement circuit, wherein FIG. 4A is a plan view of a layout example of forming a signal wiring load including a dummy pattern; (B) is a circuit diagram showing a position where a signal wiring load is added in (a) at a logic circuit level, (c) is an equivalent circuit diagram of a load capacitance shown simultaneously with the XX ′ cross-sectional configuration in (a), (D) is a diagram showing an equivalent circuit model of the present invention in which a dummy pattern is taken into account.
5A and 5B are diagrams illustrating comparison results of a simulation value and an actual measurement value of the present invention in a signal delay time, where FIG. 5A illustrates a delay circuit type 1 and FIG. 5B illustrates a delay circuit type 2; is there.
6A and 6B are schematic explanatory diagrams of a dummy pattern used in a conventional semiconductor integrated circuit, in which FIG. 6A is a cross-sectional view of a semiconductor device for explaining a mechanism of generating a step, and FIG. FIG. 7C is a perspective view showing a layered state of the semiconductor device for explaining flattening, and FIG. 9C is a perspective view showing a layered state of the semiconductor device for explaining formation of capacitance around a signal wiring including a parasitic capacitance caused by a dummy pattern.
7A and 7B are schematic explanatory diagrams of a physical effect of a dummy pattern used in a conventional semiconductor integrated circuit, and FIG. 7A is a schematic explanatory diagram of a shielding effect when a dummy pattern width is much larger than a signal wiring width; (B) is a diagram for explaining the effect of the dummy pattern on the same-layer signal wiring.
FIG. 8 is a sectional configuration diagram of a conventional semiconductor chip having an interlayer structure by a multilayer wiring process.
FIG. 9 is a diagram for explaining an effect of a dummy pattern on a signal wiring.
10A and 10B are explanatory diagrams of Type 1 in which a single signal wiring runs in a conventional signal delay measurement circuit, where FIG. 10A is a circuit diagram showing a position where a signal wiring load is added at a logic circuit level, and FIG. ) Is a plan view of a layout example for forming a signal wiring load, (c) is a view simultaneously showing an XX ′ cross-sectional configuration of (b) and an equivalent circuit of a load capacitance, and (d) is a signal wiring of a signal delay circuit. It is a figure showing width.
FIG. 11 is an explanatory view of type 2 in which a plurality of same-layer signal wirings run adjacent and parallel in a conventional signal delay measuring circuit, and (a) shows a position where a signal wiring load is added at a logic circuit level. (B) is a plan view of a layout example for forming a signal wiring load, (c) is a diagram simultaneously showing an XX ′ cross-sectional configuration of (b) and an equivalent circuit of a load capacitance, and (d) is FIG. 3 is a diagram illustrating signal wiring widths and line intervals of a signal delay circuit.
FIGS. 12A and 12B are explanatory diagrams of a measurement evaluation method in a conventional signal delay circuit, in which FIGS. 12A and 12B are two types of signal delay circuit diagrams when the number of stages of basic logic gates is different, and FIG. FIG. 3A is a signal waveform diagram illustrating a delay time of an input signal and an output signal of the signal delay circuit, and FIG. 4D is a signal waveform diagram illustrating a delay time of an input signal and an output signal of the signal delay circuit of FIG.
13A and 13B are diagrams illustrating comparison results between a conventional simulation value and an actual measurement value in a signal delay time, where FIG. 13A illustrates a delay circuit type 1 and FIG. 13B illustrates a delay circuit type 2; .
[Explanation of symbols]
1 Circuit simulation system
2 Simulation equivalent circuit model generator
21 ROM
22 RAM
23 Database
24 Input operation unit
25 Display
26 control unit
261 Layout processing means
262 Load information extraction means
262A Potential gradient calculating means
262B Charge amount calculation means
262C Capacity value calculation means
263 Load information providing means
264 potential information adding means
3 Circuit simulation device

Claims (8)

In a simulation equivalent circuit model generating apparatus for generating a simulation equivalent circuit model including circuit connection information to be subjected to circuit simulation and load information added to each connection node,
The simulation equivalent circuit model includes, as load information added to each of the connection nodes, a load existing between a dummy wiring that does not function as a circuit and other wiring, a conductor on a substrate, and a semiconductor disposed around the dummy wiring. An equivalent circuit model generator for simulation including information. Layout processing means for performing layout design processing in accordance with the circuit design data obtained in the circuit design processing, and arranging dummy wirings that do not function in terms of circuits in the layout design data obtained in the layout design processing;
Load information extracting means for extracting load information including a capacitance value existing between the dummy wiring arranged by the layout processing means and other wirings arranged around the dummy wiring, a conductor of the substrate and a semiconductor,
Load information providing means for providing load information existing around the dummy wiring extracted by the load information extracting means to a connection node corresponding to the circuit connection information;
An equivalent circuit model for simulation having potential information adding means for adding information indicating a power supply potential or a ground potential to a node corresponding to a connection point of the dummy wiring in the load information provided by the load information providing means; Generator. The load information extraction means,
When extracting the capacitance value between the dummy wiring and the conductor and the semiconductor around the dummy wiring in the load information,
By setting the potential of the dummy wiring to be the electrode portion of the capacitor together with the physical shape information obtained from the layout design data and the process parameter to be subjected to the circuit simulation to the ground potential or the power supply potential, the vicinity of the electrode portion surface of the capacitor Potential gradient calculating means for calculating the potential gradient of
Charge amount calculation means for calculating the charge amount on the electrode portion surface from the potential gradient calculated by the potential gradient calculation means,
3. The simulation equivalent circuit model generating apparatus according to claim 2, further comprising capacitance value calculating means for calculating a capacitance value from a potential difference between said charge amount calculated by said charge amount calculating means and said electrode portion. A circuit simulation system capable of executing a circuit simulation using a simulation equivalent circuit model generated by the simulation equivalent circuit model generation device according to claim 1. In a method for generating a simulation equivalent circuit model including circuit connection information to be subjected to circuit simulation and load information added to each connection node,
A first step of performing a circuit design process and a layout design process according to the circuit design process, and arranging a dummy wiring that does not function as a circuit in the layout design data obtained in the layout design process;
A second step of extracting load information including a capacitance value existing between the dummy wiring and another wiring arranged around the dummy wiring, a conductor of a substrate, and a semiconductor;
A third step of providing load information existing around the dummy wiring extracted in the second step to a corresponding connection node of the circuit connection information;
A fourth step of adding information indicating a power supply potential or a ground potential to a node corresponding to a connection point of the dummy wiring in the load information provided in the third step. . In the second step, when extracting, from the load information, a capacitance value between the dummy wiring and a conductor and a semiconductor around the dummy wiring, a physical shape information obtained from the layout design data and a circuit simulation target Setting the potential of the dummy wiring to be the electrode part of the capacitor together with the following process parameters to the ground potential or the power supply voltage, and calculating a potential gradient near the electrode part surface of the capacitor;
Calculating the amount of charge on the surface of the electrode unit from the potential gradient;
6. The method for generating an equivalent circuit model for simulation according to claim 5, further comprising the step of calculating a capacitance value from the charge amount and a potential difference between the electrode portions. A control program for causing a computer to execute each processing procedure in the method for generating an equivalent circuit model for simulation according to claim 5. A computer-readable recording medium on which the control program according to claim 7 is recorded.

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