CN109255167B - Method for adjusting ESD resistance between IC layout welding pads - Google Patents
Method for adjusting ESD resistance between IC layout welding pads Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The invention discloses a method for adjusting ESD resistance between IC layout welding pads, which comprises the following steps that S101, welding pads of different types of signals in a file are checked by predefined rules; step S102, defining different signal welding pad pairs and the maximum ESD resistance value between the signal welding pad pairs; step S103, respectively marking test marks on the signal welding pad and the power supply welding pad; step S104, loading a parasitic resistance parameter extraction rule file to extract parasitic parameters of the layout; step S105, executing a rule check file to generate a report; step S106, judging whether the sum of the resistance values of the metal wires of the discharge path in the area of the bonding pad to be detected is larger than the set maximum ESD resistance value or not according to the generated output report, if so, entering step S107 to reduce the resistance of the metal wires by adjusting the spacing between the bonding pads or the width of the metal wires, otherwise, entering step S108 to obtain that the ESD resistance value is within a safe value range, and improving the accuracy of automatic adjustment.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit design, in particular to a method for adjusting ESD resistance between IC layout welding pads.
Background
ESD (electrostatic discharge) is one of the important reliability issues in today's integrated circuits, and as device dimensions continue to decrease, the risk of ESD failure becomes a focus of integrated circuit design attention. It is known that when static electricity occurs, extremely high voltage pulses and instantaneous large current are generated and act on pins of a chip, and if an anti-ESD protection structure in the chip fails to release the energy in time, the chip is damaged irreversibly. Furthermore, the anti-ESD structure design of the chip depends on reasonable ESD protection circuit design and IC layout design, wherein the IC layout design is crucial, and the unreasonable IC layout often becomes the root of the failure risk of the ESD structure design. There are also standards (as shown in table 1 below) in the industry for testing the ESD capability of a chip, and there are many requirements on how to meet the ESD capability requirement and ensure that the chip size can be minimized as much as possible. The IO PAD area and its connections are critical to protect against ESD damage.
TABLE 1
As the manufacturing process advances, the spacing between parasitic devices inside the IC is also getting smaller, which makes the parasitic devices have higher Gain (Gain) and easier triggering characteristics, and the stray resistance/capacitance affects the protection function of the ESD clamp. In the advanced VLSI, the size of the chip is getting larger, and the VDD and VSS lines surrounding the whole chip are pulled longer, so the effect of the stray resistance is increased, which in turn reduces the protection effect of the ESD clamp. Therefore, designing the routing resistance of the electrostatic discharge path in the IC layout, and reducing the routing resistance of the electrostatic discharge path ESD path between the pads of each port has become a key point of ESD structure design.
The current general method is that according to the existing experience, the distance between two port welding pads cannot exceed a certain design experience value through visual inspection and calculation, and the width of a connected metal wire needs to reach a certain experience value. Therefore, the resistance between the two IO port pads is judged to be smaller than a certain standard value. However, the wiring in the IC layout is very complex, especially for advanced manufacturing process, the IC layout has multiple layers of metal and a plurality of wirings, the inspection is very complicated, and meanwhile, the visual inspection has large deviation. The conventional technical means mainly includes the following two methods to obtain the routing resistance of the ESD path of the electrostatic discharge path:
1) The calculation method is very large in error and complex in work because the calculation is needed again after the IC layout is changed.
2) The parasitic resistance parameters of the layout are extracted to carry out netlist simulation, but the simulation time for extracting the parasitic parameters is long, the labor and time cost is greatly increased, recalculation is needed after the layout is changed, and the work is complicated.
Disclosure of Invention
The invention provides an adjusting method of ESD resistance between welding pads of an IC layout, which is used for accurately and optimally checking the metal routing resistance of an electrostatic discharge path between the welding pads of each signal port on an automatic chip verification platform.
A method for adjusting ESD resistance between IC layout welding pads comprises the following steps: step 1, predefining rules to check signal pads for signal transmission and power pads for power supply in a file, wherein the signal pads comprise digital signal pads and analog signal pads, but the signal pads are not limited to the classification of the signal properties; the power supply welding pads comprise power supply welding pads and reference ground welding pads; step 2, determining a pad area of the ESD resistor to be detected based on the predefined signal pad and the predefined power pad, defining different pad signal pairs in the rule check file, and simultaneously setting a maximum ESD resistance value between two pads in the pad signal pairs; wherein the ESD resistance is a lumped parasitic resistance of a metal trace of an electrostatic discharge path between two pads in the pad signal pair; step 3, marking a test mark on a port corresponding to the signal welding pad to be detected and a port corresponding to the power supply welding pad in the welding pad area, and determining the initial position of resistance calculation of the metal routing of the electrostatic discharge path; step 4, loading a parasitic resistance parameter extraction rule file in a process library, and extracting the parameter of the lumped parasitic resistance of the metal routing of the electrostatic discharge path in the IC layout; step 5, combining the parameters of the lumped parasitic resistance extracted in the step 4, executing the rule check file, calculating the resistance of each corresponding section of metal routing on the electrostatic discharge path in the bonding pad area of the ESD resistance to be detected, and generating an output result report; and 6, checking whether the sum of the resistance of each section of metal wire is larger than the set maximum ESD resistance value in the step 2 or not according to the output result report generated in the step 5, if so, adjusting the calculated size of the metal wire in the step 5 or the distance between the welding pads in the welding pad area of the ESD resistance to be detected, and repeating the step 5 to ensure that the ESD resistance is smaller than or equal to the set maximum ESD resistance value in the step 2.
Further, the combination manner of the pad signal pairs defined in step 2 includes a combination of the signal pad and the power supply pad, a combination of the signal pad and the reference ground pad, a combination of the two signal pads, and a combination of the power supply pad and the reference ground pad.
Furthermore, the ESD resistor includes a metal routing resistor connected between the power supply pad and the reference ground pad between the two pads of the pad signal pair.
Further, in step 3, according to the definition of the test identifier, the signal types on the port corresponding to the signal pad and the port corresponding to the power pad are identified.
Further, in step 4, the parasitic resistance parameter extraction rule file is used to define resistance information of each physical layer in the IC layout.
Further, in the step 5, controlling the rule check file to be executed on the PERC chip automated verification platform.
Further, in the step 6, when the sum of the resistances of each section of metal wire is greater than the maximum ESD resistance value set in the step 2, the distance between adjacent pads in the pad area of the ESD resistor is reduced, or the width of the metal wire of the corresponding signal port is increased, so as to reduce the resistance of the corresponding metal wire.
Furthermore, the adjusting method is not limited to be applied to the routing resistance of the electrostatic discharge path of the ESD device, but also to the routing resistance in any IC layout structure similar to the electrostatic discharge path.
A computer program product loadable into the internal memory of a computer, for performing the aforementioned steps when the computer program product is run on a computer.
The invention has the advantages that on the PERC chip automatic verification platform, errors caused by manual calculation are avoided by automatically checking the ESD resistance between a signal welding pad and a power supply welding pad or similar IC layout structures in a physical layout based on an ESD protection structure device; according to the requirements of the process and the ESD standard performance, the metal wiring resistance of the electrostatic discharge path is quickly and accurately calculated by means of the extracted parasitic parameters, and the quality of the ESD structure design and the utilization rate of the chip area are improved.
Drawings
Fig. 1 is a flowchart of a method for checking ESD resistance between pads of an IC layout according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an ESD protection structure circuit to be tested according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an integrated circuit layout structure of an ESD resistor to be detected in the ESD protection structure circuit to be detected and a corresponding circuit schematic diagram provided in the embodiment of the present invention;
fig. 4 is an explanatory diagram of an output result report based on an automated chip verification platform according to an embodiment of the present invention.
Detailed Description
Specific examples of the present invention are described in detail below with reference to specific examples:
the invention provides an adjusting method of ESD resistance between IC layout welding pads, which is controlled and executed by a PERC (programmable electrical rule checking) chip automatic verification platform. The adjusting method defines and extracts the parasitic parameters of the signal port and the corresponding wiring of the ESD protection structure IC layout through the automatic chip verification platform, achieves the purpose of quickly and accurately calculating the wiring resistance of the electrostatic discharge path of the ESD device, saves the verification time and improves the verification accuracy.
In an embodiment of the present invention, an ESD protection structure circuit to be detected is provided, which is directed to an embodiment of an electrostatic discharge PATH ESD PATH of a large current in an instant when the ESD protection structure circuit occurs. As can be seen from table 1, since the common chip needs to reach the chip-level basic test standard +/-2kV of the ESD HBM (human body model), the actual routing resistance of each ESD PATH on the IC layout should be controlled within 1 Ω, and it is ensured that each ESD PATH passes the test standard of 2kV in the HBM test mode. As shown in the circuit diagram of fig. 2, there are two electrostatic discharge PATHs from the signal PAD IO PAD to the Power Clamp circuit module Power Clamp, which are a first electrostatic discharge PATH ESD PATH1 and a second electrostatic discharge PATH ESD PATH2, respectively, where the first electrostatic discharge PATH ESD PATH1 is formed by sequentially connecting a resistor R1, a first discharge device unit ESD cell1, a resistor R2, and a resistor R4 in series, and a routing resistor of the electrostatic discharge PATH is R1+ R2+ R4< =1 Ω; the second electrostatic discharge PATH ESD PATH2 is formed by sequentially connecting a resistor R1, a second discharge device unit ESD cell2, a resistor R5 and a resistor R6 in series, wherein each of the resistors represents a lumped parasitic resistor of each routing, and finally, the total resistance value is accurately calculated by the specific method provided by the invention. The track resistance of the electrostatic discharge path is R1+ R5+ R6< =1 omega. In addition, an ESD voltage is also present across the Power supply PAD VDD PAD and the ground reference PAD VSS PAD, so as to form a third electrostatic discharge PATH ESD PATH3, and since the third electrostatic discharge PATH ESD PATH3 is formed by sequentially connecting a resistor R3, a resistor R4, a Power Clamp circuit module Power Clamp, a resistor R6, and a resistor R7 in series, a routing resistance of the electrostatic discharge PATH is R3+ R4+ R6+ R7< =1 Ω.
Specifically, the adjusting method completes the fast and accurate operation and check of the routing resistance of the electrostatic discharge path in the ESD protection structure circuit provided in fig. 2 by executing the rule check file of the PERC chip automated verification platform. Firstly, defining a signal type welding pad, a power source type welding pad and an ESD energy discharge path among the signal type welding pad and the power source type welding pad in an actual IC layout in a rule check file, then extracting the rule file by loading a parasitic resistance parameter, and quickly and accurately obtaining the routing resistance of an electrostatic discharge path ESD path among an IO transmission signal-reference ground, an IO transmission signal-power supply and a reference ground-power supply on an automatic PERC chip verification platform.
Fig. 1 is a flowchart of a method for adjusting ESD resistance between pads of an IC layout, comprising the steps of:
step S101, predefined rule checks the pads of different types of signals in the file, i.e. predefined rule checks the signal pads for signal transmission and the power pads for power supply in the file. The signal PADS IO PADS are mainly divided into digital signal PADS IO PAD and analog signal PADS IO PAD according to the signal properties, but the signal PADS IO PAD are not limited to the foregoing classification of the signal properties. The power PADs comprise a power supply PAD VDD PAD and a reference PAD VSSPAD, and because a large-scale chip often has multiple power domains, the power supply PAD VDD PAD and the reference PAD VSSPAD are just one example, and can be classified and defined according to actual conditions. Then, the process proceeds to step S102.
Step S102, determining a pad area of the ESD resistor to be detected based on the signal pad and the power pad predefined in the step S101, and defining different pad signal pairs within the pad area range on the rule check file; meanwhile, the maximum ESD resistance value between two pads in the pad signal pair is set, according to the ESD measurement requirement, the power pads do not need to measure ESD (the ESD protection capability of the power pads is much stronger than that of common signal pads), and all the pads need to measure the ESD resistance of the power routing and the ground routing between the pad and each other pad, that is, the metal routing resistance corresponding to the electrostatic discharge path between two pads in the pad signal pair. According to the process requirements, the maximum ESD resistance value between the two bonding pads is set. Wherein the ESD resistance is a lumped parasitic resistance of a metal trace of an electrostatic discharge path between two pads of the pad signal pair. Specifically, the combination of the pad signal pairs includes a combination of the signal pad and the power supply pad, a combination of the signal pad and the ground reference pad, a combination of the two signal pads, and a combination of the power supply pad and the ground reference pad. Since the power pads do not need to measure ESD, there is no combination of two power supply pads. The resistance values of the routing resistors of the electrostatic discharge paths between the two welding pads of the different welding pad signal pairs are different. Then, the process proceeds to step S103.
Step S103, marking a test mark label on the port corresponding to the signal welding pad and the port corresponding to the power supply welding pad which need to be detected in the rule check file, and distinguishing the signal welding pad and the power supply welding pad, so that the PERC chip automatic verification platform can conveniently isolate the welding pad area to be detected from other chip areas, and the identification is accelerated. And identifying the signal types and ESD protection structure devices on the port corresponding to the signal welding pad and the port corresponding to the power supply welding pad according to the definition of the test identification, thereby determining the initial position of resistance calculation of the metal routing of the electrostatic discharge path. Then, the process proceeds to step S104.
And step S104, loading a parasitic resistance parameter extraction rule file in a process library, and extracting the parameter of the lumped parasitic resistance of the metal routing of the electrostatic discharge path in the IC layout. The parasitic resistance parameter extraction rule file is a parasitic parameter extraction rule file called from a process library and is used for extracting layout parasitic parameters, wherein the layout parasitic parameters comprise parasitic parameters of devices such as parasitic resistance, parasitic capacitance and coupling capacitance. The parasitic resistance parameter extraction rule file accurately defines the resistance information of each physical layer, and can be used for extracting and simulating the parasitic parameters of the actual IC layout in the subsequent steps. Then, the process proceeds to step S105.
Step S105, in combination with the parameter of the lumped parasitic resistor extracted in step S104, controlling the rule check file to be executed on the PERC chip verification platform, calculating the resistance of each corresponding metal trace on the electrostatic discharge path in the pad area of the ESD resistor to be detected, and generating an output result report, as shown in the report description diagram of fig. 4. Specifically, the ESD resistance standard operation formula R = Rs × (L/W), rs is a square resistance value of one layer of connection metal between pad areas, L is a length of the connection metal, and W is a width of the connection metal, so that the ESD resistance of two pads indirectly or a power connection line to be measured is defined as Ri = Rs × (L/W), and for a multilayer metal line between two pads, normalization processing needs to be performed on the square resistance of metals of different layers. And then proceeds to step S106.
It should be noted that, in the mainstream EDA tool for chip layout design, similar to the DRC \ LVS verification tool, PERC (programmable electrical rule checking) is also a verification tool for the reliability of circuit netlist and IC layout design. And combining the steps, and improving the accuracy of the ESD resistance verification in the chip by executing PERC rule check.
Step S106, according to the output result report generated in step S105, checking whether the sum of the resistances of each section of metal wires is greater than the maximum ESD resistance value set in step S102, that is, according to the generated output report, determining whether the sum of the resistances of the metal wires of the electrostatic discharge path in the pad area to be detected is greater than the maximum ESD resistance value set, if the output result report passes through a warning or other indication information, a rule violation that the resistance is greater than the maximum ESD resistance value set is highlighted, and then step S107 is performed, and if no corresponding rule violation warning is given, then step S108 is performed.
Step S107, adjusting the size of the signal pad or the power pad in the pad area to be detected and the metal trace of the port on which the test mark is printed in step S103 or the spacing between the pads in the pad area of the ESD resistor to be detected, specifically including reducing the spacing between adjacent pads in the pad area of the ESD resistor involved in the calculation, or increasing the width of the metal trace of the signal port involved in the calculation, thereby reducing the resistance of the corresponding metal trace. And then returning to step S105, so that the ESD resistance is less than or equal to the maximum ESD resistance set in step S102.
And S108, checking that the ESD resistance value is in a safe value range, and ending the verification and check process.
As an embodiment of the present invention, an integrated circuit layout based on an ESD resistor to be detected in the ESD protection structure circuit to be detected in fig. 2 is shown in fig. 3, one end of a first discharge device unit ESD cell1 is connected to a signal PAD IO PAD through a metal layer M1, and the other end of the first discharge device unit ESD cell1 is also connected to a power supply PAD VDD PAD through a metal layer M2; correspondingly, in the schematic circuit diagram, the diode D1 corresponds to the first discharge device unit ESD cell1, one end of the diode D1 is connected to the signal port IO through the resistor R1, and the other end of the diode D1 is connected to the power supply port through the equivalent resistor R2+ R3, so that the metal routing resistor of the electrostatic discharge path where the metal layer M1 is located is the resistor R1, and the metal routing resistor of the electrostatic discharge path where the metal layer M2 is located is the equivalent resistor R2+ R3. As can be known from the output report result generated by the automated verification platform of the PERC chip in fig. 4, for the integrated circuit layout of the ESD resistor to be detected in the ESD protection structure circuit to be detected in fig. 3, the routing resistor from the signal PAD IO PAD to the power supply PAD VDD PAD is composed of two parts, including a metal routing resistor (corresponding to the resistor R1) from the first discharge device cell ESD 1 to the signal PAD IO PAD and a metal routing resistor (corresponding to the equivalent resistors R2+ R3) from the first discharge device cell ESD cell1 to the power supply PAD VDD PAD, where the metal routing resistor (corresponding to the resistor R1) from the first discharge device cell ESD cell1 to the signal PAD IO PAD is 0.2 Ω, and the metal routing resistor (corresponding to the equivalent resistors R2+ R3) from the first discharge device cell1 to the power supply PAD VDD is 1.6 Ω, then the routing resistor between the two parts is obtained through calculation, so that the actual routing resistor of the integrated circuit layout cannot be controlled within the range of the hbpad 1 Ω, and the ESD protection structure circuit layout passes through the test mode of the hbkv and the power supply PAD. Therefore, the step S107 is required to be performed to improve the integrated circuit layout, including reducing the pitch of PAD PADs or increasing the width of metal traces, so as to reduce the resistance of metal traces, and then re-execute the rule CHECK file to implement PERC CHECK until the requirements are met.
A computer program product loadable into the internal memory of a computer, characterized in that software code portions for performing the preceding steps are adapted, when the computer program product is run on a computer. A computer program product according to the present invention stored on a computer usable medium comprises computer readable program means for causing a computer to identify pads in the integrated circuit layout, computer readable program means for causing a computer to identify pairs of pads for which the signal pads, the power pads and their corresponding pad signals are connected, computer readable program means for causing a computer to load a rule file for parasitic resistance parameter extraction in a process library, computer readable program means for causing a computer to calculate the resistance of each section of metal trace corresponding to the electrostatic discharge path in the pad area of the ESD resistance to be detected, computer readable program means for causing a computer to generate an output or report, and computer readable program means for causing a computer to determine whether the sum of the resistances of each section of metal trace in the output report result is greater than the set maximum ESD resistance value, and in particular, perform an operation of adjusting the size and pitch of the corresponding trace metal traces.
Practice proves that the adjusting method can quickly and accurately calculate the routing resistance of the discharge path of the ESD device of the integrated circuit layout, improves the calculation precision, avoids risks brought by manual calculation errors and potential risks brought by ESD damage, also avoids the tedious work brought by extracting parasitic parameters from the layout to netlist simulation, saves the research and development time of manpower projects, and integrally improves the quality of the ESD protection structure design.
The adjusting method provided by the embodiment of the invention is not limited to accurately calculating the routing resistance of the electrostatic discharge path of the ESD device of the integrated circuit layout, and the method is suitable for being applied to the routing resistance scene similar to the routing resistance scene on the accurately designed IC layout. In addition, the present invention can be used as a generic CMOS, automated ESD rule check verification platform for CMOS processes and derivatives, based on single or multiple metal layer analog and digital design layouts. It consists of an inspection tool with the executed rules to be inspected and a configuration file containing parasitic parameters that depend on the process library. The latter may be included in a chip automation verification platform for different processes, such as CMOS processes and derivatives, and be adjusted, for example, via an input screen.
The chip automation verification platform provided by the embodiment of the invention can automatically check the complete IC design layout at any design stage. The design may be an ESD protection layout, a design block, or a complete IC design, and the check verification platform may highlight all rule violations by warning or other indication.
The above embodiments are merely for full disclosure and not for limitation, and any replacement of equivalent technical features based on the gist of the present invention without inventive step should be regarded as the scope of the present disclosure.
Claims (8)
1. A method for adjusting ESD resistance between IC layout welding pads comprises the following steps: step 1, pre-defining rules to check signal pads for signal transmission and power pads for power supply in a file, wherein the signal pads comprise digital signal pads and analog signal pads, but the signal pads are not limited to the classification of the signal properties; the power supply welding pads comprise power supply welding pads and reference ground welding pads; it is characterized by also comprising: step 2, determining a pad area of the ESD resistor to be detected based on the predefined signal pad and the power pad, defining different pad signal pairs in the rule check file, and setting a maximum ESD resistance value between two pads in the pad signal pairs; wherein the ESD resistance is a lumped parasitic resistance of a metal trace of an electrostatic discharge path between two pads of the pad signal pair;
step 3, marking a test mark on a port corresponding to the signal welding pad to be detected in the welding pad area and a port corresponding to the power supply welding pad, and determining an initial position of resistance calculation of a metal wire of the electrostatic discharge path;
step 4, loading a parasitic resistance parameter extraction rule file in a process library, and extracting the parameter of the lumped parasitic resistance of the metal routing of the electrostatic discharge path in the IC layout;
step 5, combining the parameter of the lumped parasitic resistor extracted in the step 4, executing the rule check file, calculating the resistance of each corresponding section of metal wire on the electrostatic discharge path in the bonding pad area of the ESD resistor to be detected, and generating an output result report;
and 6, checking whether the total resistance of each section of metal wire is larger than the set maximum ESD resistance value in the step 2 or not according to the output result report generated in the step 5, if so, adjusting the calculated size of the metal wire in the step 5 or the distance between the welding pads in the welding pad area of the ESD resistance to be detected, and then repeatedly executing the step 5 to enable the ESD resistance to be smaller than or equal to the set maximum ESD resistance value in the step 2.
2. The adjusting method according to claim 1, wherein the combination of the pad signal pairs defined in step 2 includes a combination of the signal pad and the power supply pad, a combination of the signal pad and the reference ground pad, a combination of two signal pads, and a combination of the power supply pad and the reference ground pad.
3. The method according to claim 2, wherein the ESD resistance comprises all metal routing resistances between two pads of the pad signal pair, which are connected to the power supply pad and the reference ground pad.
4. The adjusting method according to claim 1, wherein in the step 3, the signal types on the port corresponding to the signal pad and the port corresponding to the power pad are identified according to the definition of the test identifier.
5. The adjusting method according to claim 1, wherein in the step 4, the parasitic resistance parameter extraction rule file is used for defining resistance information of each physical layer in the IC layout.
6. The tuning method of claim 1, wherein in step 5, controlling the rule check file to be executed on a PERC chip automated verification platform.
7. The adjusting method according to claim 1, wherein in the step 6, when the sum of the resistances of each section of metal traces is greater than the maximum ESD resistance value set in the step 2, the pitch between adjacent pads in the pad area of the ESD resistor is reduced, or the width of the metal trace of the corresponding signal port is increased, so as to reduce the resistance of the corresponding metal trace.
8. The adjusting method according to claim 1, wherein the adjusting method is not limited to be applied to the routing resistance of the ESD device ESD path, but is also applied to the routing resistance in any IC layout structure similar to the ESD path.
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| CN114167259A (en) * | 2021-12-07 | 2022-03-11 | 华东光电集成器件研究所 | Method for programming and testing on-off of through holes of multi-piece substrate |
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