CN116681028A - Modeling method of semiconductor device - Google Patents
Modeling method of semiconductor device Download PDFInfo
- Publication number
- CN116681028A CN116681028A CN202310530139.6A CN202310530139A CN116681028A CN 116681028 A CN116681028 A CN 116681028A CN 202310530139 A CN202310530139 A CN 202310530139A CN 116681028 A CN116681028 A CN 116681028A
- Authority
- CN
- China
- Prior art keywords
- scaling
- parameters
- candidate
- model
- equation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000012360 testing method Methods 0.000 claims abstract description 37
- 238000012795 verification Methods 0.000 claims abstract description 13
- 230000000704 physical effect Effects 0.000 claims description 3
- 238000005259 measurement Methods 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000013178 mathematical model Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/30—Computing systems specially adapted for manufacturing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Disclosed is a modeling method of a semiconductor device, including: acquiring test data, wherein the test data comprise size parameters and model parameters of semiconductor devices with different sizes, the size parameters are used for representing the sizes of the semiconductor devices, and the model parameters are parameters required for constructing an algorithm model; extracting candidate scaling parameters in the test data, the candidate scaling parameters being used to determine scaling parameters therein, the scaling parameters being size-affected ones of the model parameters; fitting according to the size parameter and the candidate scaling parameter to obtain a candidate scaling equation, wherein the candidate scaling equation is used for determining a scaling equation, and the scaling equation is used for representing a functional relation between the size parameter and the scaling parameter; verifying the candidate scaling parameters and the candidate scaling equation; when the candidate scaling parameters and the candidate scaling equations pass verification, determining the candidate scaling parameters as scaling parameters of the algorithm model, determining the candidate scaling equations as scaling equations of the algorithm model, and writing the scaling equations into the algorithm model to obtain the scaling model.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a modeling method of a semiconductor device.
Background
In the semiconductor integrated circuit manufacturing industry, a mathematical model is built on a semiconductor device, and simulation is performed on the semiconductor device to obtain an analog output result for inputting the semiconductor device. For example, for metal-oxide-semiconductor field effect transistor (MOSFET) devices, they can be simulated by Berkeley short-channel insulated gate field effect transistor model (BSIM).
Heterojunction bipolar transistor (heterojunction bipolar transistor, HBT) devices are widely used in the fields of radio frequency, communications, etc. with their high current gain and operating frequency. For HBT devices, a high current bipolar compact transistor model (high current bipolar compact transistor model, HICUM) is typically used to simulate it. However, unlike BSIM, there are no parameters related to scaling of device size in HICUM (e.g., the binding parameters in BSIM). In view of this, it is desirable to provide a scalable method of modeling HICUM in order to accurately characterize the electrical characteristics of HBT devices of different sizes.
Disclosure of Invention
The application provides a modeling method of a semiconductor device, which can solve the problem that an algorithm model of the semiconductor device provided in the related technology can not realize scaling, and comprises the following steps:
obtaining test data, wherein the test data comprise size parameters and model parameters of semiconductor devices with different sizes, the size parameters are used for representing the sizes of the semiconductor devices, and the model parameters are parameters required for constructing an algorithm model;
extracting candidate scaling parameters from the test data, wherein the candidate scaling parameters are used for determining scaling parameters, and the scaling parameters are parameters influenced by the size in the model parameters;
fitting according to the size parameter and the candidate scaling parameter to obtain a candidate scaling equation, wherein the candidate scaling equation is used for determining a scaling equation, and the scaling equation is used for representing a functional relation between the size parameter and the scaling parameter;
verifying the candidate scaling parameters and the candidate scaling equation;
and when the candidate scaling parameters and the candidate scaling equation pass verification, determining the candidate scaling parameters as the scaling parameters, determining the candidate scaling equation as the scaling equation, and writing the scaling parameters and the scaling equation into the algorithm model to obtain a scaling model.
In some embodiments, the validating the candidate scaling parameters and the candidate scaling equation comprises:
writing the candidate scaling equation into an algorithm model to obtain a candidate scaling model;
operating the candidate scaling model to obtain a first fitting result of the candidate scaling model;
when the first fitting result meets a first fitting accuracy requirement, determining that the candidate scaling equation passes verification;
sequentially running the candidate scaling models aiming at all the semiconductor devices with the sizes to obtain a second fitting result of the candidate scaling models;
and when the second fitting result meets the second fitting accuracy requirement, determining that the candidate parameters pass verification.
In some embodiments, the method further comprises:
and when the first fitting result does not meet the first fitting precision requirement, fitting according to the size parameter and the candidate scaling parameter again to obtain a new candidate scaling equation until the first fitting result meets the first fitting precision requirement, and verifying the candidate scaling equation meeting the first fitting precision requirement.
In some embodiments, the method further comprises:
and when the second fitting result does not meet the second fitting precision requirement, extracting new candidate scaling parameters from the test data again until the second fitting result meets the second fitting precision requirement, and verifying the candidate scaling parameters meeting the second fitting precision requirement.
In some embodiments, the algorithmic model is a HICUM-based model.
In some embodiments, the semiconductor device is an HBT device.
In some embodiments, the dimensional parameter includes at least one of a junction area, a perimeter, and a side length of the semiconductor device.
In some embodiments, the candidate scaling parameters are extracted from physical parameters, which are parameters of the model parameters that are related to physical effects of the semiconductor device.
The technical scheme of the application at least comprises the following advantages:
the method comprises the steps of obtaining test data comprising size parameters and model parameters of semiconductor devices with different sizes, extracting candidate scaling parameters from the test data, fitting the candidate scaling parameters to obtain candidate scaling equations according to the size parameters and the candidate scaling parameters, determining the candidate scaling parameters as scaling parameters of an algorithm model when the candidate scaling parameters and the candidate scaling equations pass verification, determining the candidate scaling equations as scaling equations of the algorithm model, and writing the scaling equations into the algorithm model to obtain the scaling model, so that the establishment of a scalable algorithm model is realized, and the electrical characteristics of the semiconductor devices with different sizes can be accurately represented.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a modeling method of a semiconductor device provided in an exemplary embodiment of the present application;
fig. 2 is a flowchart of a modeling method of a semiconductor device according to an exemplary embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
Referring to fig. 1, which shows a flowchart of a modeling method of a semiconductor device according to an exemplary embodiment of the present application, the method may be performed by a computer apparatus, as shown in fig. 1, and the method includes:
step 101, obtaining test data, wherein the test data comprises size parameters and model parameters of semiconductor devices with different sizes, the size parameters are used for representing the sizes of the semiconductor devices, and the model parameters are parameters required for constructing an algorithm model.
The model parameters in the test data are obtained by setting test patterns (usually in a matrix form) on a wafer, and measuring the test patterns, while the size parameters in the test data are determined when the test patterns are designed, so that test patterns with different sizes can be set on the same wafer, and test patterns with different sizes can also be set on different wafers.
For example, taking an HBT device as an example, it includes test patterns A1, A2, A3 of different sizes (different sizes may be different shapes, areas, junction areas, circumferences, etc.), the test patterns A1, A2, A3 are measured to obtain a measurement result of the test pattern A1, a measurement result of the test pattern A2, and a measurement result of the test pattern A3, and the measurement results of the test patterns A1, A2, A3 and respective dimensional parameters are used as test data.
Step 102, extracting candidate scaling parameters from the test data, wherein the candidate scaling parameters are used for determining scaling parameters, and the scaling parameters are parameters influenced by the size in the model parameters.
The candidate scaling parameters are pending scaling parameters, and if the candidate scaling parameters pass verification in the subsequent steps, the candidate scaling parameters can be used as formal scaling parameters of the algorithm model. In general, parameters related to physical effects of a semiconductor device (hereinafter, referred to as "physical parameters") may be affected by dimensions. For example, the physical parameter may be a model parameter describing a current, capacitance, resistance, or transit time of the semiconductor device, and the candidate scaling parameter may be extracted from the physical parameter.
And 103, fitting according to the size parameter and the candidate scaling parameter to obtain a candidate scaling equation, wherein the candidate scaling equation is used for determining a scaling equation, and the scaling equation is used for representing the functional relation between the size parameter and the scaling parameter.
The candidate scaling equation is a pending scaling equation, and can be used as a formal scaling equation of the algorithm model if the candidate scaling equation passes verification in a subsequent step. The scaling equation is used for representing a functional relationship between the size parameter and the scaling parameter, for example, the semiconductor device with the size parameter a1 has the scaling parameter x1, the semiconductor device with the size parameter a2 has the scaling parameter x2, then the functional relationship between x1 and x2 and the scaling value a1/a2 exists, and the functional relationship between the parameters can be obtained through fitting, so that a candidate scaling equation can be obtained.
Step 104, verifying the candidate scaling parameters and the candidate scaling equation.
The candidate scaling equations may be written into the algorithm model to obtain a candidate scaling model (i.e., a pending scaling model), which is run to verify the candidate scaling parameters and the candidate scaling equations. In the embodiment of fig. 2, a way to verify the candidate scaling parameters and the candidate scaling equations is given, which will not be described in detail herein.
And 105, determining the candidate scaling parameters as scaling parameters of the algorithm model, determining the candidate scaling equations as scaling equations of the algorithm model, and writing the scaling equations into the algorithm model to obtain the scaling model when the candidate scaling parameters and the candidate scaling equations pass verification.
In summary, in the embodiment of the application, by acquiring the test data including the size parameters and the model parameters of the semiconductor devices with different sizes, extracting the candidate scaling parameters from the test data, fitting the candidate scaling parameters to obtain the candidate scaling equation according to the size parameters and the candidate scaling parameters, determining the candidate scaling parameters as the scaling parameters of the algorithm model when the candidate scaling parameters and the candidate scaling equation pass verification, determining the candidate scaling equation as the scaling equation of the algorithm model, and writing the scaling equation into the algorithm model to obtain the scaling model, thereby realizing the establishment of the scalable algorithm model and accurately representing the electrical characteristics of the semiconductor devices with different sizes.
Referring to fig. 2, which shows a flowchart of a method for modeling a semiconductor device according to an exemplary embodiment of the present application, the method may be performed by a computer device, and the method may be an alternative implementation of the embodiment of fig. 1, as shown in fig. 2, and the method includes:
in step 201, test data including size parameters and model parameters of semiconductor devices of different sizes are acquired.
The method for obtaining the test data may refer to step 101 in the embodiment of fig. 1, which is not described herein.
Step 202, extracting candidate scaling parameters from the test data.
The method for extracting the candidate scaling parameters may refer to step 102 in the embodiment of fig. 1, which is not described herein.
And 203, fitting according to the size parameter and the candidate scaling parameter to obtain a candidate scaling equation.
The method of fitting to obtain the candidate scaling equation may refer to step 103 in the embodiment of fig. 1, which is not described herein.
And 204, writing the candidate scaling equation into the algorithm model to obtain a candidate scaling model.
After the candidate scaling equation is obtained, the functional relation between the size parameter and the candidate scaling parameter can be written into the algorithm model to obtain the candidate scaling model.
In step 205, a candidate scaling model is run to obtain a first fitting result of the candidate scaling model.
Step 206, detecting whether the first fitting result meets the first fitting accuracy requirement.
For example, the algorithm model is a model for inputting model parameters P1 and running to obtain a fitting result P2', and the fitting result P2' can be compared with the model parameters P2 in the test data to obtain a comparison result. In step 205 and step 206, model parameters of the semiconductor device of the running part size or model parameters of the semiconductor device of all sizes may be sampled to obtain a plurality of fitting results, the plurality of fitting results are compared with corresponding model parameters to obtain comparison results, and if a plurality of comparison results meet the accuracy requirement (for example, the comparison result greater than the preset proportion is greater than the accuracy requirement), it is determined that the first fitting result meets the first fitting accuracy requirement. If the first fitting result meets the first accuracy requirement, step 207 is entered; if the first fitting result does not meet the first accuracy requirement, step 203 is entered, and a new candidate scaling equation is obtained again according to the size parameter and the candidate scaling parameter, until the first fitting result meets the first fitting accuracy requirement, and the candidate scaling equation meeting the first fitting accuracy requirement is verified.
In step 207, the candidate scaling equation is determined to be validated.
And step 208, sequentially running the candidate scaling models aiming at the semiconductor devices with all the sizes to obtain a second fitting result of the candidate scaling models.
Step 209, detecting whether the second fitting result meets the second fitting accuracy requirement.
In step 208 and step 209, model parameters of the semiconductor device of all dimensions are run to obtain a plurality of fitting results, the plurality of fitting results are compared with corresponding model parameters to obtain comparison results, and if a majority of the comparison results (for example, the comparison results greater than a preset proportion are greater than the precision requirement) all meet the precision requirement (the precision requirement may be the same as or higher than the requirement in step 206), it is determined that the second fitting result meets the second fitting precision requirement. If the second fitting result meets the second accuracy requirement, then step 209 is entered; if the second fitting result does not meet the second accuracy requirement, step 202 is entered, new candidate scaling parameters are extracted again from the test data until the second fitting result meets the second fitting accuracy requirement, and the candidate scaling parameters meeting the second fitting accuracy requirement are verified.
Step 210, determining that the candidate scaling parameters pass verification.
Step 211, determining the candidate scaling parameters as scaling parameters of the algorithm model, determining the candidate scaling equation as scaling equation of the algorithm model, and writing the scaling equation into the algorithm model to obtain the scaling model.
It should be noted that, the algorithm model involved in the embodiment of the present application may be a HICUM-based model, and the semiconductor device involved may be an HBT device.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the application.
Claims (8)
1. A method of modeling a semiconductor device, comprising:
obtaining test data, wherein the test data comprise size parameters and model parameters of semiconductor devices with different sizes, the size parameters are used for representing the sizes of the semiconductor devices, and the model parameters are parameters required for constructing an algorithm model;
extracting candidate scaling parameters from the test data, wherein the candidate scaling parameters are used for determining scaling parameters, and the scaling parameters are parameters influenced by the size in the model parameters;
fitting according to the size parameter and the candidate scaling parameter to obtain a candidate scaling equation, wherein the candidate scaling equation is used for determining a scaling equation, and the scaling equation is used for representing a functional relation between the size parameter and the scaling parameter;
verifying the candidate scaling parameters and the candidate scaling equation;
and when the candidate scaling parameters and the candidate scaling equation pass verification, determining the candidate scaling parameters as scaling parameters of the algorithm model, determining the candidate scaling equation as scaling equation of the algorithm model, and writing the scaling equation into the algorithm model to obtain a scaling model.
2. The method of claim 1, wherein said validating said candidate scaling parameters and said candidate scaling equations comprises:
writing the candidate scaling equation into an algorithm model to obtain a candidate scaling model;
operating the candidate scaling model to obtain a first fitting result of the candidate scaling model;
when the first fitting result meets a first fitting accuracy requirement, determining that the candidate scaling equation passes verification;
sequentially running the candidate scaling models aiming at all the semiconductor devices with the sizes to obtain a second fitting result of the candidate scaling models;
and when the second fitting result meets the second fitting accuracy requirement, determining that the candidate parameters pass verification.
3. The method according to claim 2, wherein the method further comprises:
and when the first fitting result does not meet the first fitting precision requirement, fitting according to the size parameter and the candidate scaling parameter again to obtain a new candidate scaling equation until the first fitting result meets the first fitting precision requirement, and verifying the candidate scaling equation meeting the first fitting precision requirement.
4. A method according to claim 3, characterized in that the method further comprises:
and when the second fitting result does not meet the second fitting precision requirement, extracting new candidate scaling parameters from the test data again until the second fitting result meets the second fitting precision requirement, and verifying the candidate scaling parameters meeting the second fitting precision requirement.
5. The method of claims 1 to 4, wherein the algorithmic model is a HICUM-based model.
6. The method of claim 5 wherein the semiconductor device is an HBT device.
7. The method of claim 6, wherein the dimensional parameter comprises at least one of a junction area, a perimeter, and a side length of the semiconductor device.
8. The method of claim 7, wherein the candidate scaling parameters are extracted from physical parameters, the physical parameters being parameters of the model parameters that are related to physical effects of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310530139.6A CN116681028A (en) | 2023-05-11 | 2023-05-11 | Modeling method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310530139.6A CN116681028A (en) | 2023-05-11 | 2023-05-11 | Modeling method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116681028A true CN116681028A (en) | 2023-09-01 |
Family
ID=87779972
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310530139.6A Pending CN116681028A (en) | 2023-05-11 | 2023-05-11 | Modeling method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116681028A (en) |
-
2023
- 2023-05-11 CN CN202310530139.6A patent/CN116681028A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20080021689A1 (en) | Method for designing semiconductor integrated circuit and method of circuit simulation | |
| JP2007133497A (en) | Characteristic extraction method and characteristic extraction apparatus for semiconductor integrated circuit | |
| CN110674612B (en) | Modeling method for parasitic capacitance and resistance of integrated circuit process back-end interconnection | |
| JP2006178907A (en) | Circuit simulation method and device | |
| CN107239596B (en) | Finite element simulation model construction method for rail transit vehicle transformer | |
| KR100576766B1 (en) | Mehtod for designing a manufacturing process, the method for providing a manufacturing process design and computer-aided design system | |
| US8275596B2 (en) | Method for robust statistical semiconductor device modeling | |
| CN103777459A (en) | OPC (Optical Proximity Correction) verification method and method for preparing mask | |
| US20060176048A1 (en) | Generation and use of calibration data for automated test equipment | |
| CN109214023A (en) | A kind of test method and device of technological design kit | |
| CN116681028A (en) | Modeling method of semiconductor device | |
| CN108763830B (en) | Flicker noise model of semiconductor device and extraction method thereof | |
| CN108899320B (en) | MOSFET gate oxide layer capacitance calibration structure | |
| CN113449422B (en) | Method, device, equipment and storage medium for processing test data | |
| JP3420102B2 (en) | Model parameter extraction method | |
| WO2014077671A1 (en) | A method of generating spice-compatible isfet model | |
| CN108846171A (en) | Emulate the method for building up of the sub-circuit model of MOSFET temperature electrology characteristic | |
| CN114676570A (en) | Simulation model determining method, chip classifying method and related equipment | |
| CN105653805B (en) | The method of road parasitism Interconnect model after correction | |
| TW200929412A (en) | Model modification method for a semiconductor device | |
| CN109977522B (en) | Method for forming and de-embedding scalable de-embedding model | |
| CN112949241B (en) | Resistor mismatch model and extraction method | |
| US20100088655A1 (en) | Yield evaluating apparatus and method thereof | |
| CN117347839B (en) | Chip test circuit and chip | |
| CN112989743B (en) | System and method for verifying capacitor mismatch test result |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |