CN103777459A - OPC (Optical Proximity Correction) verification method and method for preparing mask - Google Patents
OPC (Optical Proximity Correction) verification method and method for preparing mask Download PDFInfo
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- CN103777459A CN103777459A CN201210413898.6A CN201210413898A CN103777459A CN 103777459 A CN103777459 A CN 103777459A CN 201210413898 A CN201210413898 A CN 201210413898A CN 103777459 A CN103777459 A CN 103777459A
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Abstract
The invention discloses an OPC (Optical Proximity Correction) verification method and a method for preparing a mask. The method comprises the following steps: providing a pattern subjected to OPC, calculating an AEI (After Etch Inspection) outline and marking an area beyond the target value error according to the pattern subjected to OPC, performing device simulation, detecting the electrical property of the simulated device, judging the advantages and disadvantages of the pattern subjected to OPC, and preparing the mask on the basis. The verification of the OPC is introduced into the aspect of directly detecting the electrical property of the device, photoetching variation with a bad effect on the production of the device can be captured, and a good foundation is laid for manufacturing a high-quality device. Meanwhile, the weak design spot can be caught according to the detection on the electrical property, and continuous improvement of a mask manufacturing process is promoted, so that the design process is effectively optimized, and the time and investment are greatly saved.
Description
Technical field
The present invention relates to integrated circuit and manufacture field, the particularly preparation method of a kind of OPC verification method and mask plate.
Background technology
The manufacturing of integrated circuit is a very complicated process, and wherein, photoetching technique is one of the most complicated technology, is also the important motivity that promotes integrated circuit technology development, the whether powerful performance that is directly determining chip of photoetching technique.
But, existing now an important problem is: due to the character of light, inevitably can produce the variation (Litho variations) of photoetching, for example, for via layer (Contact layer), can cause the position between through hole and polysilicon (Poly) to change, the shape of through hole itself also can be affected, and cause the variation of via regions, this saturation current (Saturation Current) to device, sequential (Timing), power (Power) etc. has certain impact, at present, manufacture of semiconductor technique develops below towards 32/28nm, but lithographic equipment but still rests on this size of 193nm, this species diversity just more easily causes the variation of photoetching so, thereby cause pattern quality to produce very large variation, the impact namely above-mentioned electrical property being produced be can not ignore.
The variation of photoetching can cause the hydraulic performance decline of device, thereby affects the quality of the devices such as SRAM, as the impact on function and the impact on performance (such as stability, literacy etc.).For this reason, industry is in the time adopting OPC process to prepare mask plate, also introduce the proof procedure of a step OPC, be commonly referred to Post OPCverification, but current OPC verification method is only for the pattern that can be formed on the figure on silicon chip, specifically please refer to Fig. 1, first the OPC checking of existing technique provides the pattern after OPC, for needed operation, as photoetching, etching technics is selected lithography model, photoresistance model (unlisted in figure) or etching model are verified the pattern of the figure after this technique, even to detect ADI(After DevelopmentInspection) after pattern, adopt lithography model, if detect AEI(After Etch Inspection) after pattern, selective etching model, the structure of the pattern after detection computations afterwards, such as whether there being bridging (Bridge), fracture (Pinch), the coverage rate (Contact coverage) of through hole, size abnormal (CDvariation), line segment shortening (Line end shortening) etc., and testing result is exported.In fact, this checking is to capture the device performance variation that the variation of photoetching causes.
Summary of the invention
The object of the present invention is to provide the preparation method of a kind of OPC verification method and mask plate, to solve the problem that the variation of device electrical performance can not be detected in prior art to the checking of OPC.
For solving the problems of the technologies described above, the invention provides a kind of OPC verification method, comprising:
Pattern after OPC is provided;
Calculate AEI profile according to the pattern after described OPC, and mark the region that exceeds desired value error;
By simulator, described AEI profile is carried out to device simulation;
Detect the electrical property of the device after simulation;
Output detections result.
Optionally, for described OPC verification method, according to combined process model in the step of the pattern calculating AEI profile after described OPC.
Optionally, for described OPC verification method, described process modeling comprises in conjunction with photoetching and the model based on etching rule or etching model.
Optionally, for described OPC verification method, described in exceed desired value error region comprise following factor: the shape of the distance between through hole and gate line, the size of through hole or through hole.
Optionally, for described OPC verification method, described device simulation goes out distance, the size of through hole or the shape of through hole between described through hole and gate line for the regional simulation that exceeds desired value error.
Optionally, for described OPC verification method, detect the relevant electrical property of distance, the size of through hole or the shape of through hole between described through hole and gate line.
Optionally, for described OPC verification method, before detecting the electrical property of the device after simulation, set electrical property threshold value.
Optionally, for described OPC verification method, described electrical property comprises one or more in resistance, electric capacity, saturation current, leakage current, sequential or power.
The preparation method who the invention provides a kind of mask plate, comprising:
Substrate is provided;
Pattern after utilizing OPC verification method as above to OPC detects, and prepared by the pattern after described OPC on described substrate to form mask plate if testing result is qualified.
Compared with prior art, in the preparation method of OPC verification method provided by the invention and mask plate, the checking of OPC is incorporated into this direction of electrical property of direct-detection device, can capture the production of device is had to dysgenic photoetching variation, lay preferably basis for manufacturing good device, simultaneously according to capturing design of thin weakness to the detection of electrical property, be conducive to the lasting improvement of mask plate manufacturing process, thereby effectively optimize design process, saved greatly time and contributed capital.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of the OPC verification method of existing technique;
Fig. 2 is the preparation method's of the mask plate of the embodiment of the present invention process flow diagram;
Fig. 3 is the schematic diagram of selecting the AEI profile of wanting mark in preparation method's process of mask plate of the embodiment of the present invention;
Fig. 4 is the schematic diagram that carries out mark after detecting on affecting the pattern of electrical property.
Embodiment
Below in conjunction with the drawings and specific embodiments, the preparation method of OPC verification method provided by the invention and mask plate is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 2 ~ Fig. 4, the pattern after OPC is provided; Calculate AEI(After Etch Inspection according to the pattern after described OPC) pattern, it is shown structure on silicon chip after etching, and marking the region that exceeds desired value error, described desired value error can be set by technological requirement or industry experience.In order can effectively to operate, also need combined process model to calculate AEI profile.
The embodiment of the present invention adopts in conjunction with photoetching and the model based on etching rule or etching model, that is to say, what need is the model that can show the situation after etching, on this basis, observable AEI profile, and mark the following region that exceeds desired value error: can be the abnormal region of distance between through hole and gate line (gate line), region of the region that the size of through hole is abnormal or the shape anomaly of through hole etc., as shown in Figure 3, distance between through hole 311 and gate line (gate line) 312 is 31.50nm, and normal condition should be 33.00nm, should carry out mark to first area 31, in second area 32, the size of through hole 321 is less than normal size (not tangent with its outer quadrilateral), should carry out mark, in the 3rd region 33, through hole 331 be shaped as ellipse, normally should be circle, as shown in the dotted portion in through hole 332 or through hole 331, also should carry out mark, Fig. 3 is symbolistic being illustrated, rather than exhaustive, as being distance between adjacent through-holes etc., due in manufacture process, this region, a few place can cause device to be affected, make its hydraulic performance decline, can avoid or reduce impact therefore detect targetedly in advance.
Then adopt simulator to carry out device simulation to described AEI profile, especially described in will simulating, exceed the region of desired value error, here can adopt TCAD instrument, simulate according to the region that exceeds desired value error, go out distance, the size of through hole or the shape of through hole between described through hole and gate line for the regional simulation that exceeds desired value error.Preferably, also described region peripheral part that exceeds desired value error should be combined and simulates, thereby obtain more complete device architecture, in order to obtain its concrete structure, need to simulate the 2D(two dimension in the region that exceeds desired value error) structural drawing and 3D(three-dimensional) structural drawing, this also can conveniently calculate the correlation parameter that the structure drawn up with diagnostic cast has.
After simulation, need to detect the electrical property of the device simulating, this is also the embodiment of the present invention is defined as the model that can show the situation after etching reason to process modeling, if be merely lithography model, whether the physical form that is merely able to so measured pattern exists extremely, can bring which kind of impact to the final performance of device and can not understand relevant shape in depth.
Distance, the size of through hole or the relevant electrical property of the shape of through hole between through hole and the gate line simulating described in detection, specifically can comprise: one or more in resistance (resistance), electric capacity (capacitance), saturation current (saturation current), leakage current (leakage), sequential (timing) or power (power) etc., can certainly increase relevant detected object for different technological requirements or knowhow.Can be preferably and need to design a form, in table, mark the detected object of relevant range, the specification threshold value (specification) that described detected object should have in this region, as shown in Table 1, described specification is to set according to production technology and/or customer requirement, is recorded in afterwards its actual performance of this region.
Table one
Can effectively capture design of thin weakness to the detection of electrical property, be conducive to the lasting improvement of mask plate manufacturing process, the problem that can also find, improve or prevent some to occur in subsequent device manufacture process, thus the competitive power of production technology and the performance of product improved.
After detecting, obtain the related data of testing result, and mark the influential part of device performance in pattern after described OPC, as shown in Figure 4, in second area 32 because the irregular meeting of through hole 321 causes leakage current OOS(out of spec.), in pattern by through hole 321 marks.For the ease of showing intuitively the influence degree to which kind of performance of device, different figures and color can be set and be distinguished, in Fig. 4, leakage current is represented by rectangle, black represents that impact is very large.
Testing result (data and after testing after described OPC after pattern) can be analyzed by related personnel, can meet the needs of production with judgement, if described electrical property is all qualified, show that the pattern after described OPC meets the requirements, just can carry out the preparation of mask plate.This can adopt existing equipment, and substrate is provided, for example, can be quartz base plate, and the design producing after qualified described detection OPC is become to mask plate.
In the OPC verification method that above-described embodiment provides and the preparation method of mask plate, the checking of OPC is incorporated into this direction of electrical property of direct-detection device, can capture the production of device is had to dysgenic photoetching variation, lay preferably basis for manufacturing good device, simultaneously according to capturing design of thin weakness to the detection of electrical property, be conducive to the lasting improvement of mask plate manufacturing process, thereby effectively optimize design process, saved greatly time and contributed capital.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to including these changes and modification.
Claims (9)
1. an OPC verification method, is characterized in that, comprising:
Pattern after OPC is provided;
Calculate AEI profile according to the pattern after described OPC, and mark the region that exceeds desired value error;
By simulator, described AEI profile is carried out to device simulation;
Detect the electrical property of the device after simulation;
Output detections result.
2. OPC verification method as claimed in claim 1, is characterized in that, according to combined process model in the step of the pattern calculating AEI profile after described OPC.
3. OPC verification method as claimed in claim 2, is characterized in that, described process modeling comprises in conjunction with photoetching and the model based on etching rule or etching model.
4. OPC verification method as claimed in claim 1, is characterized in that, described in exceed desired value error region comprise following factor: the shape of the distance between through hole and gate line, the size of through hole or through hole.
5. OPC verification method as claimed in claim 4, is characterized in that, described device simulation goes out distance, the size of through hole or the shape of through hole between described through hole and gate line for the regional simulation that exceeds desired value error.
6. OPC verification method as claimed in claim 4, is characterized in that, detects the relevant electrical property of distance, the size of through hole or the shape of through hole between described through hole and gate line.
7. OPC verification method as claimed in claim 1, is characterized in that, before detecting the electrical property of the device after simulation, sets electrical property threshold value.
8. OPC verification method as claimed in claim 7, is characterized in that, described electrical property comprises one or more in resistance, electric capacity, saturation current, leakage current, sequential or power.
9. a preparation method for mask plate, is characterized in that, comprising:
Substrate is provided;
Pattern after utilizing OPC verification method as any one in claim 1 ~ 8 as described in to OPC detects, if testing result qualified by the pattern preparation after described OPC on described substrate with formation mask plate.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107003603A (en) * | 2015-06-30 | 2017-08-01 | 格罗方德半导体公司 | Photoetching simultaneously and the method for etching correcting process |
| CN108009352A (en) * | 2017-11-30 | 2018-05-08 | 上海华力微电子有限公司 | A kind of filling flow of lithography layout and the design method of photo etched mask |
| CN108681205A (en) * | 2018-06-13 | 2018-10-19 | 上海华力微电子有限公司 | The OPC verification method of area of grid |
| CN109752918A (en) * | 2017-11-07 | 2019-05-14 | 长鑫存储技术有限公司 | Photoetching mask optimization design method and system |
| CN110765724A (en) * | 2019-10-26 | 2020-02-07 | 东方晶源微电子科技（北京）有限公司 | Mask optimization method and electronic equipment |
| CN113408236A (en) * | 2020-02-28 | 2021-09-17 | 中芯国际集成电路制造（天津）有限公司 | Process detection method, system, device and storage medium |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101807219A (en) * | 2008-02-28 | 2010-08-18 | 台湾积体电路制造股份有限公司 | Method for shape and timing equivalent dimension extraction |
| CN102169516A (en) * | 2010-02-26 | 2011-08-31 | 台湾积体电路制造股份有限公司 | Integrated circuit method |
-
2012
- 2012-10-25 CN CN201210413898.6A patent/CN103777459A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101807219A (en) * | 2008-02-28 | 2010-08-18 | 台湾积体电路制造股份有限公司 | Method for shape and timing equivalent dimension extraction |
| CN102169516A (en) * | 2010-02-26 | 2011-08-31 | 台湾积体电路制造股份有限公司 | Integrated circuit method |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107003603A (en) * | 2015-06-30 | 2017-08-01 | 格罗方德半导体公司 | Photoetching simultaneously and the method for etching correcting process |
| CN107003603B (en) * | 2015-06-30 | 2021-07-20 | 格芯(美国)集成电路科技有限公司 | Method for simultaneous photolithography and etching correction process |
| CN109752918A (en) * | 2017-11-07 | 2019-05-14 | 长鑫存储技术有限公司 | Photoetching mask optimization design method and system |
| CN108009352A (en) * | 2017-11-30 | 2018-05-08 | 上海华力微电子有限公司 | A kind of filling flow of lithography layout and the design method of photo etched mask |
| CN108681205A (en) * | 2018-06-13 | 2018-10-19 | 上海华力微电子有限公司 | The OPC verification method of area of grid |
| CN108681205B (en) * | 2018-06-13 | 2021-05-14 | 上海华力微电子有限公司 | OPC verification method for grid region |
| CN110765724A (en) * | 2019-10-26 | 2020-02-07 | 东方晶源微电子科技（北京）有限公司 | Mask optimization method and electronic equipment |
| CN113408236A (en) * | 2020-02-28 | 2021-09-17 | 中芯国际集成电路制造（天津）有限公司 | Process detection method, system, device and storage medium |
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Application publication date: 20140507 |