CN102540773B - Novel method for inspecting photolithographic process by utilizing optical proximity correction (OPC) models of post exposure bake - Google Patents
Novel method for inspecting photolithographic process by utilizing optical proximity correction (OPC) models of post exposure bake Download PDFInfo
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- CN102540773B CN102540773B CN201110250286.5A CN201110250286A CN102540773B CN 102540773 B CN102540773 B CN 102540773B CN 201110250286 A CN201110250286 A CN 201110250286A CN 102540773 B CN102540773 B CN 102540773B
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Abstract
The invention discloses a novel method for inspecting a photolithographic process by utilizing optical proximity correction (OPC) models of a post exposure bake, which comprises the steps of establishing the photolithographic process and determining conditions of the photolithographic process; collecting data of an original photolithography territory; determining the bake maximum temperature, exposing and baking photoresist, collecting data of the post exposure bake and establishing a first OPC model; determining the bake minimum temperature, exposing and baking the photoresist, collecting data of the minimum temperature of the post exposure bake and establishing a second OPC model; and respectively performing photolithography rule inspection on the first OPC model and the second OPC model by utilizing the data of the original photolithography territory, and determining whether photolithography defects exist. By establishing OPC models at different temperatures of post exposure, changes of graphs after photoetching at the different temperatures can be determined, and the temperature can be further regulated when the defects or dimension changes have serious problems to establish novel process conditions.
Description
Technical field
The present invention relates to a kind of method of checking photoetching process, relate in particular to a kind of method of the novel OPC model testing photoetching process of utilizing postexposure bake.
Background technology
In advanced photoetching process, postexposure bake (Post Exposure Bake is called for short PEB) is a very important step.The variation of baking temperature can affect the lithographic feature size of final imaging, is called postexposure bake susceptibility (PEB Sensitivity).In the time newly setting up photoetching process, need to make assessment to this influence degree.Existing way is the temperature that changes postexposure bake, selects one or more be concerned about characteristic dimensions, and the live width of carrying out under electron microscope measures, and can observe like this change in size of one or more characteristic dimensions in the time that skew occurs postexposure bake temperature.But for potential issuable photomask defect in whole domain and lithography rules mistake, cannot detect.
Summary of the invention
For the problem of above-mentioned existence, the object of this invention is to provide a kind of method of optical approach effect model (OPC model) the inspection photoetching process of utilizing postexposure bake, OPC model after exposing by foundation under different baking temperatures, can determine the variation that after photoetching, figure produces in the time that temperature is different, and by carrying out comparing calculation with original design configuration, thereby pre-determine the variation defect of the litho pattern that temperature variation may cause, and data accordingly, redefine photoetching process condition, constantly improve photoetching process.
The object of the invention is to be achieved through the following technical solutions:
A method for the novel OPC model testing photoetching process of utilizing postexposure bake, wherein, comprises the following steps:
Set up photoetching process, determine photoetching process condition;
Gather the primary light diagram data of cutting blocks for printing;
Determine a baking ceiling temperature, on substrate, smear one deck photoresist and described photoresist is exposed, toasted, gather the data of toasting obtained litho pattern after photoresist exposure under ceiling temperature condition, set up an OPC model;
Determine a baking lower limit temperature, on substrate, smear photoresist described in one deck described photoresist is exposed, toasted, gather the data of toasting obtained litho pattern after photoresist exposure under lower limit temperature condition, set up the 2nd OPC model;
Utilize the primary light diagram data of cutting blocks for printing, respectively a described OPC model, described the 2nd OPC model are carried out to litho-rule checking, and whether definite primary light diagram data of cutting blocks for printing there is photomask defect.
The method of the above-mentioned novel OPC model testing photoetching process of utilizing postexposure bake, wherein, the ceiling temperature of described postexposure bake, lower limit temperature are respectively that normal baking temperature fluctuates 10 DEG C.
The above-mentioned novel OPC model testing photoetching technological method that utilizes postexposure bake, wherein, sets up in lithographic process steps described, and described definite process conditions comprise and pre-determine the required temperature value of a postexposure bake.
Compared with the prior art, beneficial effect of the present invention is:
The present invention is by setting up the corresponding OPC model based on different postexposure bake temperature: issuable postexposure bake upper temperature limit is set up to an OPC model; Issuable postexposure bake lowest temperature is set up to an OPC model.Then by utilize these two groups of OPC models to carry out emulation and litho-rule checking (LRC) to whole domain, can detect, in whole layout area, in the time that contingent postexposure bake temperature changes, whether lithographic feature size variation range exceedes requirement or has or not specific photomask defect to produce.
And, change according to determined defect the photoetching process condition of constantly correcting, make the postexposure bake sensitivity (PEB Sensitivity) of etching condition and selected photoresist be in top condition, increase lithographic process window, guarantee to occur when abnormal in lithographic equipment postexposure bake temperature, can not produce the photomask defect of large impact and the yield that exerts an influence on lithographic feature size.Baking temperature after photolithographic exposure is changed to the photomask defect producing, set up the OPC model after temperature variation according to this method, can successfully in litho-rule checking, be detected.
Brief description of the drawings
Fig. 1 is a kind of structural representation of method of the novel OPC model testing photoetching process of utilizing postexposure bake.
Fig. 2 is a kind of process flow diagram of method of the novel OPC model testing photoetching process of utilizing postexposure bake.
Embodiment
Below in conjunction with schematic diagram and concrete operations embodiment, the invention will be further described.
As shown in Figure 2, the method flow diagram of the OPC model testing photoetching process of postexposure bake that what a kind of the present invention of the present invention was novel utilize, wherein, comprises the following steps:
S1: set up photoetching process, determine photoetching process condition;
In this step, according to the needs of photoetching, pre-determine the technological parameter of photoetching, comprise and pre-determine the required temperature value of photoresist postexposure bake in photoetching process under normal process flow.
S2: gather the primary light diagram data of cutting blocks for printing;
In this step, determine the design configuration that needs photoetching to form, gather and determine this primary light diagram data of cutting blocks for printing, the primary light the gathering diagram data of cutting blocks for printing at least comprises the data message such as critical size (CD) of original lithography layout, and original lithography layout is normal production or the lithography layout of flow mask plate used;
S3: determine a baking ceiling temperature, smear one deck photoresist and photoresist is exposed, toasted on substrate, gather data, the emulation of postexposure bake, set up an OPC model;
In this step, the temperature value required according to predetermined postexposure bake, determine the temperature value of the upper limit of its temperature variation that may occur in baking, then using this ceiling temperature value as lithographic equipment temperature, at this temperature, on substrate, smear photoresist, and carry out the aligning of photoresist, exposure, baking, a series of lithographic process steps such as development, obtain a litho pattern, and under based on ceiling temperature condition, what gather litho pattern that photoresist postexposure bake forms or pattern at least comprises the data messages such as critical size, an optical approach effect model (OPC model)---an OPC model is set up in emulation, the critical size of now setting up the lithography layout that OPC model test mask plate used comprises approaches the critical size of the lithography layout of normal flow mask plate used haply.In photoetching process, generally, the normal postexposure bake temperature of photoresist is conventionally at 90 DEG C to 130 DEG C, and the scope of the measurable side-play amount of the baking temperature of equipment is generally in +/-10 degree left and right, thereby ceiling temperature can be chosen in the 10 DEG C of left and right of roughly floating under the condition of normal temperature that photoresist carries out postexposure bake.
S4: determine a baking lower limit temperature, smear one deck photoresist on substrate photoresist is exposed, toasted, gather postexposure bake lower limit temperature data, emulation, set up the 2nd OPC model;
In this step, take with step S3 in same method, the temperature value required according to predetermined postexposure bake, determine the temperature value of the lower limit of its temperature variation that may occur in baking, then using this lower-limit temperature value as lithographic equipment temperature, at this temperature, on substrate, smear photoresist, and carry out the aligning of photoresist, exposure, baking, a series of lithographic process steps such as development, obtain another litho pattern, and adopt and the data of postexposure bake, emulation is set up an optics and is closed on model (OPC model)---the 2nd OPC model, an OPC model is identical with setting up, now utilize the critical size of the lithography layout that modeling test mask plate used comprises to approach haply the critical size of the lithography layout of normal flow mask plate used.And lower limit temperature can be chosen in-10 DEG C of left and right of roughly floating under the condition of normal temperature that photoresist carries out postexposure bake.
In addition, as other selection mode (but and without restriction), upper and lower limit temperature can be got the arbitrary temp between 0 DEG C ~ 200 DEG C.
S5: utilize the primary light diagram data of cutting blocks for printing, respectively an OPC model, the 2nd OPC model are carried out to litho-rule checking, determine whether to exist photomask defect, mainly to utilize these two groups first, second OPC models to carry out emulation and litho-rule checking to whole original layout, when photoresist postexposure bake temperature changes, whether the lithographic feature size variation range that detects the photoengraving pattern forming on photoresist exceedes requirement or has or not specific photomask defect to produce.
In this step, as shown in Figure 1, according to the needs of photoetching process, determine litho-rule checking condition, utilize the primary light i.e. figure of design in advance of diagram data 1 of cutting blocks for printing, cut blocks for printing diagram data 1 and an OPC model 2 of primary light carried out to litho-rule checking, thereby can clearly determine in the time of ceiling temperature value, the variation of the litho pattern generation size of estimating, and can judge accordingly whether this change in size exceedes acceptable scope or no generation other defect;
Same principle and method, utilize the primary light diagram data 1 of cutting blocks for printing, this figure and the 2nd OPC model (not indicating in figure) are carried out to litho-rule checking, thereby can clearly determine in the time of lower-limit temperature value, the variation of the litho pattern generation size of estimating, and can judge accordingly whether this change in size exceedes acceptable scope or no generation other defect;
S6: according to step S5, S6, determine whether defectiveness or change in size, if so, need to detect the potential domain that affected by postexposure bake, have very serious problem once defect or change in size, need further to adjust temperature; If not, process certification completes, and photoetching process condition is defined as determined condition in step S1.
Above specific embodiments of the invention be have been described in detail, but the present invention is not restricted to specific embodiment described above, it is just as example.To those skilled in the art, any to this equivalent modifications of carrying out and alternative also all among category of the present invention.Therefore, equalization conversion and the amendment done without departing from the spirit and scope of the invention, all should contain within the scope of the invention.
Claims (3)
1. a method of utilizing the OPC model testing photoetching process of postexposure bake, is characterized in that, comprises the following steps:
Set up photoetching process, determine photoetching process condition;
Gather the primary light diagram data of cutting blocks for printing;
Determine a baking ceiling temperature, on substrate, smear one deck photoresist and described photoresist is exposed, toasted, gather the data of toasting obtained litho pattern after photoresist exposure under ceiling temperature condition, set up an OPC model;
Determine a baking lower limit temperature, on substrate, smear photoresist described in one deck described photoresist is exposed, toasted, gather the data of toasting obtained litho pattern after photoresist exposure under lower limit temperature condition, set up the 2nd OPC model;
Utilize the primary light diagram data of cutting blocks for printing, respectively a described OPC model, described the 2nd OPC model are carried out to litho-rule checking, and whether definite primary light diagram data of cutting blocks for printing there is photomask defect; Wherein, utilize the primary light diagram data of cutting blocks for printing, its figure and an OPC model are carried out to litho-rule checking, determine the variation of its figure generation size in the time of ceiling temperature value, and judge whether this change in size exceedes acceptable scope or no generation other defect; Utilize the primary light diagram data of cutting blocks for printing, its figure and the 2nd OPC model are carried out to litho-rule checking, determine the variation of its figure generation size in the time of lower-limit temperature value, and judge whether this change in size exceedes acceptable scope or no generation other defect;
Determine whether defectiveness or change in size, if so, need to detect the potential domain that affected by postexposure bake, in the time that layout size variation exceedes acceptable scope or produces other defect, need further to adjust temperature; If not, process certification completes, and photoetching process condition is defined as determined condition in above-mentioned first step.
2. the method for the OPC model testing photoetching process of utilizing postexposure bake according to claim 1, is characterized in that, the ceiling temperature of described postexposure bake, lower limit temperature are respectively that normal baking temperature fluctuates 10 DEG C.
3. the OPC model testing photoetching technological method that utilizes postexposure bake according to claim 1, is characterized in that, sets up in lithographic process steps described, and described definite process conditions comprise and pre-determine the required temperature value of a postexposure bake.
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| CN103311103B (en) * | 2013-04-28 | 2016-08-31 | 上海华力微电子有限公司 | The territory map layer design method of semiconductor chip and mask plate thereof |
| CN103309149B (en) * | 2013-06-08 | 2016-03-23 | 上海华力微电子有限公司 | Optical proximity correction method |
| CN103645612B (en) * | 2013-11-29 | 2015-08-05 | 上海华力微电子有限公司 | Photoetching process graphic defects detection method |
| CN105093863A (en) * | 2015-08-20 | 2015-11-25 | 上海华力微电子有限公司 | Postexposure baking method of photolithography technique |
| CN110286568A (en) * | 2019-05-15 | 2019-09-27 | 上海华力集成电路制造有限公司 | The choosing method of the optimum temperature of postexposure bake in photoetching process |
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| US7003758B2 (en) * | 2003-10-07 | 2006-02-21 | Brion Technologies, Inc. | System and method for lithography simulation |
| US7494752B2 (en) * | 2005-02-11 | 2009-02-24 | Lsi Corporation | Method and systems for utilizing simplified resist process models to perform optical and process corrections |
| CN101305320B (en) * | 2005-09-09 | 2012-07-04 | Asml荷兰有限公司 | System and method for mask verification using an individual mask error model |
| TW200739672A (en) * | 2006-04-03 | 2007-10-16 | Promos Technologies Inc | Method for shrinking opening sizes of a photoresist pattern |
| US7743357B2 (en) * | 2006-05-31 | 2010-06-22 | Synopsys, Inc. | Method and apparatus for determining a process model that models the impact of CAR/PEB on the resist profile |
| JP2009290110A (en) * | 2008-05-30 | 2009-12-10 | Toshiba Corp | Size control method |
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