KR101143622B1 - Method for verifying optical proximity correction - Google Patents

Abstract

An optical proximity correction verification method is presented. According to the present invention, the original layout of the target patterns is designed, and optical proximity effect correction is performed. Obtain a simulated contour for the calibrated layout, obtain data of the difference values at the evaluation points between the simulation contour and the original layout, and plot the layout of the pseudo wafer image that reflects the data of the difference values. Write. The data of the layout of the wafer image is verified by design rule check.

OPC, Model Base Access, Rule Base Access, Polygon, DRC

Description

Method for verifying optical proximity correction

1 is a diagram schematically illustrating a typical rule based checking method.

FIG. 2 is a diagram schematically illustrating a typical model based checking method.

3 to 7 are schematic views illustrating an optical proximity correction verification method according to an exemplary embodiment of the present invention.

8 is a flowchart schematically illustrating an optical proximity correction verification method according to an exemplary embodiment of the present invention.

9 to 11 are diagrams schematically illustrating a modified example of the optical proximity correction verification according to the embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for verifying optical proximity correction (OPC) when fabricating a photo mask.

 As the degree of integration of semiconductor devices increases, the size of patterns required for the devices is rapidly reduced. Accordingly, the distortion phenomenon during the transfer of the pattern is severed due to the limitation of the resolution in the lithography process for forming the pattern. Accordingly, techniques for improving optical proximity effect (OPC) and resolving power as a method of overcoming the limitations of the lithography process (RET) have been proposed.

OPC may be understood to correct the layout of a target pattern to be transferred onto the wafer in consideration of the optical proximity effect (OPE). Such OPC can be considered roughly into a rule-based approach and a model-based approach.

The rule base approach is an approach that replaces the segments that make up a pattern, for example, depending on the size of the pattern shape and its associated environments. Can be understood. The model-based approach prepares a model of the pattern transfer process, uses this model to simulate an image to be actually printed on the wafer, and desired wafer for such simulated image. It can be understood in a manner of comparative matching with an image. At this time, a technique for verifying whether the OPC is properly performed on the result obtained after performing the OPC is also recognized as an important technique along with the OPC technique.

1 is a schematic diagram illustrating a typical rule based checking method.

Referring to FIG. 1, when validating patterns 11 and 13 of an original layout or an OPC layout designed according to a goal to be implemented, a design rule check (DRC) As described above, a physical dimension checking method for verifying by a specified rule is used.

The DRC sets a point 15 to evaluate and calculates the line widths of the patterns 11 and 13 or calculates the spacing interval at the set point 15 to the rule in which such calculation is provided. Judge whether it is a match.

However, such a physical dimension checking method has become difficult to ensure accurate yield as the critical size of the pattern is reduced. In addition, more and more complex OPC techniques have been incorporated to meet these physical dimension checks. Therefore, verification of the full chip region according to the model base approach is introduced rather than the OPC according to the rule base approach including such physical dimension check.

FIG. 2 is a diagram schematically illustrating a typical model based checking method.

Referring to FIG. 2, the OPC according to the model base approach includes a model base verification method such as grid base OPC verification. The model-based approach first obtains a model of the pattern transfer process, then scales or calibrates the evaluation points to be simulated for the model, and then calculates the pattern 21 of the calibrated layout and Comparing the contour contour (simulated contour 23) of the simulated layout to obtain an OPC recipe (recipe), and reflects this OPC layout, and includes a process of verifying the OPC layout.

This model-based approach achieves very good accuracy because the grid is partitioned into smaller segments and the verification procedure is performed for all evaluation points representing all these grids. Nevertheless, the verification is performed for all the grids, so there is a vulnerability in that this process takes a lot of time, resulting in a drastic decrease in throughput.

Therefore, there is a demand for developing an OPC method that can complement the model-based approach and the rule-based approach.

An object of the present invention is to provide an optical proximity effect correction method capable of realizing higher accuracy and faster verification speed.

One aspect of the present invention for achieving the above technical problem, the step of designing the original layout of the target pattern, performing the optical proximity effect correction for the original layout, the simulated contour (simulated contour) for the corrected layout ), Obtaining data of difference values between the simulation contour line and the original layout, creating a layout of the virtual wafer image reflecting the data of the difference values, and designing data of the layout of the wafer image. An optical proximity effect correction verification method including verifying with a design rule check is provided.

The optical proximity effect correction may be performed by a model based approach.

And calibrating the corrected layout into grids represented by the evaluation points to set an evaluation point from which the data of difference values are obtained.

The method may further include applying the data of the difference values for the evaluation points to the correction layout to create a layout of the virtual wafer image composed of a combination of polygons.

The design rule check verification may be performed to verify whether a line width of a pattern included in the layout of the virtual wafer image and a spaced interval between patterns are in conflict with a set rule.

According to the present invention, there is provided an optical proximity effect correction method that can complement the model base approach and the rule base approach to complement the weakness of the grid base approach and the accuracy of the physical dimension check approach. Can present

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it should not be construed that the scope of the present invention is limited by the embodiments described below. Embodiments of the invention are preferably to be interpreted as being provided to those skilled in the art to more fully describe the invention.

In the embodiment of the present invention, a model representing the pattern transfer process is appropriately obtained by using the result of transferring the pattern on the wafer according to the model base approach, and the layout obtained by OPC with respect to the original layout of the target pattern is obtained. The OPC is then calibrated to simulate the model and the model is simulated to obtain a simulated contour. Then, the difference between the simulation contour line and the original layout of the target pattern is calculated for each evaluation point.

Using the data of the difference, the layout of the pseudo wafer image is made of a combination of a plurality of polygons, and the second original layout is set. The suitability of the OPC is verified by applying DRC to the data or database of the second original layout.

3 to 7 are schematic views illustrating an optical proximity correction verification method according to an exemplary embodiment of the present invention. 8 is a flowchart schematically illustrating an optical proximity correction verification method according to an exemplary embodiment of the present invention.

3 and 8, an OPC method according to an embodiment of the present invention first designs an original layout 100 including target patterns to be transferred and implemented on a wafer, as shown in FIG. 3. (801 of FIG. 8). The original layout 100 may be understood as a layout that directly reflects the shapes of the actual target patterns.

4 and 8, for this original layout 100, an OPC layout 101 is obtained according to the model-based OPC approach (803 of FIG. 8).

For example, a pattern transfer process for implementing target patterns of the original layout 100 on an actual wafer, that is, a wafer detailed actual photograph and an etching process, may be used to obtain an appropriate model for the process for implementing the pattern. Afterwards, the original layout 100 is calibrated to apply the simulation to the model, and the model is applied to the original layout 100 to simulate the contour contours, and the simulated contour lines and the original layout 100 are simulated. Compare

The original layout 100 is grid (or pixel) divided into smaller grids or segments, which can be applied to simulations using the model through model calibration, and individual grids (or pixels) according to the grid segmentation. For evaluation points representative of, the simulated contour and original layout 100 are compared.

Based on this comparison, the segments are moved to implement the OPC layout for the original layout 100 to compensate for printed errors for each evaluation point. Thus, the final layout 101 of FIG. 4 can be understood as the OPC layout 101 obtained by the model based OPC approach.

Referring again to FIGS. 4 and 8, in order to verify the OPC layout 101, first, the OPC layout 101 is performed to perform a model-based simulation on the OPC layout 101 according to the model base approach. Calibration is performed (805 of FIG. 8).

As shown in FIG. 4, a calibration using the model is performed on the layout 101 OPC onto the wafer, and the model is set with a model for setting a position to be evaluated or calculated. At this time, the evaluation point 103 to be calculated according to the model base approach is a grid coordinate point or grid point representative of the grid (or segments according to grid division; 105) when dividing the layout area into pixels or grids 105. It can be understood as.

5 and 8, a simulation using a model is performed on the calibrated OPC layout 101 to obtain a simulation contour line 107. Afterwards, the difference 109 between the simulation contour 107 and the original layout 100 is calculated for each of the evaluation points 103 (807 in FIG. 8). Since the evaluation points 103 are set with respect to the edge of the pattern of the layout, the calculated difference values 109 are calculated from the simulation contour line 017 for the OPC layout 101 and the evaluation point 103 of the original layout 100. It can be understood as the critical line width (CD) difference in. The calculated difference values 109 at the evaluation points 103 are converted into a data format, for example GDS format and stored.

6 and 8, the difference values 109 calculated at the respective evaluation points 103 between the original layout 100 and the simulation contour 107 of the OPC layout are stored in, for example, GDS format, and such storage. The data is used to create a polygon 111 for the OPC layout (101 in FIG. 4) and weave this collection of polygons 111 to create a layout 113 of a new pseudo wafer image (FIG. 8). Of 809). Storing data in the GDS format may be understood to combine the layout 113 of the virtual wafer image into polygons 111 using the difference values 109.

By using the data of the difference values 109, by moving the respective grids (or segments) 103 in the OPC layout 101, the moved portion is moved perpendicular to the layout 113 of the final virtual wafer image. The difference values 109 are compensated for. The polygon 111 is formed by the movement of the segment 103, and the entire layout 113 of the virtual wafer image is formed by the combination of the polygons.

7 and 8, the layout 113 of the virtual wafer image is verified by a design rule check method (811 of FIG. 8). A design rule check (DRC) is performed using the data of the layout 113 of the virtual wafer image to determine whether the OPC layout 101 is suitable. For example, it is determined whether or not to violate the rules of the rule list having a spaced interval 115 from the neighboring patterns, and / or whether the line width 117 of the patterns is violating the rules. Judge. That is, verification is performed at a point where a problem may occur, for example, the spaced interval 115 portion or the line width 117 portion.

When it is determined that the OPC layout 101 is appropriate according to the result of the DRC check, the photomask is fabricated (813 in FIG. 8). On the other hand, if it is determined to be ineligible, OPC can be performed again.

As described above, in the embodiment of the present invention, similar to the model-based approach or the grid-based approach, the OPC layout is verified using the model, but the DRC is used in parallel to compensate for the weaknesses of the grid-based productivity. The weakness of the accuracy of the physical dimension checking method such as

On the other hand, the OPC correction verification method according to the embodiment of the present invention according to the wafer conditions, for example, the best condition (under exposure condition) or over exposure condition when the actual pattern is transferred onto the wafer When performed according to process conditions such as (over exposure condition), a process margin or a process window during a lithography process may be checked.

9 to 11 are diagrams schematically illustrating a modified example of the optical proximity correction verification according to the embodiment of the present invention.

FIG. 9 illustrates a case where OPC verification is performed according to an embodiment of the present invention under an optimal exposure condition, and FIG. 10 illustrates a case where OPC verification is performed under an under exposure condition. It shows the case of executing.

In the verification method in the embodiment of the present invention, the difference calculation (FIG. 807) is performed using a model, in which the wafer process conditions, for example, optimal exposure, are obtained when the model is simulated to obtain a simulation contour or a model is obtained. Conditions, under exposure conditions, and / or over exposure conditions may be applied to obtain different simulation contours.

Since the simulation contour is obtained differently according to each condition, the difference value with the contour (109 of FIG. 5) can also be obtained differently, and accordingly, the layouts of the virtual wafer image (213 of FIG. 9 and 313 of FIG. 10). 413 of FIG. 11 may also be obtained otherwise. Accordingly, in the DRC verification, as shown in FIG. 9, the spaced interval 215 and the line width 217 may be verified in the optimal condition. Also, as shown in FIG. 10, the spacing 315 and the line width 317 in the under exposure state can be verified. In this case, it may be verified that the line width does not violate the rule. In addition, as shown in FIG. 11, the spaced interval 415 and the line width 417 in the over-exposure state may be verified, where the spaced interval 415 may be verified in a case where the rule does not violate the rule.

These results can confirm the margin on the lithography process, thereby confirming the process window of the lithography process.

As mentioned above, although this invention was demonstrated in detail through the specific Example, this invention is not limited to this, It is clear that the deformation | transformation and improvement are possible by the person of ordinary skill in the art within the technical idea of this invention.

According to the present invention described above, the process of performing the OPC according to the model base approach and verifying the obtained OPC layout can be verified using the model similar to the model base method (or grid base method). In this case, by using a physical dimension check method such as DRC in parallel, it is possible to complement the grid-based productivity weakness and the physical vulnerability check accuracy weakness.

As such, the grid-based verification speed weakness and the physical dimension checking accuracy weakness can be compensated for, so that an error can be detected before the photo mask is manufactured, and a potential hot spot can be obtained. Can be detected and corrected in advance, so that a critical failure occurring after fabrication of the photo mask can be solved.

Claims (4)

Designing an original layout of the target patterns; Performing optical proximity effect correction on the original layout; Obtaining a simulated contour on the corrected layout; Obtaining data of difference values between the simulation contour and the original layout; Creating a layout of a virtual wafer image in which data of the difference values is reflected; And Verifying data of the layout of the wafer image with a design rule check; Calibrating the corrected layout into grids represented by the evaluation point to set an evaluation point from which the data of difference values are obtained; And Applying the data of the difference values for the evaluation points to the correction layout to create a layout of the virtual wafer image consisting of a combination of polygons. . Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, And said optical proximity effect correction is performed by a model-based approach. delete Claim 4 was abandoned when the registration fee was paid. The method of claim 1, The design rule check verification verifies whether the line width of the pattern included in the layout of the virtual wafer image and the spaced interval between the patterns are in conflict with a set rule. .

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