JP2005017551A - Method for verifying proximity effect correction and verification apparatus therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To produce an OPC (optical proximity correction) pattern of high accuracy in a short period of time by efficiently determining whether quantitative deviation in positions is caused by the logical fault of the OPC or not. <P>SOLUTION: A portion where the transfer accuracy is degraded is detected by comparing with a noncorrected simulation image. Specifically, the direction of the deviation of the OPC pattern with respect to the design pattern is compared with the direction of the deviation of the simulated transfer image of the design pattern with respect to the design pattern and the portion where the directions of the deviation coincide is determined as an error. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to lithography technology, and in particular, to optical proximity effect correction (OPC) verification technology.
[0002]
[Prior art]
In recent years, with the miniaturization of large-scale integrated circuit devices (hereinafter referred to as LSIs) using semiconductors, in the lithography process, which is one of the LSI manufacturing processes, the dimensions (mask dimensions) of the design pattern (target pattern). ) And the dimension (working dimension) of the transfer pattern (resist pattern) formed by transferring the design pattern onto the resist, it has become impossible to ignore the magnitude of the difference. In order to reduce the difference between the mask dimension and the processing dimension, a technique for applying a minute deformation to the design pattern, that is, proximity proximity correction (OPC) is used. There are two types of OPC: rule-based OPC that corrects a design pattern based on a correction rule (OPC rule) that has been obtained in advance, and model-based OPC that corrects a design pattern using a simulator that models a phenomenon in a lithography process. It is divided roughly into.
[0003]
There have been many reports on rule-based OPC (see, for example, Patent Document 1 and Non-Patent Document 1). In the rule-based OPC, a correction rule that combines various graphic processes is created. FIGS. 8A to 8D respectively show typical examples of such graphic processing. Specifically, as shown in FIG. 8A, a change 81a that narrows or widens the line width based on the line width L or the adjacent space dimension S with respect to the pair of line patterns 81, that is, line correction. Is done. Further, as shown in FIG. 8B, hammer head correction for adding a rectangular figure 82a to the tip of the line pattern 82 is performed in order to prevent the tip of the line pattern 82 from being transferred (patterned) thinly. Further, as shown in FIG. 8C, in order to prevent patterning in a state in which the corner portion of the rectangular pattern 83 is retracted, serif correction for adding a rectangle 83a to the convex corner portion of the rectangular pattern 83 is performed. Done. Further, as shown in FIG. 8D, inset correction is performed in which the concave corner of the L-shaped pattern 84 is cut to 84a to prevent the concave corner from being patterned.
[0004]
In recent years, rule-based OPC uses a method of simulating a transfer image of a correction pattern (OPC pattern) by lithography and verifying the result in order to verify the validity of the OPC rule.
[0005]
FIG. 9 is a flowchart of a conventional OPC rule verification procedure, and FIGS. 10A to 10E are diagrams for explaining each step of the conventional OPC rule verification procedure.
[0006]
First, in step S1, design patterns (target patterns) 91a and 91b are input to a computer as mask data (see FIG. 10A).
[0007]
Next, in step S2, OPC patterns 92a and 92b are output by correcting the design patterns 91a and 91b based on the OPC rules (see FIG. 10B). At this time, for example, line correction for narrowing the pattern is performed on the pattern portion 92c having a narrow adjacent space dimension. For example, line correction for thickening the pattern is performed on the pattern portion 92d having a large adjacent space size. That is, a correction pattern is created by using various OPC rules in combination.
[0008]
Next, in step S3, a post-transfer image shape simulation is performed on the OPC patterns 92a and 92b created in step S2 (see FIG. 10C). Thereby, simulation patterns 93a and 93b are obtained corresponding to the OPC patterns 92a and 92b, respectively.
[0009]
Next, in step S4, the design patterns 91a and 91b and the shape simulation results, that is, the simulation patterns 93a and 93b are overlaid (see FIG. 10D). Specifically, verification locations (hereinafter referred to as “sites”) 94 indicated by lines drawn perpendicularly to the design patterns 91a and 91b are set, and the simulation patterns 93a and 93b at each site 94 are designed. A positional deviation amount (Δ) with respect to the patterns 91a and 91b is measured. For the positional deviation, the deviation direction is set in advance. Specifically, the direction outside the design pattern is defined as a + (plus) deviation direction, and the direction inside the design pattern is designated as a minus (−) deviation direction.
[0010]
Finally, in step S5, a location (error location) where the positional deviation amount (Δ) measured in step S4 is large is output as an error flag 95. Specifically, the error flag 95 is output in four stages: Δ <−10 nm, −10 nm ≦ Δ <−5 nm, +5 nm <Δ ≦ + 10 nm, and +10 nm ≦ Δ. By verifying this error location, it is possible to correct a defect in the OPC pattern design.
[0011]
In actual verification, if the post-transfer image of the entire OPC pattern is simulated in step S3, the calculation time of the computer becomes enormous. In step S3, only the expected dimensions at each site are calculated and the results are used. In many cases, a method of calculating the positional deviation amount (Δ) in step S4 is used.
[0012]
[Patent Document 1]
JP 9-319067 A
[0013]
[Non-Patent Document 1]
Oberdan W. Otto et al., Automating Optical Proximity Effect Correction Rule-Based Approach (automatic-proximity-correction-based-based-approach), SPI Sympom (US) 1994, Vol. 2197, p. 278-293
[0014]
[Problems to be solved by the invention]
By the way, when there is a logical defect in the correction by the OPC rule, that is, when the definition of the processing figure, the processing order or the processing formula is inappropriate in the correction procedure combining the OPC rule, and the combination of the OPC rule is bad In some cases, proximity effect correction is performed in a direction opposite to the direction to be corrected. In order to eliminate such a problem, for example, new development such as adjustment of the processing formula is required, and as a result, it takes a lot of time to correct the combination of OPC rules. Therefore, it is desirable that a logical failure is detected early as an important failure when performing OPC.
[0015]
However, in the conventional OPC verification method, since the importance of the generated error is quantitatively determined by the positional deviation amount Δ, a quantitative defect such as a sizing amount (size change amount) error in correction is important. Is often detected as a malfunction. On the other hand, the cause of the positional deviation between the design pattern and the OPC pattern (to be exact, the transferred image) is not only a deviation of the correction amount such as a sizing amount error at the time of correction, but also various other factors. Factors are considered. For example, as described above, when the combination of OPC rules is inappropriate, or when the location of the site 94 in step S4 (see FIG. 10D) is inappropriate, the positional deviation occurs.
[0016]
In other words, there are several possible causes for the positional deviation between the design pattern and the OPC pattern. However, if the amount of deviation is detected quantitatively as in the conventional OPC verification method, the cause of the positional deviation is determined. It is difficult to identify. For example, the quantitative positional deviation may occur due to the set position of the site. More specifically, there may be a case where a pseudo error is output due to an inappropriate location of the site even though there is no problem with the correction by the OPC rule.
[0017]
Accordingly, in the conventional OPC verification method, since the reliability of the numerical value indicating the quantitative positional deviation is low, the logical problem of OPC, which is a fundamental problem, that is, an error in the combination of the OPC rules, is detected at other positions. There is a high possibility that it will be confused with the cause of the deviation and overlooked.
[0018]
In view of the above, the present invention makes it possible to efficiently determine whether the cause of quantitative positional deviation is due to a logical malfunction of OPC, thereby enabling a highly accurate OPC pattern to be generated in a short time. For the purpose.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, the inventors of the present application determine whether or not the pattern transfer accuracy is improved by the correction pattern by the rule-based OPC as compared with the case of no correction. A method and apparatus for selectively detecting logical failures in OPC are provided.
[0020]
Specifically, the first proximity effect correction verification method according to the present invention is a first method of outputting a correction pattern by performing proximity effect correction on a design pattern using a predetermined correction rule. A simulation pattern is obtained by performing a simulation of a transfer image obtained when exposure is performed under predetermined conditions on the design pattern, a second process for determining a deviation direction of the correction pattern with respect to the design pattern, and A third step of outputting, a fourth step of determining a shift direction of the simulation pattern with respect to the design pattern, a shift direction of the correction pattern determined in the second step, and a simulation pattern determined in the fourth step And a fifth step of outputting, as an error, a location where each deviation direction is the same direction. There. Note that it is not always necessary to generate the entire correction pattern or simulation pattern in the first or third step. That is, it is possible to calculate only an expected dimension at a site arranged in advance for each pattern and use the result in another process. In this way, calculation time by the computer can be shortened.
[0021]
An apparatus for carrying out such a first proximity effect correction verification method according to the present invention includes, for example, an input unit for inputting a design pattern and a predetermined design pattern input to the input unit. A correction pattern is created by performing proximity effect correction using a correction rule, a first determination unit that determines a deviation direction of the correction pattern with respect to the design pattern, and a predetermined pattern with respect to the design pattern input to the input unit A second determination unit that generates a simulation pattern by simulating a transfer image obtained when exposure is performed under the conditions, and determines a deviation direction of the simulation pattern with respect to the design pattern; and a first determination unit The deviation direction of the correction pattern determined in step 1 is compared with the deviation direction of the simulation pattern determined by the second determination unit. And, and an output unit for each shift direction and outputs the portion which becomes the same direction as an error.
[0022]
The second proximity effect correction verification method according to the present invention includes a first step of outputting a correction pattern by performing proximity effect correction on a design pattern using a predetermined correction rule. The second step of outputting the first simulation pattern by simulating the transfer image obtained when the correction pattern is exposed under predetermined conditions, and the first simulation pattern for the design pattern A third step of determining a misalignment direction, and a fourth step of outputting a second simulation pattern by simulating a transfer image obtained when exposure is performed on a design pattern under a predetermined condition. A fifth step of determining a deviation direction of the second simulation pattern with respect to the design pattern; The deviation direction of the first simulation pattern determined in the third step is compared with the deviation direction of the second simulation pattern determined in the fifth step, and an error is detected at a location where each deviation direction is the same direction. As a sixth step. In the first, second, or fourth step, it is not always necessary to generate the correction pattern, the first simulation pattern, or the second simulation pattern. That is, it is possible to calculate only an expected dimension at a site arranged in advance for each pattern and use the result in another process. In this way, calculation time by the computer can be shortened.
[0023]
An apparatus for carrying out the second proximity effect correction verification method according to the present invention as described above is predetermined for, for example, an input unit for inputting a design pattern and a design pattern input to the input unit. A correction pattern is created by performing proximity effect correction using the correction rule, and a first simulation pattern is obtained by simulating a transfer image obtained when the correction pattern is exposed under predetermined conditions. Obtained when exposure is performed under a predetermined condition with respect to the first determination unit that is created and determines the direction of deviation of the first simulation pattern from the design pattern, and the design pattern input to the input unit A second simulation pattern is created by simulating the transfer image, and the second stain is created. A second determination unit that determines a shift direction of the design pattern with respect to the design pattern, a shift direction of the first simulation pattern that is determined by the first determination unit, and a second simulation that is determined by the second determination unit An output unit that compares the pattern shift directions with each other and outputs a position where each shift direction is the same as an error;
[0024]
According to the present invention, in order to verify the right or wrong of the correction direction (deviation direction) of a correction pattern by OPC (hereinafter referred to as an OPC pattern) on the basis of a transfer image of an uncorrected design pattern, the transfer of the uncorrected design pattern is performed. It is possible to selectively detect a portion where the pattern deformation in the image is further deteriorated by the OPC process. In addition, since the design pattern itself is not compared with the transfer image of the OPC pattern as in the prior art, a quantitative positional deviation between the design pattern itself and the transfer image of the OPC pattern may be output as an error. Absent. For this reason, it is possible to selectively and efficiently detect a portion where the accuracy of pattern transfer is deteriorated due to a logical defect of OPC. That is, rule-based OPC logic error verification can be efficiently realized without generating a pseudo error. Therefore, since it is possible to improve the logical failure of OPC at an early stage, a highly accurate OPC pattern can be generated in a short time.
[0025]
Further, according to the present invention, an error portion in OPC is specified only by comparing the shift direction of the OPC pattern with the shift direction of the transfer image of the design pattern. In other words, an error location in OPC can be specified without performing detailed verification on a correction amount such as a shift amount of the OPC pattern. For this reason, the time required for OPC pattern creation can be shortened.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
Hereinafter, an OPC verification method and verification apparatus according to a first embodiment of the present invention will be described with reference to the drawings.
[0027]
FIG. 1 is a flowchart of an OPC verification method according to the first embodiment. FIGS. 2A to 2F are diagrams for explaining each step of the OPC verification method according to the first embodiment. FIG.
[0028]
First, in step S11, design patterns (target patterns) 11a and 11b are input to a computer as mask data (see FIG. 2A).
[0029]
Next, in step S12, the design patterns 11a and 11b are corrected using a predetermined combination of OPC rules, thereby outputting the OPC patterns 12a and 12b (see FIG. 2B).
[0030]
Next, in step S13, the shift direction (correction direction) of the OPC patterns 12a and 12b with respect to the design patterns 11a and 11b is determined (see FIG. 2C). Here, if the edges of the OPC patterns 12a and 12b are outside the edges of the design patterns 11a and 11b, the positive (+) direction is assumed. The edges of the OPC patterns 12a and 12b are inside the edges of the design patterns 11a and 11b. If there is, the negative (−) direction is displayed, and each shift direction is displayed using a figure (hereinafter referred to as a flag) 13.
[0031]
Next, in step S14, simulation patterns 14a and 14b are output by simulating a transfer image obtained when the design patterns 11a and 11b are exposed under predetermined conditions (FIG. 2D). reference). In other words, the processing shape of the pattern transferred onto the wafer is predicted when patterning is performed using a photomask provided with uncorrected design patterns 11a and 11b.
[0032]
Next, in step S15, the shift direction (correction direction) of the simulation patterns 14a and 14b with respect to the design patterns 11a and 11b is determined (see FIG. 2E). That is, the design patterns 11a and 11b and the simulation patterns 14a and 14b are overlapped and compared, whereby the design patterns 11a and 11b and a pattern (simulation pattern 14a) obtained by actual patterning using the design patterns 11a and 11b are compared. And 14b) is determined. Specifically, if the edges of the simulation patterns 14a and 14b are outside the edges of the design patterns 11a and 11b, the positive (+) direction is set, and the edges of the simulation patterns 14a and 14b are more than the edges of the design patterns 11a and 11b. If it is inside, the negative (-) direction is set, and each shift direction is displayed using the flag 15.
[0033]
Next, in step S16, the flags 13 and 15 output in steps S13 and S15, respectively, are overlapped to determine whether or not the flags 13 and 15 are in a mutually canceling relationship (FIG. 2 (f )reference).
[0034]
Incidentally, the reason why the OPC is originally performed is as follows. That is, the pattern cannot be transferred according to the dimension of the design pattern using a photomask provided with an uncorrected design pattern. Therefore, OPC is performed on the design pattern so as to obtain a desired pattern after exposure, and the OPC pattern obtained by the OPC pattern is used as a mask pattern. Therefore, if the OPC is properly performed, the deviation direction of the OPC pattern should be opposite to the pattern deformation direction in the transfer image of the design pattern. In this case, when the flag 13 displayed in step S13 and the flag 15 displayed in step 15 are overlapped, the plus and minus of each flag cancel each other. Conversely, when the flag 13 displayed in step S13 and the flag 15 displayed in step S15 are displayed in the same direction, the pattern transfer accuracy is further deteriorated due to the deformation of the design pattern by OPC. It means that there is. Therefore, in step S16, the flag 13 displayed in step S13 (the displacement direction of the OPC patterns 12a and 12b) and the flag 15 displayed in step S15 (the displacement direction of the simulation patterns 14a and 14b) are in the same direction. The error flag 16 is displayed at the location (pattern portion). Further, the pattern portion on which the error flag 16 is displayed is extracted as an error occurrence pattern. That is, by verifying this error occurrence pattern and specifying the location where the error has occurred, it is possible to specify the location where the logical failure has occurred in the OPC patterns 22a and 22b. Therefore, by verifying the combination of the OPC rules at the specified location and correcting the combination, it is possible to relatively easily correct the defects in the OPC pattern design.
[0035]
As described above, according to the first embodiment, the correction direction (deviation direction) of the OPC patterns 12a and 12b is based on the transfer images (simulation patterns 14a and 14b) of the uncorrected design patterns 11a and 11b. I will verify it. For this reason, it is possible to selectively detect a portion where the pattern deformation in the transfer image of the uncorrected design patterns 11a and 11b is further deteriorated by the OPC process. In addition, since the design pattern itself is not compared with the transfer image of the OPC pattern as in the prior art, a quantitative positional deviation between the design pattern itself and the transfer image of the OPC pattern may be output as an error. Absent. For this reason, it is possible to selectively and efficiently detect a portion where the accuracy of pattern transfer is deteriorated due to a logical defect of OPC. That is, rule-based OPC logic error verification can be efficiently realized without generating a pseudo error. Accordingly, such a logical defect can be improved at an early stage, so that a highly accurate OPC pattern can be generated in a short time. An OPC error caused by an incorrect correction sizing amount can be corrected by changing the correction sizing amount, so that the correction of the OPC pattern is relatively easy.
[0036]
In addition, according to the first embodiment, an error location in OPC can be identified simply by comparing the deviation direction of the OPC patterns 12a and 12b with the deviation direction of the transfer images (simulation patterns 14a and 14b) of the design patterns 11a and 11b. To do. In other words, an error location in OPC can be specified without performing detailed verification on a correction amount such as a shift amount of the OPC pattern. For this reason, the time required for OPC pattern creation can be shortened.
[0037]
In the first embodiment, the positive / negative of the shift direction of the OPC patterns 12a and 12b and the simulation patterns 14a and 14b is displayed using the flags 13 and 15 (see step S13 and step S15). However, “no deviation (0)” may be displayed using the flags 13 and 15. In this case, in step S16, the flag 13 displayed in step S13 and the flag 15 displayed in step S15 are in the same direction (flag 13: flag 15 = positive: positive or negative: negative). The error flag 16 may be displayed at a place where only one of the flags 13 and 15 becomes 0 (flag 13: flag 15 = positive: 0, 0: positive, negative: 0 or 0: negative).
[0038]
Further, in the first embodiment, in step S13, the shift amount in the shift direction is determined together with the shift direction of the OPC patterns 12a and 12b with respect to the design patterns 11a and 11b, and in step S15, the simulation for the design patterns 11a and 11b is performed. The shift amount in the shift direction may be determined together with the shift direction of the patterns 14a and 14b. In this case, in step S16, each deviation direction determined in steps S13 and S15 is the same direction, and at least one absolute value of each deviation amount determined in steps S13 and S15 is equal to or greater than a predetermined value. The error flag 16 may be displayed at the location. Specifically, assuming that the predetermined value is 10 nm, OPC pattern positional deviation: simulation pattern positional deviation = + 10 nm: +10 nm, +10 nm: +5 nm, +5 nm: +10 nm,. The error flag 16 is displayed in the case of −10 nm: −10 nm, −10 nm: −5 nm, −5 nm: −10 nm,.
[0039]
Moreover, in 1st Embodiment, you may mutually replace the execution order of step S12 and S13 and step S14 and S15.
[0040]
In the first embodiment, it is not always necessary to generate the OPC patterns 12a and 12b or the entire simulation patterns 14a and 14b in step S12 or step S14. That is, for each pattern, it is possible to calculate only the expected dimension at the site arranged in advance and use the result in other steps. In this way, calculation time by the computer can be shortened.
[0041]
Here, an example of an apparatus for performing the OPC verification method according to the first embodiment described above will be briefly described. That is, an example of the OPC verification apparatus according to the first embodiment includes an input unit, a first determination unit, a second determination unit, and an output unit. The input unit inputs a design pattern. The first determination unit creates a correction pattern by performing proximity effect correction on the design pattern input to the input unit using a predetermined correction rule, and sets a shift direction of the correction pattern with respect to the design pattern. judge. The second determination unit creates a simulation pattern by simulating a transfer image obtained when exposure is performed under a predetermined condition with respect to the design pattern input to the input unit. The direction of deviation from the design pattern is determined. The output unit compares the shift direction of the correction pattern determined by the first determination unit with the shift direction of the simulation pattern determined by the second determination unit, and an error is detected at a location where each shift direction is the same direction. Output as. The first determination unit may determine the shift amount in the shift direction together with the shift direction of the correction pattern with respect to the design pattern. In addition, the second determination unit may determine the shift amount in the shift direction together with the shift direction of the simulation pattern with respect to the design pattern. The output unit may output, as an error, a location where each of the deviation directions is the same direction and at least one absolute value of each deviation amount is equal to or greater than a predetermined value.
[0042]
(Second Embodiment)
Hereinafter, an OPC verification method and verification apparatus according to a second embodiment of the present invention will be described with reference to the drawings.
[0043]
FIG. 3 is a flowchart of the OPC verification method according to the second embodiment, and FIGS. 4A to 4G are diagrams for explaining the steps of the OPC verification method according to the second embodiment. FIG.
[0044]
First, in step S21, design patterns (target patterns) 21a and 21b are input to a computer as mask data (see FIG. 4A).
[0045]
Next, in step S22, the design patterns 21a and 21b are corrected using a predetermined combination of OPC rules, thereby outputting the OPC patterns 22a and 22b (see FIG. 4B).
[0046]
Next, in step S23, the first simulation patterns 23a and 23b are output by simulating a transfer image obtained when the OPC patterns 22a and 22b are exposed under predetermined conditions (FIG. 4). (See (c)). In other words, when the patterning is performed using the photomask provided with the OPC patterns 22a and 22b, the processing shape of the pattern transferred onto the wafer is predicted.
[0047]
Next, in step S24, the shift direction (correction direction) of the first simulation patterns 23a and 23b with respect to the design patterns 21a and 21b is determined (see FIG. 4D). In other words, the design patterns 21a and 21b and the first simulation patterns 23a and 23b are overlapped and compared, whereby a pattern (first pattern) obtained by actual patterning by the design patterns 21a and 21b and the OPC patterns 22a and 22b is obtained. The direction of deviation generated between the simulation patterns 23a and 23b) is determined. Specifically, if the edges of the first simulation patterns 23a and 23b are outside the edges of the design patterns 21a and 21b, the positive (+) direction is set, and the edges of the first simulation patterns 23a and 23b are the design pattern 21a. And the negative (-) direction if it is inside the edge of 21b, and the respective deviation directions are displayed using the flag 24.
[0048]
Next, in step S25, the second simulation patterns 25a and 25b are output by simulating a transfer image obtained when the design patterns 21a and 21b are exposed under predetermined conditions (FIG. 4). (See (e)). In other words, the processing shape of the pattern transferred onto the wafer is predicted when patterning is performed using a photomask provided with uncorrected design patterns 21a and 21b.
[0049]
Next, in step S26, the shift direction (correction direction) of the second simulation patterns 25a and 25b with respect to the design patterns 21a and 21b is determined (see FIG. 4F). In other words, the design patterns 21a and 21b and the second simulation patterns 25a and 25b are overlapped and compared, so that the design patterns 21a and 21b and the patterns obtained by actual patterning using the design patterns 21a and 21b ( The direction of deviation occurring between the second simulation patterns 25a and 25b) is determined. Specifically, if the edges of the second simulation patterns 25a and 25b are outside the edges of the design patterns 21a and 21b, the positive (+) direction is set, and the edges of the second simulation patterns 25a and 25b are the design pattern 21a. And the negative (−) direction if it is inside the edge of 21b, and the respective displacement directions are displayed using the flag 26.
[0050]
Next, in step S27, the flags 24 and 26 output in steps S24 and S26, respectively, are overlapped to determine whether or not the flags 24 and 26 are in a mutually canceling relationship (FIG. 4 (g )reference).
[0051]
Incidentally, the reason why the OPC is originally performed is as follows. That is, pattern transfer cannot be performed according to the dimensions of the design pattern using a photomask provided with an uncorrected design pattern. Therefore, OPC is performed on the design pattern so as to obtain a desired pattern after exposure, and the OPC pattern obtained by the OPC pattern is used as a mask pattern. Therefore, if the OPC is appropriately performed, the shift direction in the transfer image of the OPC pattern should be opposite to the deformation direction of the pattern in the transfer image of the design pattern. In this case, if the flag 24 displayed in step S24 and the flag 26 displayed in step S26 are overlapped, the plus and minus of each flag cancel each other. Conversely, when the flag 24 displayed in step S24 and the flag 26 displayed in step S26 are displayed in the same direction, the pattern transfer accuracy is further deteriorated due to the deformation of the design pattern by OPC. It means that there is. Therefore, in step S27, the flag 24 displayed in step S24 (the displacement direction of the first simulation patterns 23a and 23b) and the flag 26 displayed in step S26 (the displacement direction of the second simulation patterns 25a and 25b). The error flag 27 is displayed at a location (pattern portion) in which it is in the same direction. Further, the pattern portion on which the error flag 27 is displayed is extracted as an error occurrence pattern. That is, by verifying this error occurrence pattern and specifying the location where the error has occurred, it is possible to specify the location where a logical failure has occurred in the OPC patterns 22a and 22b. Therefore, by verifying the combination of the OPC rules at the specified location and correcting the combination, it is possible to relatively easily correct the defects in the OPC pattern design.
[0052]
As described above, according to the second embodiment, the transfer images (first images) of the OPC patterns 22a and 22b based on the transfer images (second simulation patterns 25a and 25b) of the uncorrected design patterns 21a and 21b. The right or wrong of the deviation direction in the first simulation pattern 23a and 23b) is verified. For this reason, it is possible to selectively detect a portion where the pattern deformation in the transferred image of the uncorrected design patterns 21a and 21b is further deteriorated by the OPC process. In addition, since the design pattern itself is not compared with the transfer image of the OPC pattern as in the prior art, a quantitative positional deviation between the design pattern itself and the transfer image of the OPC pattern may be output as an error. Absent. For this reason, it is possible to selectively and efficiently detect a portion where the accuracy of pattern transfer is deteriorated due to a logical defect of OPC. That is, rule-based OPC logic error verification can be efficiently realized without generating a pseudo error. Accordingly, such a logical defect can be improved at an early stage, so that a highly accurate OPC pattern can be generated in a short time. An OPC error caused by an incorrect correction sizing amount can be corrected by changing the correction sizing amount, so that the correction of the OPC pattern is relatively easy.
[0053]
Further, according to the second embodiment, since the simulation result of the transfer image of the OPC pattern is compared with the simulation result of the transfer image of the design pattern, the logical failure of the OPC rule can be detected in more detail. Accuracy can be improved.
[0054]
Furthermore, the present embodiment is particularly effective when a mask pattern having a complicated structure in which a new correction portion is generated when OPC is performed on a design pattern. For example, two error flags 27 displayed at the end of the line in FIG. 4G correspond to such newly generated correction points. Specifically, as shown in FIGS. 5A and 5B, for a pair of line patterns 28 (line width L) having a narrow inter-line space S, the line width L is first narrowed in OPC. Rule 28a is applied. However, when the line width L is reduced by OPC, it becomes different from the initial pattern dimension. Therefore, a new correction that is not necessary for the initial pattern, specifically, as shown in FIG. A correction 28b that thickens the tip of each line pattern 28 is required. That is, an optimal OPC pattern cannot be predicted based only on the first pattern. On the other hand, in the present embodiment, since the patterning (transfer image) is simulated based on the OPC patterns 22a and 22b, the simulation result is compared with the simulation result of the transfer image of the design pattern. It is possible to detect whether further correction is necessary due to this. Therefore, according to the present embodiment, even when OPC is performed on a complex pattern, an error location in OPC can be detected with high accuracy.
[0055]
Further, according to the second embodiment, the shift direction of the transfer images of the OPC patterns 22a and 22b (first simulation patterns 23a and 23b) and the transfer image of the design patterns 21a and 21b (second simulation patterns 25a and 25b). The error part in OPC is specified only by comparing with the deviation direction. In other words, an error location in OPC can be specified without performing detailed verification on a correction amount such as a shift amount of the OPC pattern. For this reason, the time required for OPC pattern creation can be shortened.
[0056]
In the second embodiment, whether the second simulation patterns 25a and 25b are positive or negative is displayed using the flag 26 (see step S26). However, “no deviation (0)” may be displayed using the flag 26. In this case, in step S27, the flag 24 displayed in step S24 and the flag 26 displayed in step S26 are in the same direction (flag 24: flag 26 = positive: positive or negative: negative). The error flag 27 may be displayed at a location where the flag 26 becomes 0 (flag 24: flag 26 = positive: 0 or negative: 0).
[0057]
In the second embodiment, the execution order of steps S22, S23, and S24 and steps S25 and S26 may be interchanged.
[0058]
In the second embodiment, it is not always necessary to generate the OPC patterns 22a and 22b, the first simulation patterns 23a and 23b, or the entire second simulation patterns 25a and 25b in step S22, step S23, or step S25. Absent. That is, for each pattern, it is possible to calculate only the expected dimension at the site arranged in advance and use the result in other steps. In this way, calculation time by the computer can be shortened.
[0059]
Here, an example of an apparatus for carrying out the OPC verification method according to the second embodiment described above will be briefly described. That is, an example of the OPC verification apparatus according to the second embodiment includes an input unit, a first determination unit, a second determination unit, and an output unit. The input unit inputs a design pattern. The first determination unit creates a correction pattern by performing proximity effect correction on the design pattern input to the input unit using a predetermined correction rule, and performs a predetermined condition on the correction pattern. A first simulation pattern is created by simulating a transfer image obtained when exposure is performed, and a deviation direction of the first simulation pattern with respect to a design pattern is determined. The second determination unit creates a second simulation pattern by simulating a transfer image obtained when the design pattern input to the input unit is exposed under a predetermined condition, The direction of deviation of the second simulation pattern from the design pattern is determined. The output unit compares the shift direction of the first simulation pattern determined by the first determination unit with the shift direction of the second simulation pattern determined by the second determination unit, and each shift direction is the same. The part that becomes the direction is output as an error.
[0060]
(Third embodiment)
Hereinafter, an OPC verification method and verification apparatus according to a third embodiment of the present invention will be described with reference to the drawings.
[0061]
FIG. 6 is a flowchart of the OPC verification method according to the third embodiment, and FIGS. 7A to 7G are diagrams for explaining the steps of the OPC verification method according to the third embodiment. FIG.
[0062]
First, in step S31, as in step S21 of the second embodiment, design patterns (target patterns) 31a and 31b are input to the computer as mask data (see FIG. 7A).
[0063]
Next, in step S32, as in step S22 of the second embodiment, the design patterns 31a and 31b are corrected by using a predetermined combination of OPC rules, whereby the OPC patterns 32a and 32b are corrected. Is output (see FIG. 7B).
[0064]
Next, in step S33, similarly to step S23 of the second embodiment, a first simulation is performed by simulating a transfer image obtained when the OPC patterns 32a and 32b are exposed under predetermined conditions. The simulation patterns 33a and 33b are output (see FIG. 7C). In other words, when the patterning is performed using the photomask provided with the OPC patterns 32a and 32b, the processing shape of the pattern transferred onto the wafer is predicted.
[0065]
Next, in step S34, the shift direction (correction direction) of the first simulation patterns 33a and 33b with respect to the design patterns 31a and 31b and the shift amount in the shift direction are determined (see FIG. 7D). In other words, the design patterns 31a and 31b and the first simulation patterns 33a and 33b are overlapped and compared, whereby the design patterns 31a and 31b and the patterns obtained by actual patterning using the OPC patterns 32a and 32b (first The deviation direction between the simulation patterns 33a and 33b) and the deviation amount in the deviation direction are determined. Specifically, the site 34a is set for the design patterns 31a and 31b, and the positional deviation amount (ΔΔ of the first simulation patterns 33a and 33b with respect to the design patterns 31a and 31b at each site 34a. ₄ ). At this time, if the edges of the first simulation patterns 33a and 33b are outside the edges of the design patterns 31a and 31b, the positive (+) direction is set, and the edges of the first simulation patterns 33a and 33b are the design patterns 31a and 31b. If it is inside the edge, the negative (−) direction is set, and the respective shift directions and the shift amount in the shift direction are displayed using the flag 34 (see FIG. 7D).
[0066]
Next, in step S35, similarly to step S25 of the second embodiment, a second simulation is performed by simulating a transfer image obtained when the design patterns 31a and 31b are exposed under predetermined conditions. The simulation patterns 35a and 35b are output (see FIG. 7E). In other words, the processing shape of the pattern transferred onto the wafer is predicted when patterning is performed using a photomask provided with uncorrected design patterns 31a and 31b.
[0067]
Next, in step S36, the shift direction (correction direction) of the second simulation patterns 35a and 35b with respect to the design patterns 31a and 31b and the shift amount in the shift direction are determined (see FIG. 7F). In other words, the design patterns 31a and 31b and the second simulation patterns 35a and 35b are overlapped and compared, so that the design patterns 31a and 31b and the patterns obtained by actual patterning using the design patterns 31a and 31b ( The deviation direction generated between the second simulation patterns 35a and 35b) and the deviation amount in the deviation direction are determined. Specifically, the site 36a is set for the design patterns 31a and 31b, and the positional shift amount (ΔΔ of the second simulation patterns 35a and 35b with respect to the design patterns 31a and 31b at each site 36a. ₆ ). At this time, if the edges of the second simulation patterns 35a and 35b are outside the edges of the design patterns 31a and 31b, the positive (+) direction is set, and the edges of the second simulation patterns 35a and 35b are the design patterns 31a and 31b. If it is inside the edge, the negative (−) direction is set, and the respective shift directions and the shift amount in the shift direction are displayed using the flag 36 (see FIG. 7F).
[0068]
Next, in step S37, the flags 34 and 36 output in steps S34 and S36, respectively, are overlapped to determine whether or not the flags 34 and 36 are in a mutually canceling relationship (FIG. 7 (g )reference).
[0069]
Incidentally, the reason why the OPC is originally performed is as follows. That is, pattern transfer cannot be performed according to the dimensions of the design pattern using a photomask provided with an uncorrected design pattern. Therefore, OPC is performed on the design pattern so as to obtain a desired pattern after exposure, and the OPC pattern obtained by the OPC pattern is used as a mask pattern. Therefore, if the OPC is appropriately performed, the shift direction in the transfer image of the OPC pattern should be opposite to the deformation direction of the pattern in the transfer image of the design pattern. In this case, if the flag 34 displayed in step S34 and the flag 36 displayed in step S36 are overlapped, the plus and minus of each flag cancel each other. Conversely, when the flag 34 displayed in step S34 and the flag 36 displayed in step S36 are displayed in the same direction, the pattern transfer accuracy is further deteriorated due to the deformation of the design pattern by OPC. It means that there is. Further, the shift amount Δ indicated by the flag 34 ₄ Is the amount of deviation Δ indicated by the flag 36. ₆ The larger the absolute value, the worse the pattern transfer accuracy. Therefore, in step S37, the flag 34 displayed in step S34 and the flag 36 displayed in step S36 are locations where they are in the same direction and the amount of deviation Δ ₄ Is the amount of deviation Δ ₆ An error flag 37 is displayed at a location (pattern portion) that is larger than the absolute value of. Further, the pattern portion on which the error flag 37 is displayed is extracted as an error occurrence pattern. That is, by verifying this error occurrence pattern and specifying the location where the error has occurred, it is possible to specify the location where the logical failure occurs in the OPC patterns 32a and 32b. Therefore, by verifying the combination of the OPC rules at the specified location and correcting the combination, it is possible to relatively easily correct the defects in the OPC pattern design.
[0070]
In the present embodiment, as shown in FIG. ₄ Absolute value and deviation Δ ₆ The type of the error flag 37 is classified according to the magnitude of the difference from the absolute value. Thereby, the severity of the error can be determined based on the type of the error flag 37.
[0071]
The third embodiment described above is different from the second embodiment as follows.
[0072]
That is, in the second embodiment, in step S24, the deviation direction of the first simulation patterns 23a and 23b (transfer images of the OPC patterns 22a and 22b) with respect to the design patterns 21a and 21b is determined. Also, in step S26, the deviation direction of the second simulation patterns 25a and 25b (transfer images of the design patterns 21a and 21b) with respect to the design patterns 21a and 21b is determined. In step S27, an error flag 27 is displayed at a location where the deviation directions determined in steps S24 and S26 are the same.
[0073]
In contrast, in the third embodiment, in step S34, the shift direction of the first simulation patterns 33a and 33b (transfer images of the OPC patterns 32a and 32b) with respect to the design patterns 31a and 31b and the shift amount in the shift direction. Δ ₄ Determine. In step S36, the second simulation patterns 35a and 35b (transfer images of the design patterns 31a and 31b) with respect to the design patterns 31a and 31b are shifted in the shift direction and the shift amount Δ in the shift direction. ₆ Determine. Further, in step S37, each of the deviation directions determined in steps S34 and S36 is the same direction and the deviation amount Δ ₄ Is the amount of deviation Δ ₆ An error flag 37 is displayed at a location larger than the absolute value of.
[0074]
According to the third embodiment, in addition to the same effects as those of the second embodiment, the following effects can be obtained. That is, the deviation amount Δ ₄ Is the amount of deviation Δ ₆ The larger the absolute value of, the greater the degree of OPC malfunction. ₄ Absolute value and deviation Δ ₆ By classifying the type of the error flag 37 according to the magnitude of the difference from the absolute value, the severity of the OPC defect can be easily determined based on the type of the error flag 37.
[0075]
In the third embodiment, the sign of the displacement direction of the second simulation patterns 35a and 35b is displayed using the flag 36 (see step S36). However, “no deviation (0)” may be displayed using the flag 36. In this case, in step S37, in addition to the flag 34 displayed in step S34 and the flag 36 displayed in step S36 in the same direction (flag 34: flag 36 = positive: positive or negative: negative) The error flag 37 may be displayed at a location where the flag 36 becomes 0 (flag 34: flag 36 = positive: 0 or negative: 0).
[0076]
In the third embodiment, the execution order of steps S32, S33, and S34 and steps S35 and S36 may be interchanged.
[0077]
In the third embodiment, it is not always necessary to generate the OPC patterns 32a and 32b, the first simulation patterns 33a and 33b, or the second simulation patterns 35a and 35b in Step S32, Step S33, or Step S35. Absent. That is, for each pattern, it is possible to calculate only the expected dimension at the site arranged in advance and use the result in other steps. In this way, calculation time by the computer can be shortened.
[0078]
In the third embodiment, in step S37, the shift amount Δ ₄ Absolute value and deviation Δ ₆ Although the type of the error flag 37 is divided according to the magnitude of the difference from the absolute value, the type of the error flag need not be divided according to the magnitude of the difference. That is, one type of error flag may be used.
[0079]
Here, an example of an apparatus for performing the OPC verification method according to the third embodiment described above will be briefly described. In other words, an example of an OPC verification apparatus according to the third embodiment includes an input unit, a first determination unit, a second determination unit, and an output unit. The input unit inputs a design pattern. The first determination unit creates a correction pattern by performing proximity effect correction on the design pattern input to the input unit using a predetermined correction rule, and performs a predetermined condition on the correction pattern. A first simulation pattern is created by simulating a transfer image obtained when exposure is performed, and a shift direction of the first simulation pattern with respect to a design pattern and a shift amount in the shift direction are determined. The second determination unit creates a second simulation pattern by simulating a transfer image obtained when the design pattern input to the input unit is exposed under a predetermined condition, A deviation direction with respect to the design pattern of the second simulation pattern and a deviation amount in the deviation direction are determined. The output unit compares the shift direction of the first simulation pattern determined by the first determination unit with the shift direction of the second simulation pattern determined by the second determination unit, and each shift direction is the same. A location where the absolute value of the deviation amount determined by the first determination unit is larger than the absolute value of the deviation amount determined by the second determination unit is output as an error.
[0080]
【The invention's effect】
According to the present invention, since the right or wrong of the misalignment direction of the correction pattern by OPC is verified on the basis of the transfer image of the uncorrected design pattern, the pattern deformation in the transfer image of the uncorrected design pattern is further deteriorated by the OPC process. It is possible to selectively detect the end of the area. For this reason, it is possible to selectively and efficiently detect a portion where the accuracy of pattern transfer is deteriorated due to a logical defect of OPC. Therefore, since it is possible to improve the logical failure of OPC at an early stage, a highly accurate OPC pattern can be generated in a short time.
[Brief description of the drawings]
FIG. 1 is a flowchart of an OPC verification method according to a first embodiment of the present invention.
FIGS. 2A to 2F are diagrams for explaining each step of an OPC verification method according to the first embodiment of the present invention;
FIG. 3 is a flowchart of an OPC verification method according to a second embodiment of the present invention.
FIGS. 4A to 4G are diagrams for explaining each step of an OPC verification method according to a second embodiment of the present invention.
FIGS. 5A to 5C are diagrams for explaining the effect of the OPC verification method according to the second embodiment of the present invention;
FIG. 6 is a flowchart of an OPC verification method according to a third embodiment of the present invention.
FIGS. 7A to 7G are views for explaining each step of an OPC verification method according to a third embodiment of the present invention.
FIGS. 8A to 8D are diagrams showing various graphic processes used for rule-based OPC. FIGS.
FIG. 9 is a flowchart of a conventional OPC verification method.
FIGS. 10A to 10E are diagrams for explaining each step of a conventional OPC verification method;
[Explanation of symbols]
11a, 11b Design pattern
12a, 12b OPC pattern
13 flags
14a, 14b Simulation pattern
15 flags
16 Error flag
21a, 21b Design pattern
22a, 22b OPC pattern
23a, 23b First simulation pattern
24 flags
25a, 25b Second simulation pattern
26 flags
27 Error flag
28 A pair of line patterns
31a, 31b Design pattern
32a, 32b OPC pattern
33a, 33b First simulation pattern
34 flags
34a site
35a, 35b Second simulation pattern
36 flags
36a site
37 Error flag

Claims (8)

A first step of outputting a correction pattern by performing proximity effect correction on the design pattern using a predetermined correction rule;
A second step of determining a deviation direction of the correction pattern with respect to the design pattern;
A third step of outputting a simulation pattern by simulating a transfer image obtained when exposure is performed on the design pattern under predetermined conditions;
A fourth step of determining a deviation direction of the simulation pattern with respect to the design pattern;
The deviation direction of the previous correction pattern determined in the second step is compared with the deviation direction of the simulation pattern determined in the fourth step, and a location where each deviation direction is the same direction is regarded as an error. A proximity effect correction verification method comprising: a fifth step of outputting. The second step includes a step of determining a deviation amount in the deviation direction together with a deviation direction of the correction pattern with respect to the design pattern,
The fourth step includes a step of determining a deviation amount in the deviation direction together with a deviation direction of the simulation pattern with respect to the design pattern,
The fifth step includes a step of outputting, as an error, a location where each of the misalignment directions is the same direction and at least one absolute value of each misalignment amount is a predetermined value or more. The proximity effect correction verification method according to claim 1. A first step of outputting a correction pattern by performing proximity effect correction on the design pattern using a predetermined correction rule;
A second step of outputting a first simulation pattern by simulating a transfer image obtained when the correction pattern is exposed under predetermined conditions;
A third step of determining a deviation direction of the first simulation pattern with respect to the design pattern;
A fourth step of outputting a second simulation pattern by simulating a transfer image obtained when the design pattern is exposed under predetermined conditions;
A fifth step of determining a deviation direction of the second simulation pattern with respect to the design pattern;
The shift direction of the first simulation pattern determined in the third step is compared with the shift direction of the second simulation pattern determined in the fifth step, and the shift directions are the same direction. A proximity effect correction verification method, comprising: a sixth step of outputting as an error a portion to become. The third step includes a step of determining a deviation amount in the deviation direction together with a deviation direction of the first simulation pattern with respect to the design pattern,
The fifth step includes a step of determining a deviation amount in the deviation direction together with a deviation direction of the second simulation pattern with respect to the design pattern,
The sixth step is a location where the respective shift directions are the same direction, and the absolute value of the shift amount determined in the third step is the absolute value of the shift amount determined in the fifth step. The method for verifying proximity effect correction according to claim 3, further comprising a step of outputting a portion that becomes larger as an error. An input unit for inputting a design pattern;
A correction pattern is created by performing proximity effect correction on the design pattern input to the input unit using a predetermined correction rule, and a first shift direction of the correction pattern with respect to the design pattern is determined. A determination unit of
A simulation image is created by simulating a transfer image obtained when the design pattern input to the input unit is exposed under a predetermined condition, and the simulation pattern is shifted from the design pattern. A second determination unit for determining a direction;
The shift direction of the correction pattern determined by the first determination unit in the previous period is compared with the shift direction of the simulation pattern determined by the second determination unit in the previous period. A proximity effect correction verification apparatus comprising: an output unit that outputs an error. The first determination unit determines a shift amount in the shift direction together with a shift direction of the correction pattern with respect to the design pattern,
The second determination unit determines a shift amount in the shift direction together with a shift direction of the simulation pattern with respect to the design pattern,
6. The output unit according to claim 5, wherein the output unit outputs, as an error, a portion where each of the shift directions is the same direction and at least one absolute value of each shift amount is a predetermined value or more. Proximity effect correction verification device. An input unit for inputting a design pattern;
When a correction pattern is created by performing proximity effect correction on the design pattern input to the input unit using a predetermined correction rule, and the correction pattern is exposed under predetermined conditions A first determination unit that creates a first simulation pattern by simulating a transfer image obtained in step S1 and determines a direction of deviation of the first simulation pattern from the design pattern;
A second simulation pattern is created by simulating a transfer image obtained when the design pattern input to the input unit is exposed under a predetermined condition, and the second simulation pattern is generated. A second determination unit that determines a deviation direction of the design pattern;
The deviation direction of the first simulation pattern determined by the first determination unit in the previous period is compared with the deviation direction of the second simulation pattern determined by the second determination unit in the previous period. A proximity effect correction verification device, comprising: an output unit that outputs a portion in the same direction as an error. The first determination unit determines a shift amount in the shift direction together with a shift direction of the first simulation pattern with respect to the design pattern,
The second determination unit determines a shift amount in the shift direction together with a shift direction of the second simulation pattern with respect to the design pattern,
The output unit is a location where the respective shift directions are the same direction, and the absolute value of the shift amount determined by the first determination unit is the absolute value of the shift amount determined by the second determination unit. The proximity effect correction verification apparatus according to claim 7, wherein a portion that is larger than the output is output as an error.

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