KR101095062B1 - Method for verifing of optical proximity correction - Google Patents

Abstract

The present invention discloses a method of verifying optical proximity effect compensation.

The method of verifying optical proximity effect compensation of the present invention includes performing optical proximity effect correction on a target layout, performing after development inspection (ADI) simulation on the optical proximity effect corrected OPC layout, and performing the ADI simulation. And measuring a threshold plot for the image obtained through the step, and detecting a defect using the threshold plot.

Optical Proximity Compensation Verification, Threshold Plot

Description

Method for verifing of optical proximity correction

The present invention relates to a verification method after optical proximity effect correction, and more particularly, to a verification method for an OPC layout in which optical proximity effect correction is completed.

Optical lithography is generally used as a technique for transferring a pattern formed on an exposure mask to a semiconductor substrate.

Through an optical lithography process, an exposure source having passed through optical lenses including a plurality of lenses, filters, and mirrors passes through an opening area of the exposure mask to expose a photosensitive film coated on a semiconductor substrate, thereby forming the same shape as the various patterns formed on the exposure mask. To form a photosensitive film pattern.

A semiconductor device having a desired pattern is formed by etching the etched layer formed under the photosensitive film using the photosensitive film pattern as an etching mask.

At this time, as the size and spacing of the pattern gradually decrease due to the reduction of design rules due to the high integration of the semiconductor device, the size of the semiconductor device pattern approaches the wavelength of the light source, thereby affecting the exposure mask under the influence of light diffraction and interference. It is not formed in the form of the formed pattern but is formed distorted.

This phenomenon is called the optical proximity effect (OPE). If the pattern is not the same size and spacing, the optical proximity effect is further maximized so that the exposure source is overexplosure at the corner or corner of the pattern. Or under explosure, whereby the mask pattern of the corner portion or corner portion may be distorted and rounded on the wafer.

Due to this effect, the pattern is deformed or shifted so that the overlap margin of the upper layer and the lower layer may be reduced, that is, in the case of important parts such as the contact hole pattern connected to the circuit pattern, the circuit pattern and the contact hole. This unconnected or connected area is reduced, which may adversely affect the characteristics of the semiconductor device.

In order to overcome the optical proximity effect, various methods have been proposed, one of which is to add a sub-resolution or smaller pattern to the exposure mask pattern so as to be implemented on the semiconductor substrate as the pattern of the exposure mask without being affected by various optical phenomena. Optical proximity correction (OPC) method using the erasing method.

As described above, the manufacturing method of the exposure mask according to the related art in which the optical proximity effect is corrected is as follows.

First, the target layout is designed and corrected for the optical proximity effect.

At this time, in order to be implemented in the form of the target layout by the method of optical proximity effect correction, for example, to overcome the problem of rounding the end of the line pattern (line end) such as line end treatment (line end treatment) You can add serif patterns or hammer patterns.

In addition, a plurality of sub resolution scattering bars may be added around the target pattern in order to minimize the line width variation of the pattern according to the pattern density.

In addition, the OPC program organizes the experience of a lithography engineer into rules to rule out the layout, and the model based method to correct the layout using the mathematical model of the lithography system. It can be divided into.

Through various methods as described above, the expected weak point is detected even after the optical proximity effect is corrected, which is performed through model based verification (MBV).

Model-based verification verifies areas where pattern defects can occur on a semiconductor substrate when a design layout in which optical proximity effect correction has been made is formed on a semiconductor substrate by a lithography process using the exposure mask.

Such model-based verification may be performed between the line pattern of the upper pattern or the lower pattern and the contact hole pattern connected thereto. When the contact hole pattern is circular or elliptical, the degree of overlap between the line pattern and the contact hole pattern is specified. Can be achieved by

That is, the distance between the contact hole pattern and the contact hole pattern that is connected to the line pattern is out of the distance or the out of area.

However, in this case, when the contact hole pattern is not a circular or elliptical line type or a trench, there is a problem in that verification cannot be performed by measuring an overlap area or an out-of-distance with the line pattern as in the related art.

The present invention is to solve the problem that the verification is not made accurately because the line-type hole or trench can not accurately measure the overlap area or the distance away from the line pattern connected thereto.

The verification method of optical proximity effect correction of the present invention comprises the steps of performing optical proximity effect correction on a target layout;

Performing after development inspection (ADI) simulation on the optical proximity effect corrected OPC layout;

Measuring a threshold plot for the image obtained through the ADI simulation; and

Detecting a defect using the threshold plot.

In this case, the ADI simulation is characterized in that it comprises a simulation for implementing an image of the photoresist pattern on the wafer.

The threshold plot may be divided into a point where the photoresist pattern is formed and a point where the photoresist pattern is not formed based on a threshold level reference value.

In addition, detecting defects using the threshold plot may include a threshold plot for an ADI simulation of a line type hole or trench OPC layout and a threshold for an ADI simulation of a line pattern OPC layout overlapping with the line type hole or trench. By overlapping the plot, the threshold level reference value is detected.

In this case, the OPC layout of the line pattern may include a gate layout.

The line-type hole or trench OPC layout may include a recess gate layout.

The verification method of the optical proximity effect correction according to the present invention has an advantage of more accurately verifying a semiconductor device having a weak CD variation or overlap margin, such as when a line-type hole or trench is connected to a line pattern. .

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

1 is a flowchart illustrating a method of verifying optical proximity effect correction according to the present invention.

First, a target layout is designed (S1).

In this case, the target layout may be understood as a process of designing a layout of a target pattern to be implemented on the wafer.

Next, optical proximity effect correction is performed on the target layout (S2).

In this case, the optical proximity effect correction is an operation for obtaining a wafer image of a shape that is not distorted from the shape of the target layout. After performing calibration using data of a test pattern to describe a process of obtaining a wafer image, an exposure process is performed. Modeling may be included in consideration of effects such as an optical proximity effect that may occur during the process.

Next, after developmet inspection (ADI) simulation is performed on the OPC layout whose target layout is optical proximity effect corrected (S3).

The ADI simulation may be a simulation of the photoresist pattern obtained through modeling in consideration of effects such as an optical proximity effect that may occur during the exposure process.

In this case, the layout of the line pattern in which the optical proximity effect is completed is a gate layout as an embodiment, and the layout of the hole or trench of the line type in which the optical proximity effect is connected to the layout is a recess gate layout as an embodiment.

However, the present invention is not limited thereto and may be changed to a line pattern having a high CD variation or a pattern having a weak overlap margin.

An ADI simulation image of the gate layout (hereinafter referred to as a "gate OPC layout") in which the optical proximity effect correction has been completed and the recess gate layout (hereinafter referred to as a "recess gate OPC layout") in which the optical proximity effect correction has been completed are obtained. If you overlap the ADI simulation image of ().

2 is an image in which an ADI simulation image of a gate OPC layout and an ADI simulation image of a recess gate OPC layout overlap.

Referring to FIG. 2, in the center of the cell array region, the ADI simulation image 101 of the gate OPC layout completely surrounds the ADI simulation image 102 of the recess gate OPC layout, so that the two images coincide.

However, in the outer portion of the cell array region, it can be seen that the ADI simulation image 102 of the recess gate OPC layout is far outward of the ADI simulation image 101 of the gate OPC layout and the two images do not coincide.

Next, a threshold plot of the ADI simulation image of the gate OPC layout and the ADI simulation image of the recess gate OPC layout is measured (S4).

In this case, the gate OPC layout and the recess gate OPC layout ADI simulation image may be a simulation image for predicting the photoresist pattern to be implemented on the wafer.

In addition, the threshold plot shows an image profile of the ADI simulation image of FIG. 2, and is a graph which can confirm the formation of the photoresist pattern using the photoresist pattern predictable through the ADI simulation image.

The point that becomes the threshold level reference value of the threshold plot may be understood as an optimal energy level at which the photoresist film is formed as a relative reference point at which the photoresist pattern is formed.

When the threshold level reference value is 0.5, it may be understood that the photoresist pattern is formed at the point where the threshold level reference value is 0.5 or less, and that the photoresist pattern is not formed at the point where the threshold level reference value exceeds 0.5.

In the present invention, the threshold level reference value is 0.5, but this is not necessarily the case.

Next, the defect is detected using the threshold plot (S5).

FIG. 3 is a threshold plot of the photoresist pattern for the gate OPC layout and the photoresist pattern for the recess gate OPC layout, FIG. 4 is a threshold plot showing the cell array center of the gate OPC layout and the recess gate OPC layout, and FIG. 5 is A threshold plot showing the cell array outline of the gate OPC layout and recess gate OPC layout.

Referring to FIG. 3, first, in the threshold plot 201 of the photoresist pattern of the gate OPC layout, a point at which the threshold level reference value is 0.5 or less is a portion where the photoresist pattern for forming the gate pattern is formed later, and the threshold level reference value exceeds 0.5. One point may be understood as a portion where the photoresist pattern is not formed.

Similarly, in the threshold plot 202 of the photoresist pattern of the recess gate OPC layout, a point where the threshold level reference value is 0.5 or less is a portion where the photoresist pattern is formed so that a recess gate is not formed later, and a point that exceeds the threshold level reference value 0.5 is It can be understood as a portion where the photoresist pattern is not formed to form a recess gate later.

Referring to FIG. 3 again, at the center of the cell array, the threshold plots of the photoresist pattern of the gate OPC layout and the photoresist pattern of the recess gate OPC layout are crossed at regular intervals to form the photoresist pattern of the recess gate. It can be seen that the photoresist pattern of the gate is formed on the portion that is not.

However, in the outer portion of the cell array, the threshold plots of the photoresist pattern of the gate OPC layout and the photoresist pattern of the recess gate OPC layout do not cross at regular intervals, so that the photoresist pattern of the gate is a portion where the photoresist pattern of the recess gate is not formed. That is, it can be seen that the portion that does not surround the recess gate is formed.

Referring to FIG. 4, when the threshold plot of the center of the cell array is examined in detail, a portion where the threshold plot 201 of the photoresist pattern of the gate OPC layout is less than or equal to a threshold level reference value of 0.5, that is, a portion where the gate pattern is formed may be formed in the recess gate OPC layout. The threshold plot 202 for the photoresist pattern includes a portion exceeding a threshold level reference value of 0.5, that is, a portion in which a recess gate is formed.

It can be understood that the gate is connected to the portion where the recess gate is formed.

Referring to FIG. 5, in detail, the threshold plot of the cell array outer periphery is illustrated in FIG. 5, where the threshold plot 202 for the photoresist pattern of the recess gate OPC layout exceeds the threshold level reference value 0.5. Since the plot 201 also exceeds the threshold level reference value of 0.5, the gate pattern is not formed to be connected to the portion where the recess gate is formed, but it is confirmed that the plot 201 is formed as much as (a) from the recess gate.

This can be understood as being formed so that the gate is not connected to the portion where the recess gate is formed.

As described above, after a simulation is performed on the line pattern of which the optical proximity effect is corrected and the layout of the hole or trench of the line type connected thereto, a defect plot of the unconnected portion may be detected using a threshold plot of the photoresist pattern. Can be.

1 is a flow chart for a method of verifying optical proximity effect correction in accordance with the present invention.

2 is an image in which an ADI simulation image of a gate OPC layout and an ADI simulation image of a recess gate OPC layout overlap.

3 is a threshold plot of the photoresist pattern for the gate OPC layout and the photoresist pattern for the recess gate OPC layout.

4 is a threshold plot showing the cell array center of the gate OPC layout and the recess gate OPC layout.

5 is a threshold plot showing the cell array outline of the gate OPC layout and the recess gate OPC layout.

Claims (6)

Performing optical proximity effect correction on the target layout; Performing after development inspection (ADI) simulation on the optical proximity effect corrected OPC layout; Measuring a threshold plot for the image obtained through the ADI simulation; And Detecting a defect using the threshold plot, Detecting a defect using the threshold plot Overlap the threshold plot for the ADI simulation of the line type hole or trench OPC layout and the threshold plot for the ADI simulation of the line pattern OPC layout overlapping the hole or trench of the line type with respect to the threshold level reference value. And detecting the optical proximity effect correction. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, The ADI simulation includes a simulation for implementing an image of a photoresist pattern on a wafer. Claim 3 was abandoned when the setup registration fee was paid. 3. The method of claim 2, And the threshold plot is divided into a point at which the photoresist pattern is formed and a point at which the photoresist pattern is not formed, based on a threshold level reference value. delete Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, And the OPC layout of the line pattern comprises a gate layout. Claim 6 was abandoned when the registration fee was paid. The method of claim 1, And the OPC layout of the line-type holes or trenches includes a recess gate layout.

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