KR100944332B1 - Method for manufacturing mask of the semiconductor device and method for manufacturing the semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a mask and a method for manufacturing a semiconductor device, the process of changing the process by increasing the size of the original mask layout designed to a minimum size within the range that satisfies the Design Rule and Disclosed is a technique for providing a stable mask layout against a focus change of an exposure apparatus and improving a patterning accuracy and an overlap margin to improve device characteristics.

Description

Method for manufacturing a mask of a semiconductor device and a method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING MASK OF THE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a mask of a semiconductor device and a method for manufacturing a semiconductor device. In particular, the present invention relates to a method for correcting optical proximity effects during mask fabrication.

As semiconductor devices are highly integrated, the size of patterns required for semiconductor devices is gradually decreasing. As the size of a pattern decreases, an optical proximity effect (OPE) is generated in an exposure process due to influence between adjacent patterns. In order to overcome this problem, optical proximity correction (OPC) is performed to correct a layout of a pattern to suppress a pattern distortion caused by an optical proximity effect.

Here, the optical proximity effect correction is to correct the layout of the target pattern to be patterned on the wafer in consideration of the optical proximity effect.

Referring to the mask manufacturing method of the semiconductor device according to the prior art, the original layout (Layout) of the target pattern (Target Pattern) to be formed on the wafer is designed.

Next, when the design rule of the original layout is checked and does not violate the intended design rule, an optical proximity effect correction (OPC) is performed on the original layout to design the final layout. .

Next, a photo mask is fabricated using the data of the final layout.

In the method of manufacturing a mask and a method of manufacturing a semiconductor device according to the prior art described above, if the design rule for the original layout is not checked and it does not violate the intended design rule, the optical layout effect correction is performed to perform the final layout. And a photomask is produced using the data of the final layout. Therefore, even if the space (Space) outside the pattern on the final layout is enough there is a problem that does not fully utilize the space. In addition, the pattern formed on the wafer is sensitive to the change in the process or the focus of the exposure apparatus during the exposure process using the photo mask formed by combining the data of the layout designed to the minimum size. There is a problem that the production rate of the device is lowered due to the lack of open or overlap margin.

The present invention executes an algorithm for increasing the size of the target pattern by a predetermined size with respect to the original layout on which the target pattern is formed to increase the size of the pattern as much as possible within the range that does not violate the design rule to obtain a final layout. Subsequently, a mask is manufactured using the final layout to form a mask that is stable to a process change and a focus change, and the patterning is performed using the mask to improve patterning margin and overlap margin, and a method of manufacturing a semiconductor device. The purpose is to provide.

Mask manufacturing method of a semiconductor device according to the present invention

Designing the original mask layout,

Forming a plurality of first polygonal sites on corner and edge lines of the polygons formed in the mask layout;

Moving the plurality of first polygonal sites in a direction of expanding the size of the polygon to form a plurality of second polygonal sites;

Forming a modified mask layout using the plurality of second polygonal sites as corner and edge lines;

First verifying the modified mask layout;

Repositioning the second polygonal site of the portion of the plurality of second polygonal sites that has not passed the verifying step into the first polygonal site;

And secondly verifying the modified mask layout,

Fabricating a mask using the modified mask layout that has passed the verifying step;

The mask layout is composed of a plurality of polygons (Polygon),

The polygon is in the form of a line, the form of a contact pad, and a combination thereof;

The first and second verification step is

Determining whether the modified mask layout violates an intended design rule;

The method may further include modifying the mask layout when the determination result violates the intended design rule.

The method may further include performing optical proximity effect correction (OPC) on the verified mask layout.

In addition, the method of manufacturing a semiconductor device according to the present invention

Forming an etched layer and a photoresist on the semiconductor substrate;

Forming a photoresist pattern by performing exposure and development processes on the photoresist using a mask manufactured by the mask manufacturing method;

And etching the etched layer using the photoresist pattern as a mask.

The method of manufacturing a mask of a semiconductor device and the method of manufacturing a semiconductor device according to the present invention increase the size of an original mask layout designed to a minimum size as much as possible within a range that satisfies a design rule and change of exposure process and exposure equipment. It provides a stable mask layout against a focus change of, which improves patterning accuracy and overlap margin, thereby improving device characteristics.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

1 is a flowchart schematically showing a method for manufacturing a mask of a semiconductor device of the present invention.

Referring to FIG. 1, an original layout of a target pattern to be formed on a wafer is designed (S100).

Next, a plurality of first polygonal sites are formed on corners and edge lines of the pattern formed in the original layout (S110). In this case, a polygon is divided into a line shape and a contact pad shape by the first polygonal site.

Then, the first polygonal site is moved by 'd' outside of the pattern, that is, in a direction in which the size of the pattern is expanded. At this time, the moved first polygonal site is defined as a second polygonal site (S120 and S130).

Next, a design rule is checked for a modified layout in which the second polygon site is a corner and an edge line (S140). Here, the design rule check refers to determining whether the modified mask layout violates the intended design rule.

At this time, the second polygonal site of the evaluation point determined to be unsuitable through the design rule check is returned to the first polygonal site position of the original layout (S145).

Then, the second polygonal site of the evaluation point determined to be bonded through the design rule check is again moved by 'd' in the direction in which the size of the pattern is expanded.

In step S140, the design rule is checked to determine whether it violates the design rule.

As described above, the process of 'S110' to 'S140' is repeated to obtain a final layout in which a pattern having a maximum size is expanded within a range that satisfies a design rule, and then optical proximity effect correction is performed on the final layout.

Next, a photomask is produced by combining the data of the final layout corrected for the optical proximity effect.

2A to 2C are layouts showing a mask manufacturing method of the semiconductor device of the present invention.

Referring to FIG. 2A, an original layout of a target pattern to be formed on a wafer is illustrated, and the first pattern 200, the contact pad 210a and the line pattern (in the form of isolation lines) are formed. A second pattern 210 formed by 210b is shown. Here, the first pattern 200 and the second pattern 210 are adjacent to each other in a parallel form. At this time, the CD (Critical Dimension) of the contact pad 210a is formed to be larger than the CD of the line pattern 210a in contact.

Next, first polygonal sites 220a are formed on corners and edge lines of the first and second patterns 200 and 210 formed in the original layout. In this case, the first polygon site 220a is mainly formed at the corners of the first and second patterns 200 and 210, and the first polygonal site 220a is adjacent to the contact pad 210a of the second pattern 210. It is also formed on the edge line.

2B and 2C, a direction in which the size of the first pattern 200 and the second pattern 210 extends from the first polygonal site 220a formed on the original layout shown in FIG. 2A. Move by 'd'. Here, the first polygon site 220a moved by 'd' is defined as the second polygon site 220b.

Next, a modified layout is formed, with the second polygon site 220b as corner and edge lines.

Then, the first verification of the modified layout is performed.

Here, the verifying step is performed for each evaluation point, and refers to determining whether the modified layout violates the intended design rule. As a result of the first verification, when the designer does not meet the intended design rule, the mask layout should be modified.

For example, as shown in 'A' of FIG. 2C, the second polygon site 220b of the evaluation point that does not satisfy the design rule in the first verification is relocated to the first polygon site 220a on the original layout. At this time, if the design rule is not satisfied between the contact pad 210a form and the line pattern, it is preferable to reduce the size of the line pattern.

As such, when the design rule is not satisfied, only some regions may not increase in size.

Next, the second polygon site 220b is moved by 'd' in the pattern of the size that satisfies the design rule, and the layout of the second polygon site 220b as the edge line is secondly verified.

As such, after increasing the size of the target pattern formed on the original layout by a predetermined size, the design rule is checked, and the portion that violates the design rule is modified to the size of the original target pattern, and the portion that satisfies the design rule is again constant. Increase by size At this time, the step of increasing the size of the target pattern by a predetermined size may be repeatedly performed.

Next, the verification is again performed on the modified layout, and when the modified layout satisfies the design rule check, the final layout 230 is obtained with data for each polygon site.

Next, optical proximity effect correction is performed on the final layout 230.

Then, a photomask is fabricated using the data of the final layout with the optical proximity effect corrected.

Referring to the method of manufacturing a semiconductor device using the photomask formed through the mask manufacturing method of the semiconductor device described above, an etched layer and a photosensitive film are formed on the semiconductor substrate.

Next, an exposure process is performed on the photosensitive film using a mask formed using the final layout corrected for the optical proximity effect as described above.

Next, the exposed photoresist is developed to form a photoresist pattern in which a target pattern is defined. In this case, since the exposure mask of the present invention extends the target pattern of the original layout as much as possible within the range that does not violate the design rule, the exposure mask may perform a stable process against a change in the process and a change in focus of the exposure apparatus.

1 is a process flow diagram schematically showing a method for manufacturing a mask of a semiconductor device according to the present invention.

2A to 2C are layouts showing a mask manufacturing method of a semiconductor device according to the present invention.

<Explanation of Signs of Major Parts of Drawings>

200: first pattern 210: second pattern

220a: first polygon site 220b: second polygon site

230: final layout

Claims (8)

Designing an original mask layout; Forming a plurality of first polygonal sites on corner and edge lines of the polygons formed in the mask layout; Moving the plurality of first polygonal sites in a direction of expanding the size of the polygon to form a plurality of second polygonal sites; Forming a modified mask layout using the plurality of second polygonal sites as corner and edge lines; First verifying the modified mask layout; Repositioning the second polygonal site of the portion of the plurality of second polygonal sites that has not passed the verifying step into the first polygonal site; And And secondly verifying the modified mask layout. The method of claim 1, And performing the first and second verification steps repeatedly. The method of claim 1, And fabricating a mask using the modified mask layout that has passed the verifying step. The method of claim 1, The mask layout method of manufacturing a mask of a semiconductor device, characterized in that consisting of a plurality of polygons (Polygon). The method of claim 4, wherein The polygon is a mask manufacturing method of a semiconductor device, characterized in that the line form, the contact pad form and combinations thereof. The method of claim 1, The first and second verification step is Determining whether the modified mask layout violates an intended design rule; And The method of manufacturing a mask of a semiconductor device according to the determination result, further comprising the step of modifying the mask layout in case of violation of the intended design rule. The method of claim 1, And performing optical proximity effect correction (OPC) on the verified mask layout. Forming an etched layer and a photosensitive film on the semiconductor substrate; Forming a photoresist pattern by performing exposure and development processes on the photoresist using a mask fabricated by the method of claim 1; And Etching the etched layer using the photoresist pattern as a mask Method of manufacturing a semiconductor device comprising a.

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