CN110068986B - Method of trimming pattern, medium, server, and method of manufacturing photomask - Google Patents
Method of trimming pattern, medium, server, and method of manufacturing photomask Download PDFInfo
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- CN110068986B CN110068986B CN201910238963.8A CN201910238963A CN110068986B CN 110068986 B CN110068986 B CN 110068986B CN 201910238963 A CN201910238963 A CN 201910238963A CN 110068986 B CN110068986 B CN 110068986B
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/82—Auxiliary processes, e.g. cleaning or inspecting
- G03F1/84—Inspecting
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Abstract
The invention provides a method for trimming a pattern, a medium, a server and a method for manufacturing an optical mask, wherein the method for trimming the pattern comprises the following steps: simulating the surface topography of the wafer by using a chemical mechanical polishing model to obtain a topography map, wherein the topography map represents the height of the surface of the wafer; marking an area of the surface of the wafer, which does not accord with the preset height, to obtain the information of the step height marking layer; establishing a corresponding depth-of-field model according to the information of the level-height mark layer; and carrying out optical proximity correction processing on the graph to be trimmed by utilizing the depth of field model. The method for correcting the graph can detect the hot spot problem on the uneven area of the surface of the wafer, and can improve the yield of devices by correcting and optimizing the bad influence caused by the problem through the graph.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a method for trimming a pattern, a medium, a server and a manufacturing method of an optical mask.
Background
Optical Proximity Correction (OPC) is a lithography enhancement technique that affects the resulting image errors. Optical proximity correction is mainly used in the production of semiconductor devices in order to ensure that the edges of the patterns designed in the production process are completely etched. If the projection image has illegal behaviors, such as line width is narrower or wider than the design, the imaging can be compensated by changing the mask plate. Other distortions, such as rounding, are more difficult to compensate for due to the resolution of the optical tool. These distortions, if not corrected, can greatly alter the electrical performance of the produced circuit. Optical proximity correction corrects these errors by moving the edges of the pattern on the reticle or adding additional polygons. The goal of optical proximity correction is to make the circuits produced on the silicon wafer as consistent as possible with the circuits of the mask design.
The existing simulation and correction of optical proximity correction are based on data of a flat wafer, and the real morphology condition of the wafer is not considered, so that the yield of the prepared device is low.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a method for trimming a pattern, a medium, a server and a method for manufacturing an optical mask, which are used to solve the problem that the simulation or/and correction of the existing optical proximity correction does not consider the real shape and appearance of the wafer to affect the yield of the device.
To achieve the above and other related objects, the present invention provides a method of trimming a pattern, the method comprising: simulating the surface topography of the wafer by using a chemical mechanical polishing model to obtain a topography map, wherein the topography map represents the height of the surface of the wafer; marking an area of the surface of the wafer, which does not conform to the preset height, and obtaining step height marking layer information; establishing a corresponding depth-of-field model according to the level mark layer information; and carrying out optical proximity correction processing on the graph to be trimmed by utilizing the depth of field model.
In an embodiment of the present invention, the marking the region of the wafer surface that does not conform to the predetermined height to obtain the information of the step-height mark layer includes: dividing the surface of the wafer into different areas according to the height of the surface of the wafer, wherein the heights of adjacent areas are different; the area which accords with the preset height is a non-trimming area, and the area which does not accord with the preset height is an area to be trimmed; marking each area to be trimmed by using a GDS marking layer mode to obtain the step height marking layer information of the corresponding area; the regions to be trimmed with the same height obtain the same level mark layer information.
In an embodiment of the present invention, a method for dividing a wafer surface into different regions according to a height of the wafer surface includes: dividing the surface of the wafer into different areas according to the height difference of the surface of the wafer; the division mode includes: the height difference accords with a preset division range or a preset division value.
In an embodiment of the present invention, an implementation process of establishing a corresponding depth of field model according to the information of the level-height mark layer includes: obtaining a focal length corresponding to the order height according to the order height marking layer information, and establishing an optical model under the corresponding focal length, namely the depth of field model; the focal length of the depth-of-field model is matched with the corresponding order height; the step height is the height difference.
In an embodiment of the present invention, an implementation process of performing optical proximity correction processing on a graph by using the depth of field model includes: selecting exposure patterns in the regions corresponding to the depth-of-field model simulation matched with the regions according to the region division of the surface of the wafer; comparing the exposed graph with a mask plate design graph to obtain an edge error; judging whether the edge error meets a preset range or not; if so, finishing; otherwise, moving the edge position of the exposed graph, and continuously comparing with the design graph of the mask plate until the edge error meets the preset range.
In an embodiment of the invention, the method for trimming a pattern further includes: and carrying out optical rule checking processing on the graph after the optical proximity correction processing.
In an embodiment of the invention, the method for trimming a pattern further includes: generating the chemical mechanical polishing model based on preset information; the preset information comprises wafer related information and process related information; the wafer related information comprises: the pattern size and the error range of the wafer required during photoetching, and the height and the error range of the surface of the wafer after chemical mechanical polishing; the process related information includes: the required depth of field during photoetching and the bad point of the pattern during exposure.
In an embodiment of the invention, an implementation process of the method for trimming a graphic includes: generating a first GDS file based on preset information; the preset information comprises wafer related information and process related information; performing standard optical proximity correction based on the first GDS file to generate a standard optical proximity correction result; performing standard optical rule check based on the standard optical proximity correction result to generate a second GDS file; simulating the surface topography of the wafer by using a chemical mechanical polishing model based on the first GDS file; and importing the information of the depth of field models corresponding to different areas into the second GDS file to generate a third GDS file.
In an embodiment of the invention, the method for trimming a pattern further includes: and performing optical rule checking processing on the third GDS file based on the depth of field model to generate a fourth GDS file.
In an embodiment of the invention, another implementation process of the method for trimming a pattern includes: generating a first GDS file based on preset information; the preset information comprises wafer related information and process related information; simulating the surface topography of the wafer by using a chemical mechanical polishing model based on the first GDS file; generating a fifth GDS file based on the information of the depth-of-field model corresponding to the different areas; and performing optical proximity correction processing on the fifth GDS file based on a depth of field model to generate a sixth GDS file.
In an embodiment of the invention, the method for trimming a pattern further includes: and carrying out optical rule checking processing on the sixth GDS file based on a depth of field model to generate a seventh GDS file.
The invention also provides a manufacturing method of the optical mask, and the mask pattern on the optical mask is corrected by using the method for trimming the pattern.
The invention also provides a semiconductor device manufacturing method, and in the manufacturing process of the semiconductor device, the optical mask pattern is corrected by using the method for trimming the pattern.
The invention also provides a server, comprising a memory and a processor; the memory stores a computer program; the computer program, when called by the processor, performs the method of trimming graphics.
The invention also provides a medium storing a computer program; the computer program, when called by a processor, performs the method of trimming a graphic.
As described above, the method for trimming a pattern, the medium, the server, and the method for manufacturing an optical mask according to the present invention have the following advantageous effects:
the method for correcting the graph can detect the hot spot problem on the uneven area of the surface of the wafer, and can improve the yield of devices by correcting and optimizing the bad influence caused by the problem through the graph.
Drawings
FIG. 1A is a schematic flow chart of a conventional optical proximity correction.
FIGS. 1B and 1C are schematic views showing the processing results of real wafers with the same design pattern at different exposure focal lengths.
Fig. 2A and fig. 2B are schematic diagrams illustrating an implementation flow of a method for trimming a pattern according to an embodiment of the present invention.
Fig. 3 is a schematic flow chart illustrating an implementation of step S202 of the method for trimming a pattern according to the embodiment of the present invention.
Fig. 4A and 4B are reference diagrams illustrating a method for trimming a pattern according to an embodiment of the invention.
Fig. 5 is a flowchart illustrating an implementation of step S204 of the method for trimming a pattern according to the embodiment of the present invention.
Fig. 6A and fig. 6B are schematic diagrams illustrating a flowchart of an embodiment of a method for trimming a pattern according to an embodiment of the invention.
Fig. 7A and 7B are schematic diagrams illustrating another specific implementation flow of the method for trimming a pattern according to the embodiment of the invention.
FIG. 8 is a schematic diagram illustrating an adjustment of an edge inner position error according to an embodiment of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Both simulation and Correction of the conventional Optical Proximity Correction (OPC) are based on data of a flat wafer, and do not consider the real topography of the wafer, and the conventional Optical Rule Check (Optical Rule Check) based on an Optical Proximity Correction model also does not consider the real topography of the wafer, so that the problem of low yield of the manufactured devices due to the influence of the wafer surface cannot be detected, as shown in fig. 1A. FIGS. 1B and 1C show the same design for processing a real wafer at different exposure focal lengths, wherein the abscissa represents the focal length (focus) from the projection lens to the wafer during exposure of the lithography machine, and the ordinate represents the line width corresponding to each focal length on the wafer; the different lines in the graph represent different energies (energy) used during wafer exposure, and each line represents an energy.
To solve the above problem, an embodiment of the present invention provides a method for trimming a pattern, as shown in fig. 2A, the method including:
s201, simulating the surface topography of the wafer by using a Chemical Mechanical Polishing (CMP) model to obtain a topography map, wherein the topography map reflects the height of the surface of the wafer.
In an embodiment of the invention, the chemical mechanical polishing model is generated based on preset information; the preset information comprises wafer related information and process related information; the wafer related information comprises: the pattern size and the error range of the wafer required during photoetching, and the height and the error range of the surface of the wafer after chemical mechanical polishing; the process related information includes: the required depth of field during photoetching and the dead pixel of the pattern during exposure. The preset information (tech information) related to the present invention mainly relates to the pattern size of the wafer required in the photolithography and the allowable error range, for example, the pattern size target is 50nm, and the error is ± 5nm; after the CMP, the height of the wafer surface is required and the allowable error range is, for example, 200nm for the height requirement, and the error is ± 20nm. The process includes required depth of focus during photolithography, bad point of pattern during exposure, etc.
S202, marking the area of the surface of the wafer, which does not accord with the preset height, and obtaining the information of the step height marking layer.
S203, establishing a corresponding depth of field model according to the information of the level mark layer.
And S204, performing optical proximity correction processing on the graph to be trimmed by utilizing the Depth of Field (DOF) model.
In an embodiment of the invention, referring to fig. 2B, the method for trimming a pattern further includes:
s205, carrying out optical rule checking processing on the graph after the optical proximity correction processing.
In an embodiment of the present invention, referring to fig. 3, the step S202 of marking the region of the wafer surface that does not conform to the predetermined height to obtain the information of the step mark layer includes:
s301, dividing the surface of the wafer into different areas according to the height of the surface of the wafer, wherein the adjacent areas have different heights; the area which accords with the preset height is a non-trimming area, and the area which does not accord with the preset height is an area to be trimmed;
s302, marking each area to be trimmed by using a GDS (graphic file format) marking layer mode to obtain the step height marking layer information of the corresponding area; the regions to be trimmed with the same height obtain the same level mark layer information. GDS is the most common graphic data description language file format used in integrated circuit layout design.
In an embodiment of the present invention, an implementation method for dividing a wafer surface into different regions according to a height of the wafer surface includes: dividing the surface of the wafer into different areas according to the height difference of the surface of the wafer; the dividing method comprises the following steps: the height difference accords with a preset division range or the height difference accords with a preset division value. For example: the difference in height accords with and predetermines the partition scope to flat face is the standard, and it is 0um to establish the height, and the difference in height is a step height region for 0 ~ 0.3um, and the difference in height is a step height region for-0.3 um ~ 0 um. For example: the difference in height accords with preset division value to the level is the standard, establishes highly to be 0um, highly to be 0.1um for a step height region, highly to be 0.2um for a step height region, highly to be-0.1 um for a step height region, highly to be-0.2 um for a step height region. Referring to fig. 4, the GDS is divided into different regions according to height difference, each region represents a height, i.e., height marking layer information (DOF marking layer), 11 represents a height difference of 0.3um,12 represents an actually required height of the wafer, and 0um,13 represents a height difference of-0.3 um. The protection scope of the present invention is not limited to the specific division of the regions listed in the present embodiment.
In an embodiment of the present invention, an implementation process of establishing a corresponding depth of field model according to the information of the level-height mark layer includes: obtaining a focal length corresponding to the order height according to the order height marking layer information, and establishing an optical model under the corresponding focal length, namely the depth of field model; the focal length of the depth of field model is matched with the corresponding order height; the step height is the height difference.
In an embodiment of the present invention, referring to fig. 5, an implementation process of performing optical proximity correction processing on a graph by using the depth of field model includes:
s501, selecting exposure patterns in the regions corresponding to the depth-of-field model simulation matched with the regions according to the region division of the surface of the wafer;
s502, comparing the exposed graph with a mask plate design graph to obtain an edge error;
s503, judging whether the edge error accords with a preset range;
s504, finishing trimming if the finishing is finished;
and S505, otherwise, moving the edge position of the exposed graph, and continuously comparing the edge position with the design graph of the mask plate until the edge error meets the preset range.
In an embodiment of the invention, referring to fig. 6A and 6B, an implementation process of the method for trimming a pattern includes:
s601, generating a first GDS file based on preset information; the preset information comprises wafer related information and process related information;
s602, performing standard optical proximity correction based on the first GDS file to generate a standard optical proximity correction result;
s603, standard optical rule checking is carried out based on the standard optical proximity correction result, and a second GDS file is generated;
s604, simulating the surface appearance of the wafer by utilizing a chemical mechanical polishing model based on the first GDS file;
and S605, importing the information of the depth models corresponding to different areas into the second GDS file to generate a third GDS file.
S606, the third GDS file is subjected to optical rule checking processing based on the depth of field model, and a fourth GDS file is generated.
For example: in the GDS, an optical model (DOF model, i.e. depth of field model) is built in the M layer (layer) under standard conditions (no height difference on wafer surface), which is assumed to be a, and the focal length is 0.
Based on the method for trimming the graph, in the step of executing, specifically, the following operations can be executed:
1) First, a Chemical Mechanical Polishing (CMP) simulation is performed on the surface of a wafer (wafer) to obtain a height difference of the wafer surface, GDS is divided into different regions according to the height difference, each region represents a height, that is, height marking layer information (DOF marking layer), as shown in fig. 4A, 11 represents a height difference of 0.3um,12 represents a height actually required by the wafer, and 0um,13 represents a height difference of-0.3 um, and the information is imported into an S-OPCed GDSII file shown in fig. 6A, that is, an Input GDSII for TORC.
2) Different DOF models (depth of field models) are built according to the step difference, a DOF model B is generated by subtracting-0.3 um from the focal length of the DOF model A in a 13 region, and a DOF model C is generated by adding 0.3um to the focal length of the DOF model A in an 11 region with the height difference of 0.3um.
3) And finally, according to the height Marking layer information (DOF Marking layer), adopting corresponding DOF models in different height areas, adopting DOF model C in 11 area, adopting DOF model A in 12 area and adopting DOF model B in 13 area, and simulating the graph to form a T-ORCed Hot Spot GDSII file shown in FIG. 6A.
In an embodiment of the invention, referring to fig. 7A and 7B, another implementation process of the method for trimming a pattern includes:
s701, generating a first GDS file based on preset information; the preset information comprises wafer related information and process related information;
s702, simulating the surface appearance of the wafer by using a chemical mechanical polishing model based on the first GDS file;
s703, generating a fifth GDS file based on the information of the depth of field model corresponding to different areas; the different areas correspond to different depth of field models, and the fifth GDS file is generated based on information of the depth of field models corresponding to the areas divided on the surface of the wafer. For example: and the wafer surface is divided into three areas to be modified, namely an area A, an area B and an area C, wherein the area A corresponds to the depth of field model A, the area B corresponds to the depth of field model B, the area C corresponds to the depth of field model C, and the fifth GDS file is generated based on the information of the depth of field model A, the depth of field model B and the depth of field model C.
S704, performing optical proximity correction processing on the fifth GDS file based on the depth of field model to generate a sixth GDS file.
S705, performing optical rule checking processing on the sixth GDS file based on the depth of field model to generate a seventh GDS file.
The OPC based on DOF Model Database (DOF Model Database) is the optical proximity effect correction based on Model, calculates the exposed pattern by using an optical Model and a photoresist photochemical reaction Model, and corrects the mask pattern by using a calculation method, so that the pattern projected on the photoresist meets the design requirement as much as possible. The DOF model is the optical model at the corresponding focal length. Specifically, referring to fig. 8, the DOF model is used to simulate the pattern edge of the photoresist after exposure of the mask pattern, and the pattern edge is compared with the original design pattern to calculate the edge position error; and moving the edge position during the operation of the correction software, and simulating and calculating a corresponding edge placement error by the DOF model. This process is repeated until the calculated edge position error reaches an acceptable value.
For example: in the GDS, an optical model of the M layer is established under standard conditions (no difference in height of wafer surface), the model is a, and the focal length is 0.
Based on the method for trimming the graph, in the step of executing, specifically, the following operations can be executed:
1) First, a Chemical Mechanical Polishing (CMP) simulation is performed on the surface of a wafer (wafer) to obtain a height difference of the wafer surface, and the GDS is divided into different regions according to the height difference, each region represents a height, i.e., a degree of freedom marking layer information (DOF marking layer), as shown in fig. 4B, 11 represents a height difference of 0.3um,12 represents an actually required height of the wafer, and 0um,13 represents a height difference of-0.3 um.
2) Different DOF models are built according to the step difference, the focus of the DOF model A is subtracted by-0.3 um in a 13 region to generate a DOF model B, and the focus of the DOF model A is added by 0.3um in an 11 region with the height difference of 0.3um to generate a DOF model C.
3) Performing pattern correction by adopting corresponding DOF models in different GDS regions according to the DOF Marking layer information (DOF Marking layer), performing OPC correction by adopting a DOF model C in a region 11, adopting a DOF model A in a region 12 and adopting a DOF model B in a region 13; and finally, adopting corresponding DOF models in different GDS regions according to the degree of freedom Marking layer information (DOF Marking layer), adopting DOF model C in the 11 region, adopting DOF model A in the 12 region and adopting DOF model B in the 13 region to simulate a mask pattern, and outputting a T-OPCed GDSII file shown in the figure 7A.
The embodiment of the invention also provides a manufacturing method of the optical mask, which comprises the following steps: and correcting the mask pattern on the optical mask by using the method for trimming the pattern.
The embodiment of the invention also provides a manufacturing method of the semiconductor device, which comprises the following steps: in the manufacturing process of the semiconductor device, the optical mask pattern is corrected by using the method for trimming the pattern.
The embodiment of the invention also provides a server, which comprises a memory and a processor; the memory stores a computer program; the computer program, when called by the processor, performs the method of trimming graphics described above.
The embodiment of the invention also provides a medium which stores a computer program; the computer program, when called by a processor, performs the method of trimming a graphic described above.
The method for correcting the graph can detect the hot spot problem on the uneven area of the surface of the wafer, and can improve the yield of devices by correcting and optimizing the bad influence caused by the problem through the graph.
In conclusion, the present invention effectively overcomes various disadvantages of the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (14)
1. A method of modifying a feature, the method comprising:
simulating the surface topography of the wafer by using a chemical mechanical polishing model to obtain a topography map, wherein the topography map represents the height of the surface of the wafer;
marking an area of the surface of the wafer, which does not accord with the preset height, to obtain the information of the step height marking layer;
establishing a corresponding depth-of-field model according to the information of the level-height mark layer;
carrying out optical proximity correction processing on the graph to be trimmed by utilizing the depth-of-field model; the method for trimming the graph comprises the following steps:
generating a first GDS file based on preset information; the preset information comprises wafer related information and process related information;
performing standard optical proximity correction based on the first GDS file to generate a standard optical proximity correction result;
performing standard optical rule check based on the standard optical proximity correction result to generate a second GDS file;
simulating the surface topography of the wafer by using a chemical mechanical polishing model based on the first GDS file;
and importing the information of the depth models corresponding to different areas into the second GDS file, and performing optical proximity correction processing on the second GDS file to generate a third GDS file.
2. A method for modifying patterns according to claim 1, wherein the step of marking the regions of the wafer surface that do not conform to the predetermined height comprises the steps of:
dividing the surface of the wafer into different areas according to the height of the surface of the wafer, wherein the heights of adjacent areas are different;
the area which accords with the preset height is a non-trimming area, and the area which does not accord with the preset height is an area to be trimmed;
marking each area to be trimmed by using a GDS marking layer mode to obtain the step height marking layer information of the corresponding area; the regions to be trimmed with the same height obtain the same level mark layer information.
3. A method of modifying a pattern as claimed in claim 2, wherein one method of dividing a wafer surface into different regions based on the height of the wafer surface comprises:
dividing the surface of the wafer into different areas according to the height difference of the surface of the wafer; the dividing method comprises the following steps: the height difference accords with a preset division range or a preset division value.
4. The method for trimming graphics according to claim 2, wherein one implementation of establishing a corresponding depth-of-field model according to the hierarchical mark layer information comprises:
obtaining a focal length corresponding to the order height according to the order height marking layer information, and establishing an optical model under the corresponding focal length, namely the depth of field model; the focal length of the depth of field model is matched with the corresponding order height; the step height is the height difference.
5. The method of claim 3, wherein one implementation of the optical proximity correction processing of the pattern to be trimmed using the depth of field model comprises:
selecting exposure patterns in the regions corresponding to the depth-of-field model simulation matched with the regions according to the region division of the surface of the wafer;
comparing the exposed graph with a mask plate design graph to obtain an edge error;
judging whether the edge error meets a preset range or not;
if so, finishing;
otherwise, moving the edge position of the exposed graph, and continuously comparing with the design graph of the mask plate until the edge error meets the preset range.
6. A method of trimming a pattern according to claim 1, further comprising:
and carrying out optical rule checking processing on the graph after the optical proximity correction processing.
7. A method of trimming a pattern according to claim 1, further comprising:
generating the chemical mechanical polishing model based on preset information; the preset information comprises wafer related information and process related information; the wafer related information comprises: the pattern size and the error range of the wafer required during photoetching, and the height and the error range of the surface of the wafer after chemical mechanical polishing; the process related information includes: the required depth of field during photoetching and the bad point of the pattern during exposure.
8. A method of trimming a pattern according to claim 1, further comprising:
and carrying out optical rule checking processing on the third GDS file based on a depth of field model to generate a fourth GDS file.
9. A method of trimming a pattern according to any one of claims 1 to 7, wherein the method of trimming a pattern comprises:
generating a first GDS file based on preset information; the preset information comprises wafer related information and process related information;
simulating the surface topography of the wafer by using a chemical mechanical polishing model based on the first GDS file;
generating a fifth GDS file based on information of the depth of field model corresponding to different regions;
and carrying out optical proximity correction processing on the fifth GDS file based on the depth of field model to generate a sixth GDS file.
10. A method of trimming a pattern according to claim 9, further comprising:
and carrying out optical rule checking processing on the sixth GDS file based on the depth of field model to generate a seventh GDS file.
11. A method for manufacturing an optical mask, wherein the mask pattern on the optical mask is corrected by the method for trimming a pattern according to any one of claims 1 to 10.
12. A method for manufacturing a semiconductor device, wherein the method for trimming a pattern according to any one of claims 1 to 10 is used to correct a pattern of an optical mask during a manufacturing process of the semiconductor device.
13. A server, characterized by: comprising a memory and a processor; the memory stores a computer program; the computer program, when invoked by the processor, performs a method of trimming graphics as claimed in any one of claims 1 to 10.
14. A medium, in which a computer program is stored; the computer program, when invoked by a processor, performs a method of trimming a graphic as claimed in any one of claims 1 to 10.
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| CN102566328A (en) * | 2010-12-08 | 2012-07-11 | 无锡华润上华科技有限公司 | Method for improving edge development effect of wafer |
| CN103744271A (en) * | 2014-01-28 | 2014-04-23 | 苏州苏大维格光电科技股份有限公司 | Laser direct-writing system and photolithography method |
| CN105223771A (en) * | 2015-10-14 | 2016-01-06 | 上海华力微电子有限公司 | A kind of optimization method of optical proximity effect correction model |
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| CN102566328A (en) * | 2010-12-08 | 2012-07-11 | 无锡华润上华科技有限公司 | Method for improving edge development effect of wafer |
| CN103744271A (en) * | 2014-01-28 | 2014-04-23 | 苏州苏大维格光电科技股份有限公司 | Laser direct-writing system and photolithography method |
| CN105223771A (en) * | 2015-10-14 | 2016-01-06 | 上海华力微电子有限公司 | A kind of optimization method of optical proximity effect correction model |
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