JP2006235080A - Method for making mask pattern, method for making layout, method for manufacturing photomask, photomask, and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent pattern collapse of a line end portion or a defect pattern as a whole and to improve the process margin in lithography and the manufacturing yield of a device. <P>SOLUTION: The method for making a mask pattern comprises: recognizing a dummy pattern 51 which does not effect on device operation among design data of a semiconductor device corresponding to a pattern to be formed in a mask, extracting an end portion of the line or space constituting the recognized dummy pattern 51; and newly arranging a common dummy pattern 52 to connect the extracted end portion and a dummy pattern 51 adjacent to the end portion. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a mask pattern creation method for creating a mask pattern from design data of a semiconductor device, a photomask manufacturing method and a photomask using the mask pattern creation method, and a semiconductor device using the photomask. It relates to a manufacturing method. The present invention also relates to a layout creation method for correcting design data.

  Recent progress in semiconductor manufacturing technology is very remarkable, and semiconductor devices with a minimum processing dimension of 0.09 μm are mass-produced. Such miniaturization is realized by dramatic progress in fine pattern formation techniques such as a mask process technique, an optical lithography technique, and an etching technique.

  In an era when the pattern size is sufficiently large, a mask pattern that is faithful to the design pattern is created, the mask pattern is transferred onto the wafer by the projection optical system, and the underlying pattern is etched onto the wafer. I was able to form. However, as pattern miniaturization progresses, it has become difficult to faithfully form a pattern in each process, and a problem has arisen that the final finished dimension does not match the design pattern. In order to solve these problems, taking into account conversion differences in each process, means for creating a mask pattern different from the design pattern so that the final finished dimension becomes equal to the design pattern dimension (hereinafter referred to as mask data processing). Say) has become very important.

  For mask data processing, figure calculation processing, MDP (Mask Data Processing) processing for changing a mask pattern using a design rule checker (DRC), etc., and further, optical proximity effect (Optical Proximity Effect: OPE) correction There is an OPC (Optical Proximity Correction) process, etc., and by performing these processes, the mask pattern is appropriately corrected so that the final finished dimension becomes desired.

In recent years, with the miniaturization of device patterns, k1 values (k1 = W / (NA / λ) in the lithography process, W: design pattern dimensions, λ: exposure wavelength of exposure apparatus, and NA: exposure apparatus are used. The numerical aperture (lens) of the lens is further reduced, and as a result, the OPE tends to increase further, so that the load of the OPC processing becomes very large. In order to achieve high accuracy of OPC processing, a model-based OPC method that is equipped with a light intensity simulator capable of accurately predicting OPE and can calculate an appropriate correction value for each mask pattern has become mainstream (for example, (See Patent Documents 1 and 2).
Japanese Patent Laid-Open No. 2001-13668 JP 2003-17390 A

  However, even in the current model-based OPC, the correction cannot be said to be complete, and the deviation from the design pattern of the shape at the line end increases as the miniaturization progresses. For this reason, when a resist pattern is formed on a wafer with an exposure apparatus, the possibility that the line end of the pattern will collapse or become defective is increasing.

  The present invention has been made in view of the above circumstances, and the object of the present invention is to prevent the resist pattern from collapsing at the end of the line or the pattern itself from being defective, and improve the lithography process margin. Another object of the present invention is to provide a mask pattern forming method that can contribute to an improvement in device manufacturing yield.

  Another object of the present invention is to provide a photomask manufacturing method and photomask using this method, and further a semiconductor device manufacturing method. Another object of the present invention is to provide a layout creation method for correcting design data.

  In order to solve the above problems, the present invention adopts the following configuration.

  That is, according to one aspect of the present invention, in the method for creating a mask pattern, a step of recognizing a dummy pattern that does not affect device operation from design data of a semiconductor device corresponding to a pattern to be formed on the mask; A step of extracting an end portion of a line or space forming the dummy pattern, and a step of newly arranging a shared dummy pattern for connecting the extracted end portion and a dummy pattern adjacent to the end portion. , Including.

  According to another aspect of the present invention, in the method for creating a mask pattern, a step of extracting an end portion of a line or space forming a device pattern from design data of a semiconductor device corresponding to a pattern to be formed on a mask; , A step of measuring a relationship between a distance S between the extracted end portion and a pattern facing the end portion and a resist finish dimension of the line end portion by lithography, the distance S, and using the resist as a mask The step of measuring the relationship between the etching dimension conversion difference at the line end due to the adhesion of the etching side wall deposit, and the final dimension of the line end considering the etching dimension conversion difference within the resist finish dimension is within a predetermined dimension. The step of determining the value of the distance S as described above.

  According to still another aspect of the present invention, a photomask includes a semiconductor device pattern and a line / space dummy pattern on a mask substrate, and an end of the line or space forming the dummy pattern is shared. It is characterized by being connected to an adjacent dummy pattern by a pattern.

  According to still another aspect of the present invention, in a layout creation method for correcting design data, a step of recognizing a dummy pattern that does not affect device operation from the design data, and the recognized dummy pattern Extracting an end of a line or space that forms a line, a step of newly arranging a shared dummy pattern for connecting the extracted end and a dummy pattern adjacent to the end, and the shared dummy And a step of registering a layout in which a pattern is arranged as new design data.

  According to still another aspect of the present invention, in a layout creation method for modifying design data, a step of extracting an end of a line or space forming a device pattern from the design data, and the extracted end A step of measuring a relationship between a distance S between a portion and a pattern facing the end and a resist finished dimension of a line end by lithography, and adhesion of a sidewall deposit in etching using the distance S and a resist as a mask The step of measuring the relationship between the etching dimension conversion difference at the line end due to the step S and the distance S so that the final dimension of the line end considering the etching dimension conversion difference is within a predetermined dimension in the resist finished dimension. A process of determining a value, a process of arranging a pattern at the position of the distance S, and a layout in which the pattern is arranged at the position of the distance S Characterized in that it comprises a step of registering as a Do design data.

  According to the present invention, the end of the line or space of the dummy pattern is connected to the adjacent dummy pattern, or the distance S between the end of the line or space of the semiconductor device pattern and the pattern opposing the pattern is optimally set. It is possible to prevent the line end pattern from collapsing or the pattern itself from being defective. As a result, it is possible to contribute to the improvement of the process margin of lithography and the improvement of device manufacturing yield.

  The details of the present invention will be described below with reference to the illustrated embodiments.

(First embodiment)
FIG. 1A is a diagram showing an example of a dummy pattern arrangement method previously proposed by the present applicant (Japanese Patent Application No. 2004-360109). The L / S-shaped dummy pattern 12 surrounded by a dotted line in the figure is effective for improving the optical contrast of the main pattern (device pattern) 11 and does not perform OPC processing on a relatively large convex pattern. Thus, by performing the OPC process only on the fine pattern, the EB exposure time and the MDP processing time can be reduced.

  FIG. 1B shows an enlarged view of a part of the simulation result obtained by exposing the mask created by the above method. In the figure, 13 is a main pattern after exposure, and 14 is a dummy pattern after exposure. From this result, it is observed that the isolated dummy pattern 14 surrounded by a dotted line becomes thin. Furthermore, the result (SEM image) actually exposed on the substrate is shown as a micrograph in FIG. The part surrounded by the dotted line is a part corresponding to the dotted line part of FIG. 1B, and it can be seen that a part of the resist collapse occurs in these parts.

  It is known that the fine patterns arranged in this way are thin due to the influence of focus fluctuation during exposure or the influence of lens aberration of the exposure apparatus. Further, in a pattern portion having a small contact area with the base film, such as a line tip, “peeling” from the base film may occur before the resist disappears due to dimensional thinning.

  That is, in the dummy pattern arrangement method shown in FIG. 1, it is possible to improve the optical contrast of the main pattern, but it is impossible to deny the possibility of resist collapse at the leading edge of the dummy pattern. Dust generated by such resist collapse adheres to the main pattern, and there is a risk of causing an open or short, which causes yield deterioration. Therefore, it is required to have a dummy pattern shape that does not cause resist collapse without reducing optical contrast.

Here, the pattern refers to a line or space portion having an edge having a length of W or less and having a shape in which edges having a length of W or more are connected in the same direction from both vertices of the edge. A part refers to the vicinity of both vertices of an edge of length W. In particular, the dimension of W for which the present embodiment is effective is that when the exposure wavelength λ and the numerical aperture of the exposure apparatus are NA,
W / (λ / NA) ≦ 0.32 (1)
Is satisfied.

  The feature of this embodiment is to prevent resist collapse at the tip of the dummy pattern by devising the arrangement of the dummy pattern. FIG. 3A shows an example of the dummy pattern placement method according to the present embodiment, and FIG. 3B shows an enlarged view of a part of the simulation result obtained by performing exposure on the mask created. In FIG. 3, 31 is a device pattern, 32 is a dummy pattern, 33 is a device pattern after exposure, and 34 is a dummy pattern after exposure.

  In the present embodiment, a design layout for preventing resist collapse without reducing optical contrast as described above is shown. That is, as shown in the flowchart of FIG. 4, first, a dummy pattern that does not affect the device operation is recognized from the design data of the semiconductor device corresponding to the pattern to be formed on the mask (step S1). Next, the end of the line where the resist collapse is likely to occur is extracted from the dummy pattern (step S2). Then, the extracted end portion is shared with a part of another adjacent dummy pattern. That is, by newly providing a shared dummy pattern between the extracted end portion and the adjacent dummy pattern, the end portion is connected to the adjacent dummy pattern (step S3). Thereby, the end of the dummy pattern is erased (step S4).

  Such a process makes it possible to create a layout that prevents the occurrence of resist collapse. At this time, if the shared portion between the line end portion of the dummy pattern and the other dummy pattern becomes significantly large, the improvement of the optical contrast with respect to the main pattern (device pattern) is hindered. Therefore, it is desirable to form the shared portion with a minimum size that can avoid resist collapse at the end of the line.

  In particular, when the line width W of the main pattern satisfies the formula (1), it is necessary to increase the pattern resolution by setting the illumination shape of the exposure apparatus to a special shape. Specifically, it may have a special illumination shape called second illumination (FIG. 13A) or fourth illumination (FIG. 13B). By applying such an illumination shape, a range (referred to as an optical distance) that affects the dimensions of the main pattern increases. When the expression (1) is satisfied, the optical distance is 1 μm or more, and the shape of the dummy pattern that is 1 μm or more away from the main pattern affects the dimensions of the main pattern. In such a case, it is important to determine the size of the shared pattern so as to minimize the influence on the main pattern due to the addition of the shared dummy pattern at the end of the line. In addition, if the dummy patterns are arranged in a regular line and space pattern, it is more effective to improve the contrast of the main pattern.

  As shown in FIG. 5A, the size of the shared dummy pattern 52 is set to be 0.5 times or more and 2 times or less the line width (A) of the dummy pattern 51. Thereby, the improvement of the optical contrast with respect to a main pattern can be maintained. In the present embodiment, the size of the connection region with the adjacent pattern is 0.5 to 2 times the line width (A) of the dummy pattern 51. However, the present invention is not limited to this. The optimum value of the connection region with the adjacent pattern may be obtained experimentally from the actual resist shape.

  Further, as shown in FIG. 5B, when the line end portions of the dummy pattern 51 are arranged in a line, by sharing each line tip portion with a minimum size, It is possible to avoid resist collapse by minimizing the influence on the optical contrast with respect to the main pattern existing in the portion.

  As described above, according to the present embodiment, the dummy pattern is recognized from the design data, the line end portion that forms the dummy pattern is extracted, and the extracted end portion is connected to the adjacent dummy pattern. It is possible to prevent the pattern collapse of the part or the pattern itself from being a defect. Accordingly, it is possible to improve the lithography process margin and the device manufacturing yield.

(Second Embodiment)
FIG. 6 shows the resist finished shape on the wafer after lithography at the front end of the line, in which 61 is a device pattern after exposure, and 62 is a dummy pattern after exposure. The solid line in FIG. 6 is the mask pattern planar shape after OPC, and the dotted line is the design pattern. That is, the resist finished planar shape on the wafer calculated from the mask pattern after OPC is shown.

  FIG. 6A shows a case where another pattern exists at a position about 0.8 μm away from the line end, and FIG. 6B shows a case where another pattern exists at a position about 0.4 μm away from the line end. is there. The other pattern facing the line end is not necessarily a dummy pattern, and may be a device pattern.

  6A and 6B show that the shape of the line tip portion is different. In (a), the contact area between the tip and the base is sufficiently secured, but in (b), the tip is sharp and the contact area with the base is not sufficiently secured. As a result, in (b), there is a high possibility of resist collapse at the end of the line, and (a) is more desirable from the viewpoint of lithography.

  On the other hand, FIG. 7 shows a finished shape after the resist base is etched using the resist shape of FIG. 6, in which 71 is a device pattern after etching, and 72 is a dummy pattern after etching. Similarly to FIG. 6, the mask pattern planar shape after OPC is indicated by a dotted line, and the design pattern is indicated by a solid line.

  In FIG. 7A, since the distance between the line end of the device pattern 71 and the dummy pattern 72 facing the line end is large, the area to be etched increases, and the reaction product generated at that time is generated at the line end. It becomes easy to adhere as a side wall deposit. For this reason, there is a possibility that the end of the line comes into contact with the wafer and is electrically short-circuited. Further, in FIG. 7B, the distance between the line end portion and another pattern is short, the area to be etched is smaller than that in FIG. 7A, and the side wall deposits of the reaction product can be reduced. That is, from the viewpoint of etching, (b) is preferable because the resist shape can be faithfully reproduced.

  In this embodiment, from these viewpoints, the amount of side wall deposits attached to the line end after etching is estimated according to the distance from the line end to another pattern, and as a result, the resist dimensions at the line end, We estimated how much the amount of shortening (retraction amount) at the end of the line would change. The flowchart at this time is shown in FIG.

  First, the end of the line that forms the device pattern is extracted from the design data (step S1). Next, the relationship between the distance S between the extracted end portion and the dummy pattern opposite to the end portion, and the etching dimensional conversion difference at the line end portion due to the adhesion of the sidewall deposit in the etching using the resist as a mask is measured (step) S2). Subsequently, the relationship between the resist finished dimension at the line end by lithography and the distance S is measured (step S3). Next, the value of the distance S is determined so that the final dimension of the line end portion considering the etching dimension conversion difference in the resist finished dimension is within a predetermined dimension (step S4). Here, the resist dimension at the end of the line refers to the dimension at the location shown in FIG.

  FIG. 9A shows the distance S from the front end of the line to the opposing pattern on the horizontal axis, and the dimensional change amount (etching conversion difference: after etching) on the vertical axis due to the adhesion of sidewall deposits generated by etching. The difference between the size of the resist and the resist size). FIG. 9B shows the distance S from the line tip portion to the opposing pattern on the horizontal axis, and the dimensional change amount of the line tip portion due to adhesion of the sidewall deposit generated by etching on the vertical axis. It can be seen that as the distance S increases, the dimensional change amount at the end of the line and the dimensional change amount at the end of the line due to etching both increase in the positive direction.

  Furthermore, a lithography simulation was performed to estimate the distance S, the resist dimension at the line end, and the amount of shortening at the line end. FIG. 10A shows the resist dimensions at the line end, and FIG. 10B shows the amount of shortening at the line tip. This graph is a result under a specific exposure condition, and varies depending on the exposure wavelength of the exposure apparatus, the lens numerical aperture, the illumination shape, the pattern line width, the OPC condition (the length of jog), and the like.

  From FIG. 9 and FIG. 10, the finished dimensions after the final processing considering the resist dimensions and the etching conversion difference are shown in FIG. The final finished dimensions at the end of the line are shown in FIG. 11 (a) because the resist dimensions and the processing conversion difference tend to become thicker as S increases from FIGS. 9 (a) and 10 (a). As shown. At this time, it was estimated that S when the final finished dimension of the line end becomes a desired dimension was 0.2 μm.

  On the other hand, it can be seen from FIG. 10B that the amount of shortening at the tip of the line increases as S increases at the resist stage. On the contrary, FIG. 9B shows that the amount of shortening tends to be smaller due to etching, and the amount of shortening reduction due to etching is smaller. This is because the inclination of the vertical axis with respect to S is larger in FIG. 9B than in FIG. As a result, the shortening amount after the final processing is as shown in FIG. 11B, and it can be seen that the shortening amount becomes 0 when S = 0.8 μm.

  In such a case, it is necessary to determine the value of S from the allowable shortening amount of this pattern and the allowable dimension of the line end. Whether the amount of shortening is acceptable or not depends on the dimensional relationship with another layer different from this layer.

  For example, where the contact hole is arranged from the tip of the line, or if the pattern is a gate, there is a possibility that the pattern will run on the diffusion layer due to shortening, etc., and determines the allowable amount of shortening. It becomes a factor. On the other hand, the allowable dimension of the line end can be resolved between the line ends with a sufficient margin (processing process margin such as lithography and etching), or can be embedded in the space between the line end patterns. Whether or not there is a factor that determines the allowable dimension of the line end.

  From these points of view, it is common to determine the value of S between S = 0.2 μm (conditions where the line end pattern dimension is desired) and S = 0.8 μm (conditions where the shortening amount is 0). is there. If it is determined that there is no S satisfying the specifications during this period, it is necessary to review the process conditions including the exposure conditions, the OPC conditions, and the design rules and design pattern layout. . However, since this is a very large amount of work, even if it is judged that the specifications have not been met, by using these patterns as routine dimensional control points in the factory, the amount of shortening and the line end dimension allowance are allowed. It is also possible to tune the process to achieve capacity.

  Calculate the distance S that allows the line end dimensions and the amount of shortening by the above method, place another pattern at that position, and if necessary, manage the dimensions at the factory, and further process It was confirmed that by adjusting the conditions, layout, design rules, and OPC conditions, the shape of the line end can be stably formed on the wafer.

  In this embodiment, in order to determine the distance S between the line end portion of the pattern group and the pattern facing the line end portion, the resist dimension (resist width) and the shortening amount in the lithography process, and the etching conversion difference are used. In addition, it may be determined by adding device characteristics, specifically, electrical characteristics and timing analysis.

  As described above, according to the present embodiment, the end of the line that forms the device pattern is extracted from the design data, and the distance S between the extracted end and the opposing pattern is optimally set. It is possible to prevent the pattern collapse or the pattern itself from being a defect. Accordingly, it is possible to improve the lithography process margin and the device manufacturing yield.

(Modification)
The present invention is not limited to the above-described embodiments. In the embodiment, the end of the line forming the dummy pattern or the device pattern is extracted. Instead, the end of the space is extracted, and based on the end of the space, the arrangement of the shared pattern, the resist dimension, and the etching dimension conversion are performed. You may make it measure a difference.

  In the embodiment, a method for creating a mask pattern has been described. However, a photomask can be manufactured by forming a mask pattern on a mask substrate using the method. Furthermore, a semiconductor device can be manufactured by forming a pattern of a semiconductor layer on a resist on a semiconductor substrate using this photomask.

  In addition, various modifications can be made without departing from the scope of the present invention.

The figure which shows the reference example of the dummy pattern arrangement | positioning method. The figure which shows the result of having actually exposed on the board | substrate by the method of FIG. The figure which shows an example of the dummy pattern arrangement | positioning method in 1st Embodiment. 6 is a flowchart showing a procedure for creating correction data from design data according to the first embodiment. The figure which shows the mode of sharing the front-end | tip part of a dummy pattern. The figure which shows the finished shape on the wafer after the lithography of the line end front-end | tip part in 2nd Embodiment. The figure which shows the finished shape after etching the resist shape of FIG. 9 is a flowchart illustrating a procedure for creating correction data from design data according to the second embodiment. The figure which shows the relationship between the distance S from the line front-end | tip part to the pattern which opposes, and the etching conversion difference of a line edge part and front-end | tip part. The figure which shows the relationship between the distance S from the line front-end | tip part to the pattern which opposes, the resist dimension of the line edge part and front-end | tip part, and the amount of shortening. The figure which shows the relationship between the distance S from the line front-end | tip part to the pattern which opposes, the resist dimension of the line edge part and front-end | tip part, and the amount of shortening. The figure for defining the resist dimension of a line edge part. The top view which shows the example of a special illumination shape.

Explanation of symbols

11, 31 ... Device pattern 12, 32 ... Dummy pattern 13, 33 ... Device pattern (after exposure)
14, 34 ... dummy pattern (after exposure)
51 ... Dummy pattern 52 ... Shared dummy pattern 61 ... Device pattern (after exposure)
62 ... Dummy pattern (after exposure)
71 ... Device pattern (after etching)
72 ... dummy pattern (after etching)

Claims (7)

Recognizing a dummy pattern that does not affect device operation from the design data of the semiconductor device corresponding to the pattern to be formed on the mask;
Extracting an end of a line or space forming the recognized dummy pattern;
A step of newly arranging a shared dummy pattern for connecting the extracted end portion and a dummy pattern adjacent to the end portion;
A mask pattern creating method comprising: Extracting an end of a line or space forming a device pattern from design data of a semiconductor device corresponding to a pattern to be formed on a mask;
Measuring a relationship between a distance S between the extracted end portion and a pattern facing the end portion, and a resist finish size of a line end portion by lithography;
Measuring the relationship between the distance S and the etching dimension conversion difference at the end of the line due to adhesion of sidewall deposits of etching using a resist as a mask;
Determining the value of the distance S so that the final dimension of the line end considering the etching dimension conversion difference in the resist finish dimension is within a predetermined dimension;
Placing a pattern at the position of the distance S;
A mask pattern creating method comprising:   A method for manufacturing a photomask, comprising: forming a mask pattern on a mask substrate using the mask pattern creating method according to claim 1.   A photomask comprising a circuit pattern and a dummy pattern of a semiconductor device on a mask substrate, and an end of a line or space forming the dummy pattern is connected to an adjacent dummy pattern by a shared pattern.   A method for manufacturing a semiconductor device, comprising: forming a pattern of a semiconductor device on a resist on a semiconductor substrate using the photomask according to claim 4. A process of recognizing dummy patterns from design data that do not affect device operation;
Extracting an end of a line or space forming the recognized dummy pattern;
A step of newly arranging a shared dummy pattern for connecting the extracted end portion and a dummy pattern adjacent to the end portion;
Registering the layout in which the shared dummy pattern is arranged as new design data;
The layout creation method characterized by including. Extracting the end of the line or space forming the device pattern from the design data; and
Measuring a relationship between a distance S between the extracted end portion and a pattern facing the end portion, and a resist finish size of a line end portion by lithography;
Measuring the relationship between the distance S and the etching dimension conversion difference at the end of the line due to adhesion of sidewall deposits of etching using a resist as a mask;
Determining the value of the distance S so that the final dimension of the line end considering the etching dimension conversion difference in the resist finish dimension is within a predetermined dimension;
Placing a pattern at a position of distance S;
Registering a layout in which a pattern is arranged at the position of the distance S as new design data;
The layout creation method characterized by including.

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