CN104516192A - Method of establishing OPC model and inspection method of arrangement pattern - Google Patents
Method of establishing OPC model and inspection method of arrangement pattern Download PDFInfo
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- CN104516192A CN104516192A CN201310463702.9A CN201310463702A CN104516192A CN 104516192 A CN104516192 A CN 104516192A CN 201310463702 A CN201310463702 A CN 201310463702A CN 104516192 A CN104516192 A CN 104516192A
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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Abstract
A method of establishing OPC model and an inspection method of arrangement patterns are disclosed. Through the method of establishing the OPC model, a final OPC model is obtained with consideration of a permitted minimum thickness of a photoresist layer in subsequent etching of wafers. When the final OPC model is employed for simulation, a zone causing influence to accuracy of a pattern finally formed on the wafers due to thickness loss of the photoresist layer can be effectively found out, which is beneficial to subsequent modification of a photomask pattern, so that a pattern finally formed by etching the wafer with the photoresist layer as the photomask is high in accuracy when the modified photomask pattern is employed in exposure of the photoresist layer.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to and a kind ofly set up the method for OPC model, the inspection method of layout graph.
Background technology
In semiconductor fabrication, along with constantly reducing of design size, the diffraction effect of light becomes more and more obvious, its result is exactly finally degenerate to the optical image that design configuration produces, the final actual graphical formed through photoetching on silicon chip becomes different with design configuration, this phenomenon is called as OPE(OpticalProximity Effect, optical proximity effect).
In order to revise OPE phenomenon, just create OPC(Optical Proximity Correction, optical proximity effect correction).The core concept of OPC is exactly set up OPC model based on the consideration of offsetting OPE phenomenon, according to OPC model design photomask figure, although the corresponding photomask pattern of the litho pattern like this after photoetching there occurs OPC phenomenon, but due to according to the counteracting considered during OPC model design photomask figure this phenomenon, therefore, the litho pattern after photoetching is close to the actual targeted graphical of wishing to obtain of user.
But, due in the manufacture process of integrated circuit, after formation litho pattern, also need described litho pattern to be transferred on wafer to form final graphics.Litho pattern after photoetching wishes close to user is actual the targeted graphical that obtains, and does not mean that and be follow-uply formed in figure on wafer just close to above-mentioned targeted graphical.Compared to targeted graphical, the degree of accuracy that prior art is formed in the final graphics that wafer is formed still has much room for improvement.
Summary of the invention
The problem that technical scheme of the present invention solves is to provide a kind ofly sets up the method for OPC model, the inspection method of layout graph, to improve the degree of accuracy of the follow-up final graphics be formed on wafer.
For solving the problem, the invention provides a kind of method setting up OPC model, comprising: provide targeted graphical, etching system and surface to be formed with the wafer of photoresist layer; The photomask pattern obtained according to described targeted graphical and etching system, the optical mask plate with above-mentioned photomask pattern and original OPC model are provided; Utilize described optical mask plate and etching system exposed wafer, photoresist layer forms litho pattern, and obtain the size being positioned at litho pattern bottom photoresist layer, using the described size being positioned at litho pattern bottom photoresist layer as with reference to size; Out of focus starting point in original OPC model is arranged on the bottom of photoresist layer, according to described reference dimension, described original OPC model is calibrated, until the size of litho pattern obtained by the OPC model after this calibration bottom the photoresist layer of simulating equals described reference dimension, using the OPC model after this calibration as mid-module; The minimum thickness of the photoresist layer allowed when obtaining aforementioned exposed wafer, is arranged on the minimum thickness place of the photoresist layer of permission, obtains final OPC model by the out of focus starting point of described mid-module.
Optionally, in original OPC model, simulate the figure obtained consistent with targeted graphical for described photomask pattern.
Optionally, the size of the litho pattern bottom described photoresist layer is obtained by electron microscope measurement.
Optionally, the step that described original OPC model is calibrated is comprised: the calibration of exposure focal plane, the depth calibration of mimic diagram, light acid diffusion length calibration and prism polarization calibration.
Accordingly, present invention also offers a kind of inspection method of layout graph, comprising: provide any one photomask pattern described above and final OPC model, described photomask pattern is made up of multiple minute pattern; Utilize described final OPC model to simulate described photomask pattern, obtain test pattern, the spirte in described test pattern and the minute pattern one_to_one corresponding on photomask pattern; Spirte in described test pattern is detected one by one, when spirte characteristic of correspondence is of a size of 0 in test pattern, then minute pattern corresponding with this spirte in photomask pattern is marked.
Optionally, comprising: revise the minute pattern be labeled in described photomask pattern, until utilize final OPC model to simulate amended photomask pattern, in the test pattern obtained, all spirte characteristic of correspondence sizes are greater than 0.
Compared with prior art, technical scheme of the present invention has the following advantages:
In acquisition after the photomask pattern of preliminary calibration, exposed wafer forms litho pattern on photoresist layer, obtains the size of the litho pattern be positioned at bottom photoresist layer; Then the out of focus starting point in original OPC model is arranged on the bottom of photoresist layer, using the size of the litho pattern bottom photoresist layer as reference size, revise described original OPC model, until the size of litho pattern that this amended OPC model obtains bottom the photoresist layer of simulating equals described reference dimension, obtain mid-module; Again the out of focus starting point of mid-module is arranged on the minimum thickness place of the photoresist layer of permission, obtains final OPC model.Owing to setting up the minimum thickness of the photoresist layer allowed when final OPC model considers subsequent etching wafer, when the OPC model utilizing this final is simulated, effectively can find the region because the degree of accuracy of photoresist layer thickness loss to the final graphics formed on wafer impacts, be beneficial to prevent from source, improve the degree of accuracy of the follow-up final graphics be formed on wafer.
Further, final OPC model is utilized to simulate described photomask pattern, when the characteristic dimension of the spirte in test pattern is 0, minute pattern corresponding with this spirte on photomask pattern is marked, and revised, until utilize final OPC model to simulate amended photomask pattern, in the test pattern obtained, all spirte characteristic of correspondence sizes are greater than 0.Utilize this amended photomask pattern exposed photoresist layer, the degree of accuracy of the final graphics formed for mask etching wafer with described photoresist layer is high.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet setting up the method for OPC model of the embodiment of the present invention;
Fig. 2 is the structural representation of the exposure system of the embodiment of the present invention;
Fig. 3 is the schematic flow sheet of the inspection method of the layout graph of the embodiment of the present invention.
Embodiment
As described in background, even if the litho pattern after photoetching is close to the actual targeted graphical of wishing to obtain of user, but the degree of accuracy of the follow-up final graphics formed on wafer still has much room for improvement.
Can learn by analysis, above-mentioned phenomenon major reason is caused to be: to be formed in the process of litho pattern at exposure imaging, because litho pattern is at the density of zones of different and size difference, the degree of developer solution corrosion photoresist thickness also can be distinguished to some extent, especially the region that litho pattern distribution is comparatively intensive, it is more that the thickness of photoresist layer is corroded, thickness loss serious (Top Loss).The region that the serious photoresist layer of described thickness loss is corresponding, even if litho pattern is identical with targeted graphical, but the thickness due to the photoresist layer in this region can not meet the demand of subsequent etching processes, the follow-up thickness etching the final graphics of formation on wafer can not be met consumers' demand, thus the problem that the degree of accuracy causing the final graphics formed on wafer is lower.
The data that cannot get the electron microscope (CDSEM) of the thickness information of photoresist layer because existing OPC system is two-dimensional size information based on the litho pattern that can only get are set up, and therefore cannot find out the defect of the figure that above-mentioned photoresist layer thickness loss causes.
And if want to set up a tight OPC model can measuring the three-dimensional dimension of litho pattern, need through complicated mathematics and physical manipulations, its cost of development is high, and also there is the problem of the length consuming time caused because calculated amount is excessive in use, be unfavorable for the efficiency improving actual process production.
Comprehensive above various consideration, The embodiment provides a kind of method setting up OPC model, provides targeted graphical, etching system and surface to be formed with the wafer of photoresist layer; The photomask pattern obtained according to described targeted graphical and etching system, the optical mask plate with above-mentioned photomask pattern and original OPC model are provided; Utilize described optical mask plate and etching system exposed wafer, photoresist layer forms litho pattern, and obtain the size being positioned at litho pattern bottom photoresist layer, using the described size being positioned at litho pattern bottom photoresist layer as with reference to size; Out of focus starting point in original OPC model is arranged on the bottom of photoresist layer, according to the described original OPC model of described reference dimension amendment, until the size of litho pattern obtained by this amended OPC model bottom the photoresist layer of simulating equals described reference dimension, using this amended OPC model as mid-module; The minimum thickness of the photoresist layer allowed when obtaining aforementioned exposed wafer, is arranged on the minimum thickness place of the photoresist layer of permission, obtains final OPC model by the out of focus starting point of described mid-module.This final OPC model can be used for detecting the defect of the figure that photoresist layer thickness loss causes.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Please refer to Fig. 1, in embodiments of the invention, the described method setting up OPC model, comprising:
Step S101, provides targeted graphical, etching system and surface to be formed with the wafer of photoresist layer;
Step S102, provides the photomask pattern obtained according to described targeted graphical and etching system, the optical mask plate with above-mentioned photomask pattern and original OPC model;
Step S103, utilize described optical mask plate and etching system exposed wafer, photoresist layer forms litho pattern, and obtains the size being positioned at litho pattern bottom photoresist layer, using the described size being positioned at litho pattern bottom photoresist layer as with reference to size;
Step S104, out of focus starting point in original OPC model is arranged on the bottom of photoresist layer, according to described reference dimension, described original OPC model is calibrated, until the size of litho pattern obtained by the OPC model after this calibration bottom the photoresist layer of simulating equals described reference dimension, using the OPC model after this calibration as mid-module;
Step S105, the minimum thickness of the photoresist layer allowed when obtaining etching wafer, is arranged on the minimum thickness place of the photoresist layer of permission, obtains final OPC model by the out of focus starting point of described mid-module.
Concrete, please refer to Fig. 2, described targeted graphical is provided by user, for providing guidance for manufacturing, is the figure that actual needs is formed; Described etching system 202 is the equipment for carrying out photolithographic exposure, and its inside comprises multiple optical element, can make light that the changes such as multiple reflections, refraction, focusing occur therein; The wafer 204 that described surface is formed with photoresist layer 203 is the object as follow-up photoetching, and photoresist layer 203 forms litho pattern, follow-uply transfers on wafer by litho pattern, for the manufacture of integrated circuit by the mode of etching again.
Described photomask pattern is the figure obtained according to described targeted graphical and etching system design.In embodiments of the invention, described photomask pattern is carried out the figure that preliminary calibration crosses, namely adopt the optical mask plate 201 with the making of this mask graph to carry out exposure imaging by the photoresist layer 203 on above-mentioned etching system 202 pairs of wafer 204 surfaces, the litho pattern obtained is identical with preceding aim figure; Described original OPC model is the model after preliminary calibration, and described photomask pattern checks through original OPC model mock survey and actual manufacture, repeatedly obtains after amendment.
In embodiments of the invention, obtain above-mentioned there is the optical mask plate 201 of photomask pattern after, utilize described optical mask plate 201 and etching system 202 exposed wafer 204, photoresist layer 203 form litho pattern.In an embodiment of the present invention, the light that light source 200 sends is after optical mask plate 201, enter optical system 202, and after there is the changes such as multiple reflections, refraction, focusing therein, finally penetrated by optical system 202, be irradiated to photoresist layer 203 surface being coated on wafer 204 surface, form actual litho pattern.
After photoresist layer 203 forms litho pattern, obtain the size of the litho pattern be positioned at bottom photoresist layer 203, for follow-up as reference modification of dimension OPC model.In embodiments of the invention, adopt electron microscope (CDSEM) to measure the litho pattern bottom photoresist layer 203, corresponding size can be obtained.
It should be noted that, in actual manufacturing process, described targeted graphical is made up of several little figures, therefore, the photomask pattern of design also has the minute pattern of several correspondences to form, and the litho pattern be formed in bottom photoresist layer 203 is also made up of multiple spirte.Therefore, in the embodiment of the present invention actual measurement be the size of multiple spirtes bottom photoresist layer 203 of litho pattern.
Due in actual light carving technology, convergence of rays Jiao through etching system injection forms focus to a bit, along with focus is different from the position relationship of photoresist layer, the light distribution be formed in photoresist layer is also not quite similar, and causes being formed in the litho pattern that in photoresist layer, different-thickness place is corresponding and also distinguishes to some extent.Ideal situation is: focus is positioned at the interior thickness place of photoresist layer, and the light distribution of light in photoresist layer is tending towards even, and now out of focus phenomenon does not occur light yet, and the litho pattern difference that in photoresist layer, different-thickness place is corresponding is less.
Learn by analysis, as long as light out of focus does not occur in the thickness of photoresist layer, the error of the litho pattern so formed still and between targeted graphical in allowed limits, can meet process requirements.And out of focus starting point (defocus start) being arranged on different positions in OPC model, the litho pattern that simulation obtains is not identical yet.In order to make the figure that obtains accurate, can process requirements be met, needing to ensure to locate out of focus phenomenon does not occur bottom photoresist layer.Therefore, in an embodiment of the present invention, the bottom that out of focus starting point in original OPC model is arranged on photoresist layer (is represent with this position as separatrix, there is not out of focus in this position and above local light, but the local light generation out of focus below this position), according to described reference dimension, described original OPC model is calibrated further, can calibrate the correlation parameter of the optical model in original OPC model or lithography model, such as expose the calibration of focal plane, the depth calibration of mimic diagram, light acid diffusion length is calibrated, and prism polarization calibration etc., until the size of litho pattern obtained by the OPC model after this calibration bottom the photoresist layer of simulating equals described reference dimension, using the OPC model after this calibration as mid-module.
The minimum thickness of the photoresist layer allowed during described etching wafer is follow-up when being transferred on wafer by litho pattern, and photoresist layer is just etched and don't undermines the thickness of bottom wafers.The minimum thickness of the photoresist layer of described permission is relevant to the size of each little figure in targeted graphical and the factor such as pattern density, etch process parameters.In an embodiment of the present invention, those skilled in the art determine at targeted graphical, etch process parameters is determined, know the minimum thickness of the photoresist layer how obtaining corresponding permission, do not repeat them here.
Learn afterwards by analysis; the degree of accuracy of the final graphics that wafer is formed is lower is because the thickness loss of photoresist layer is serious; its thickness after photoetching, before etching has been less than the minimum thickness of the photoresist layer of permission; when making subsequent etching wafer; also do not form the final graphics of predetermined thickness; the photoresist in the region that the thickness loss of these photoresist layers is serious has been consumed; expose crystal column surface; the effect protected without the need to the crystal column surface be etched cannot be served as in follow-up continuation etching, thus cause this region to form figure.
Based on above-mentioned analysis, in embodiments of the invention, after the minimum thickness of the photoresist layer allowed when getting aforementioned exposed wafer, the out of focus starting point of the aforementioned mid-module obtained being arranged on the minimum thickness place of the photoresist layer of permission, obtaining final OPC model.So, the final OPC model of later use is carried out simulation to photomask pattern and is obtained test pattern, by judging whether the characteristic dimension of the spirte in each region in test pattern is 0, can judge whether this region is formed with spirte, thus judge whether the thickness of the photoresist layer corresponding with this region satisfies the demands.
After above-mentioned steps completes, the foundation of the OPC model of the embodiment of the present invention completes, and utilizes this model then can be checked through because of the low problem of the degree of accuracy of serious the caused final graphics formed on wafer of the thickness loss of photoresist layer.
Particularly, please refer to Fig. 3, present invention also offers a kind of inspection method of layout graph, comprising:
Step S301, the photomask pattern final OPC model being provided and obtaining according to targeted graphical and etching system, described photomask pattern is made up of multiple minute pattern;
Step S302, utilizes described final OPC model to simulate described photomask pattern, obtains test pattern, the spirte in described test pattern and the minute pattern one_to_one corresponding on photomask pattern;
Step S303, detects one by one to the spirte in described test pattern, when in test pattern, spirte characteristic of correspondence is of a size of 0, is then marked by minute pattern corresponding with this spirte in photomask pattern;
Step S304, revise the minute pattern be labeled in described photomask pattern, until utilize final OPC model to simulate amended photomask pattern, in the test pattern obtained, all spirte characteristic of correspondence sizes are greater than 0, using this amended described photomask pattern as final design configuration.
Wherein, described final OPC model is the model set up according to said method; Described photomask pattern is the aforementioned figure having carried out preliminary calibration and crossed.In an embodiment of the present invention, described photomask pattern is made up of multiple minute pattern, the photomask with described photomask pattern is utilized to expose photoresist layer, the litho pattern obtained is consistent with targeted graphical, and the error between the litho pattern namely formed and targeted graphical is in the scope that user's technique allows.
As mentioned before, due to the minimum thickness place of photoresist layer allowed when out of focus starting point to be arranged on etching wafer by described final OPC model, can by the value of the characteristic dimension of test pattern obtained, judge the thickness of the photoresist layer after the actual exposure of each region, the thickness finding out photoresist layer is less than these regions of the minimum thickness of the photoresist layer of permission.
In an embodiment of the present invention, the spirte in described test pattern is detected one by one, when the characteristic dimension of spirte in test pattern is 0, then minute pattern corresponding with this spirte on photomask pattern is marked.Known by analysis above, this minute pattern can cause the thickness loss of photoresist layer in follow-up photoetching process serious, make the thickness of the photoresist layer in this region lower than the minimum thickness allowed, cause and follow-uply cannot form the final graphics met the demands on wafer, the degree of accuracy of the final graphics that wafer is formed has much room for improvement.
In an embodiment of the present invention, the minute pattern be labeled in photomask pattern can also be revised, then said method is adopted repeatedly to check, until utilize final OPC model to simulate amended photomask pattern, in the test pattern obtained, all spirte characteristic of correspondence sizes are greater than 0.When namely adopting this amended photomask pattern exposure to form litho pattern, the thickness loss of photoresist layer can not affect the degree of accuracy of the final graphics etching formation on wafer.
To sum up, in acquisition after the photomask pattern of preliminary calibration, exposed wafer forms litho pattern on photoresist layer, obtains the size of the litho pattern be positioned at bottom photoresist layer; Then the out of focus starting point in original OPC model is arranged on the bottom of photoresist layer, using the size of the litho pattern bottom photoresist layer as reference size, revise described original OPC model, until the size of litho pattern that this amended OPC model obtains bottom the photoresist layer of simulating equals described reference dimension, obtain mid-module; Again the out of focus starting point of mid-module is arranged on the minimum thickness place of the photoresist layer of permission, obtains final OPC model.Owing to setting up the minimum thickness of the photoresist layer allowed when final OPC model considers subsequent etching wafer, when the OPC model utilizing this final is simulated, effectively can find the region because the degree of accuracy of photoresist layer thickness loss to the final graphics formed on wafer impacts, be beneficial to prevent from source, improve the degree of accuracy of the follow-up final graphics be formed on wafer.
Further, final OPC model is utilized to simulate described photomask pattern, when the characteristic dimension of the spirte in test pattern is 0, minute pattern corresponding with this spirte on photomask pattern is marked, and revised, until utilize final OPC model to simulate amended photomask pattern, in the test pattern obtained, all spirte characteristic of correspondence sizes are greater than 0.Utilize this amended photomask pattern exposed photoresist layer, the degree of accuracy of the final graphics formed for mask etching wafer with described photoresist layer is high.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (6)
1. set up a method for OPC model, it is characterized in that, comprising:
Targeted graphical, etching system and surface is provided to be formed with the wafer of photoresist layer;
The photomask pattern obtained according to described targeted graphical and etching system, the optical mask plate with above-mentioned photomask pattern and original OPC model are provided;
Utilize described optical mask plate and etching system exposed wafer, photoresist layer forms litho pattern, and obtain the size being positioned at litho pattern bottom photoresist layer, using the described size being positioned at litho pattern bottom photoresist layer as with reference to size;
Out of focus starting point in original OPC model is arranged on the bottom of photoresist layer, according to described reference dimension, described original OPC model is calibrated, until the size of litho pattern obtained by the OPC model after this calibration bottom the photoresist layer of simulating equals described reference dimension, using the OPC model after this calibration as mid-module;
The minimum thickness of the photoresist layer allowed when obtaining etching wafer, is arranged on the minimum thickness place of the photoresist layer of permission, obtains final OPC model by the out of focus starting point of described mid-module.
2. set up the method for OPC model as claimed in claim 1, it is characterized in that, it is consistent with targeted graphical that described photomask pattern simulates the figure obtained in original OPC model.
3. set up the method for OPC model as claimed in claim 1, it is characterized in that, the size of the litho pattern bottom described photoresist layer is obtained by electron microscope measurement.
4. set up the method for OPC model as claimed in claim 1, it is characterized in that, the step that described original OPC model is calibrated is comprised: the calibration of exposure focal plane, the depth calibration of mimic diagram, light acid diffusion length calibration and prism polarization calibration.
5. an inspection method for layout graph, is characterized in that, comprising:
There is provided the photomask pattern according to any one of claim 1-4 and final OPC model, described photomask pattern is made up of multiple minute pattern;
Utilize described final OPC model to simulate described photomask pattern, obtain test pattern, the spirte in described test pattern and the minute pattern one_to_one corresponding in photomask pattern;
Spirte in described test pattern is detected one by one, when spirte characteristic of correspondence is of a size of 0 in test pattern, then minute pattern corresponding with this spirte on photomask pattern is marked.
6. the inspection method of layout graph as claimed in claim 5, it is characterized in that, comprise: revise the minute pattern be labeled in described photomask pattern, until utilize final OPC model to simulate amended photomask pattern, in the test pattern obtained, all spirte characteristic of correspondence sizes are greater than 0.
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| CN110361927A (en) * | 2018-04-11 | 2019-10-22 | 中芯国际集成电路制造(上海)有限公司 | Lithography model generation method and OPC modification method |
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| CN104516192B (en) | 2018-10-16 |
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