WO2014077671A1 - A method of generating spice-compatible isfet model - Google Patents

A method of generating spice-compatible isfet model Download PDF

Info

Publication number
WO2014077671A1
WO2014077671A1 PCT/MY2013/000192 MY2013000192W WO2014077671A1 WO 2014077671 A1 WO2014077671 A1 WO 2014077671A1 MY 2013000192 W MY2013000192 W MY 2013000192W WO 2014077671 A1 WO2014077671 A1 WO 2014077671A1
Authority
WO
WIPO (PCT)
Prior art keywords
isfet
model
spice
optimization
compatible
Prior art date
Application number
PCT/MY2013/000192
Other languages
French (fr)
Inventor
Ismail MUHAMAD AMRI
Mat Hussin MOHD ROFEI
Original Assignee
Mimos Berhad
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mimos Berhad filed Critical Mimos Berhad
Publication of WO2014077671A1 publication Critical patent/WO2014077671A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Definitions

  • the present invention relates to a method of generating user-friendly ISFET model for simulation of semiconductor integrated circuit. It is particularly suitable to accurately characterize the electrical and electrochemical behaviors of the ISFET device.
  • ISFET Insulation-to-semiconductor
  • This fact leads to the difficulties of modeling and integrating ISFET devices into complete circuit architecture for several critical purposes such as design optimization and yield prediction. Circuit level design integration and simulation are vital to meet the increasing demand of robust sensor products. Some researchers tend to use any available commercial model parameters from provided commercial datasheet or any research papers which is not extracted from the actual fabricated wafer, resulting to the wrong analysis and lengthen the product development cycle. The difficulty of developing this model is mainly due to the complicated integration between standard electrical and non-standard electrochemical characteristics of the ISFET device. There are some efforts done to characterize ISFET device in order to ensure that the ISFET device could be simulated and integrated with other silicon-based devices and produce highly value-added sensor products.
  • ISFET is one of the available devices in semiconductor industry. A part from its important role in the development of highly integrated sensor products, the device is actually suffers the lack of support in device modelling department. This drawback has leads to difficulties in integrating such device into the complete circuit architecture.
  • prior arts have been developed for ISFET model but they typically used either system level or hybrid model platforms which resulting to the complicated model extraction flow, as shown in Figure 1.
  • the present invention provides a method of generating SPICE-compatible ISFET model using built-in optimizer function, wherein the methods comprising: identifying ISFET device geometries for width, length and gate oxide thickness as inputs in initial ISFET modeling (100); and measuring electrical and electrochemical characteristics of the fabricated ISFET device (200); characterized in that transferring the electrical and electrochemical characteristics measurement data into SPICE netlist and correlating with simulation setup (300); and optimizing the ISFET model parameters using optimizer in SPICE simulator (400).
  • SPICE model based on the available sub-circuit model descriptions.
  • SPICE is the de- facto standard which has revolutionized the semiconductor industry and is easily ported to other non-SPICE circuit simulators such as Spectre and Eldo.
  • the constrain of integration between electrical and electrochemical characteristics is handled by extracting standard MOSFET model parameters for standard electrical part first follows by the sub-circuit modeling to take care on the electrochemical part. It serves as a generic description of the ISFET devices in different kind of supported commercial and educational simulators as it use SPICE-compatible format.
  • the present invention requires the electrical measurement from actual fabricated ISFET device. The measurement results are transferred into the circuit simulator netlist for the extraction of related model parameters. In the initial stage, the uses of default model parameters would not show good agreement between measured and simulated data.
  • Built-in optimizer function in SPICE circuit simulator is utilized in the present invention for the curve fitting between measured and simulated.
  • Figure 1 illustrates the flow chart of the prior art of the present invention.
  • Figure 2 illustrates the method of generating SPICE-compatible ISFET model of the present invention.
  • FIG. 13 illustrates details of ISFET measurement flow from electrical to electrochemical characteristics.
  • Figure 4 illustraterates the optimization process to ensure the good fitting between measured and simulated curves.
  • Figure 5 illustrates an example of optimization steps with SPICE model parameters and measurement and simulation setup.
  • the present invention relates to amethod of generating SPICE-compatible ISFET model using built-in optimizer function, wherein the methods comprising: identifying ISFET device geometries for width, length and gate oxide thickness as inputs in initial ISFET modeling (100); and measuring electrical and electrochemical characteristics of the fabricated ISFET device (200); characterized in that transferring the electrical and electrochemical characteristics measurement data into SPICE netlist and correlating with simulation setup (300); and optimizing the ISFET model parameters using optimizer in SPICE simulator (400).
  • a wafer with fabricated ISFET structures is required in the first stage of the extraction flow.
  • the geometrical parameters such as length (L), width (W) and gate oxide thickness (TOX) need to be identified first for the suitable selection of level in device modeling (100). Bigger ISFET structure could be modeled with SPICE model level 1 , 2 or 3 while smaller ISFET structure need to use SPICE model level 13 (i.e. BSIM1).
  • the next step is the actual device measurement using parameter analyzer (200).
  • the step of measuring electrical and electrochemical characteristics (200) further comprising: measuring I-V curves at reference, lower and upper pH values (201); and exporting the measurement data into text file with certain format to agree with simulation setup (203).
  • the electrical and electrochemical measurements are then transferred to the SPICE netlist (300) which contains the MOS model parameters and related sub-circuit description of the ISFET electrochemical component.
  • the step of transferring the electrical and electrochemical characteristics measurement data into SPICE netlist (300) further comprising: setting the optimization setup for number of iterations, calculation of error between measured and simulated data and optimization acceptance criteria (301 ); connecting and sweeping the ISFET terminals for I-V curves simulation (303); and determining the correct setup with respect to the measurement data (305).
  • the model parameters are extracted and optimized using built-in optimizer (400) available in the SPICE simulator to fit the measured and simulated curves.
  • the step of optimizing the ISFET model parameters (400) further comprising: setting the initial ISFET model with default model parameters (401); adding the initial ISFET model into the SPICE netlist in accordance with the obtained measurement data (403);
  • the step of setting the initial ISFET model further comprising (401): selecting BSIMI model with related ISFET sub-circuit model parameters (401a) and the typical model parameters comprising typical values for vfbO, phiO, kl, k2, etaO, x3e, muz, mus, uOO, ul , x3ul , x3ms, x2e, x2m, x2ms, x2u0, x2ul , n0, nbO, ndO, Nsil and Nnit.
  • the optimization process continues until the error between measured and simulated data are less than root-mean-square (RMS) error is less than 10%.
  • RMS root-mean-square
  • FIG. 3 The details of ISFET measurement flow from electrical to electrochemical characteristics are shown in Figure 3. Electrical characteristics are referring to the I-V curves measurements at typical or reference pH value while electrochemical characteristics are referring to the I-V curves measurement at pH smaller and bigger than the reference value.
  • Figure 4 illustrates the optimization process to ensure the good fitting between measured and simulated curves. The optimization process loops through all the optimization steps, so as to consider one optimization step at a time.
  • Figure 5 is a table illustrating an example of optimization steps with SPICE model parameters and measurement and simulation setup.
  • Figure 6 illustrates the example of SPICE simulation file for model extraction process.

Abstract

The present invention relates to a method to generate a compact SPICE model based on the available sub-circuit model descriptions. The method comprisingcomprising: identifying ISFET device geometries for width, length and gate oxide thickness as inputs in initial ISFET modeling (100); and measuring electrical and electrochemical characteristics of the fabricated ISFET device (200); characterized in that transferringthe electrical and electrochemical characteristics measurement data into SPICE netlist and correlating with simulation setup (300); and optimizing the ISFET model parameters using optimizer in SPICE simulator (400).

Description

Description
Title of Invention: A METHOD OF GENERATING SPICE- COMPATIBLE ISFET MODEL
[ 1 ] FIELD OF INVENTION
[2] The present invention relates to a method of generating user-friendly ISFET model for simulation of semiconductor integrated circuit. It is particularly suitable to accurately characterize the electrical and electrochemical behaviors of the ISFET device.
[3] BACKGROUND OF THE INVENTION
[4] There is no user-friendly extraction flow available for Ion-Sensitive Field Effect
Transistor (ISFET) model. This fact leads to the difficulties of modeling and integrating ISFET devices into complete circuit architecture for several critical purposes such as design optimization and yield prediction. Circuit level design integration and simulation are vital to meet the increasing demand of robust sensor products. Some researchers tend to use any available commercial model parameters from provided commercial datasheet or any research papers which is not extracted from the actual fabricated wafer, resulting to the wrong analysis and lengthen the product development cycle. The difficulty of developing this model is mainly due to the complicated integration between standard electrical and non-standard electrochemical characteristics of the ISFET device. There are some efforts done to characterize ISFET device in order to ensure that the ISFET device could be simulated and integrated with other silicon-based devices and produce highly value-added sensor products.
[5] Unfortunately, most of the reports are focusing on the system level device modeling such as using VHDL or Verilog-A platforms. This requires huge efforts in understanding the program source code and compiling the whole program for the sake of proper ISFET model extraction. There are also reports on ISFET model development based on the well-known SPICE (Simulation Program with Integrated Circuit Emphasis) simulator but the model still contains several parameters which are not SPICE-compatible and more towards the behavioral modeling. Besides that the said behavioral model also do not provides any tool or method for the critical model extraction purpose.
[6] Integrated circuit designers usually use circuit simulator to test the circuit design. In most cases, a simulation test is done to verify the design functionalities prior to the actual wafer fabrication stage. Besides that, the designers use the simulation analysis for further design optimization as well as predicting the design yield with the availability of accurate device model. ISFET is one of the available devices in semiconductor industry. A part from its important role in the development of highly integrated sensor products, the device is actually suffers the lack of support in device modelling department. This drawback has leads to difficulties in integrating such device into the complete circuit architecture. There are prior arts have been developed for ISFET model but they typically used either system level or hybrid model platforms which resulting to the complicated model extraction flow, as shown in Figure 1. Considering the fact that the current ISFET models are developed based on certain platforms, so it is only suitable for certain simulator and cannot be easily ported into other simulators. These constrains have actually put further dilemma to the ISFET device engineer and circuit designer in finding the correct solution during the design integration stage. Therefore, there is need to develop a user-friendly ISFET model to be easily used and understand by both device engineer and circuit designer.
[7] SUMMARY OF THE INVENTION
[8] According to an aspect of the present invention, the present invention provides a method of generating SPICE-compatible ISFET model using built-in optimizer function, wherein the methods comprising: identifying ISFET device geometries for width, length and gate oxide thickness as inputs in initial ISFET modeling (100); and measuring electrical and electrochemical characteristics of the fabricated ISFET device (200); characterized in that transferring the electrical and electrochemical characteristics measurement data into SPICE netlist and correlating with simulation setup (300); and optimizing the ISFET model parameters using optimizer in SPICE simulator (400).
[9] The above provision is advantageous as it provides a method to generate a compact
SPICE model based on the available sub-circuit model descriptions. SPICE is the de- facto standard which has revolutionized the semiconductor industry and is easily ported to other non-SPICE circuit simulators such as Spectre and Eldo. The constrain of integration between electrical and electrochemical characteristics is handled by extracting standard MOSFET model parameters for standard electrical part first follows by the sub-circuit modeling to take care on the electrochemical part. It serves as a generic description of the ISFET devices in different kind of supported commercial and educational simulators as it use SPICE-compatible format. The present invention requires the electrical measurement from actual fabricated ISFET device. The measurement results are transferred into the circuit simulator netlist for the extraction of related model parameters. In the initial stage, the uses of default model parameters would not show good agreement between measured and simulated data. Built-in optimizer function in SPICE circuit simulator is utilized in the present invention for the curve fitting between measured and simulated.
[ 10] BRIEF DESCRIPTION OF THE DRAWINGS
[1 1] Figure 1 illustrates the flow chart of the prior art of the present invention.
[12] Figure 2 illustrates the method of generating SPICE-compatible ISFET model of the present invention.
[13] Figure 3 illustrates details of ISFET measurement flow from electrical to electrochemical characteristics.
[14] Figure 4illustrates the optimization process to ensure the good fitting between measured and simulated curves.
[15] Figure 5 illustrates an example of optimization steps with SPICE model parameters and measurement and simulation setup.
[16] Figure 6illustrates the example of SPICE simulation file for model extraction
process.
[17] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[ 18] Generally, the present invention relates to amethod of generating SPICE-compatible ISFET model using built-in optimizer function, wherein the methods comprising: identifying ISFET device geometries for width, length and gate oxide thickness as inputs in initial ISFET modeling (100); and measuring electrical and electrochemical characteristics of the fabricated ISFET device (200); characterized in that transferring the electrical and electrochemical characteristics measurement data into SPICE netlist and correlating with simulation setup (300); and optimizing the ISFET model parameters using optimizer in SPICE simulator (400).
[19] With reference to Figure 2, a wafer with fabricated ISFET structures is required in the first stage of the extraction flow. The geometrical parameters such as length (L), width (W) and gate oxide thickness (TOX) need to be identified first for the suitable selection of level in device modeling (100). Bigger ISFET structure could be modeled with SPICE model level 1 , 2 or 3 while smaller ISFET structure need to use SPICE model level 13 (i.e. BSIM1). The next step is the actual device measurement using parameter analyzer (200). The step of measuring electrical and electrochemical characteristics (200) further comprising: measuring I-V curves at reference, lower and upper pH values (201); and exporting the measurement data into text file with certain format to agree with simulation setup (203).
[20] The electrical and electrochemical measurements are then transferred to the SPICE netlist (300) which contains the MOS model parameters and related sub-circuit description of the ISFET electrochemical component.The step of transferring the electrical and electrochemical characteristics measurement data into SPICE netlist (300) further comprising: setting the optimization setup for number of iterations, calculation of error between measured and simulated data and optimization acceptance criteria (301 ); connecting and sweeping the ISFET terminals for I-V curves simulation (303); and determining the correct setup with respect to the measurement data (305).
[21] The model parameters are extracted and optimized using built-in optimizer (400) available in the SPICE simulator to fit the measured and simulated curves. The step of optimizing the ISFET model parameters (400) further comprising: setting the initial ISFET model with default model parameters (401); adding the initial ISFET model into the SPICE netlist in accordance with the obtained measurement data (403);
identifying the SPICE model parameters for each optimization steps (405); setting the optimization range for the minimum and maximum values based on the provided typical value (407); [22] simulating the SPICE netlist and optimization process is done based on the provided ISFET model parameters and optimization range (409); comparing the measured and simulated curves for a good fitting (41 1); adjusting the optimization range if the fitting is not good, in order to improve the fitting quality and continuing with the optimization (413); and continuing the optimization process if the fitting is good until it completes all the steps (415). The step of setting the initial ISFET model further comprising (401): selecting BSIMI model with related ISFET sub-circuit model parameters (401a) and the typical model parameters comprising typical values for vfbO, phiO, kl, k2, etaO, x3e, muz, mus, uOO, ul , x3ul , x3ms, x2e, x2m, x2ms, x2u0, x2ul , n0, nbO, ndO, Nsil and Nnit.The optimization process continues until the error between measured and simulated data are less than root-mean-square (RMS) error is less than 10%.
[23] The details of ISFET measurement flow from electrical to electrochemical characteristics are shown in Figure 3. Electrical characteristics are referring to the I-V curves measurements at typical or reference pH value while electrochemical characteristics are referring to the I-V curves measurement at pH smaller and bigger than the reference value. Figure 4 illustrates the optimization process to ensure the good fitting between measured and simulated curves. The optimization process loops through all the optimization steps, so as to consider one optimization step at a time. Figure 5 is a table illustrating an example of optimization steps with SPICE model parameters and measurement and simulation setup. Figure 6 illustrates the example of SPICE simulation file for model extraction process.
[24] Although the invention has been described with reference to particular embodiment, it is to be understood that the embodiment is merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiment that other arrangements may be devised without departing from the scope of the present invention as defined by the appended claims.

Claims

Claims
[Claim 1 ] A method of generating SPICE-compatible ISFET model comprising:
identifyinglSFET device geometries for width, length and gate oxide thickness as inputs in initial ISFET modeling (100); and
measuringelectrical and electrochemical characteristics of the fabricated ISFET device (200);
characterizedin that
transferringthe electrical and electrochemical characteristics measurement data into SPICE netlist and correlating with simulation setup (300); and
optimizingthe ISFET model parameters using optimizer in SPICE simulator (400).
[Claim 2] A method of generating SPICE-compatible ISFET model as claimed in
Claim 1, wherein the step of measuring electrical and electrochemical characteristics (200) further comprising:
measuringl-V curves at reference, lower and upper pH values (201); and
exportingthe measurement data into text file with certain format to agree with simulation setup (203).
[Claim 3] A method of generating SPICE-compatible ISFET model as claimed in
Claim 1 , wherein the step of transferring the electrical and electrochemical characteristics measurement data into SPICE netlist (300) further comprising:
settingthe optimization setup for number of iterations, calculation of error between measured and simulated data and optimization acceptance criteria (301);
connectingand sweeping the ISFET terminals for I-V curves simulation (303); and
determiningthe correct setup with respect to the measurement data (305).
[Claim 4] A method of generating SPICE-compatible ISFET model as claimed in
Claim 1 , wherein the step of optimizing the ISFET model parameters (400) further comprising:
settingthe initial ISFET model with default model parameters (401); addingthe initial ISFET model into the SPICE netlist in accordance with the obtained measurement data (403);
identifyingthe SPICE model parameters for each optimization steps (405);
settingthe optimization range for the minimum and maximum values based on the provided typical value (407); simulatingthe SPICE netlist and optimization process is done based on the provided ISFET model parameters and optimization range (409); comparingthe measured and simulated curves for a good fitting (41 1); adjustingthe optimization range if the fitting is not good, in order to improve the fitting quality and continuing with the optimization (413); and
continuingthe optimization process if the fitting is good until it completes all the steps (415).
[Claim 5] A method of generating SPICE-compatible ISFET model as claimed in
Claim 4, wherein the step of setting the initial ISFET model further comprising (401):
selectingBSIMl model with related ISFET sub-circuit model parameters (401 a).
[Claim 6] A method of generating SPICE compatible ISFET model as claimed in
Claim 4, wherein the step of continuing the optimization process (415) covers all steps right from threshold voltage, drain current, subthreshold swing parameters, to surface site density parameters.
[Claim 7] A method of generating SPICE-compatible ISFET model as claimed in
Claim 5, wherein the typical model parameters comprising typical values for vfbO, phiO, kl , k2, etaO, x3e, muz, mus, uOO, ul , x3ul , x3ms, x2e, x2m, x2ms, x2u0, x2ul , nO, nbO, ndO, Nsil and Nnit.
PCT/MY2013/000192 2012-11-14 2013-11-13 A method of generating spice-compatible isfet model WO2014077671A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
MYPI2012004928 2012-11-14
MYPI2012004928 2012-11-14

Publications (1)

Publication Number Publication Date
WO2014077671A1 true WO2014077671A1 (en) 2014-05-22

Family

ID=49885355

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/MY2013/000192 WO2014077671A1 (en) 2012-11-14 2013-11-13 A method of generating spice-compatible isfet model

Country Status (1)

Country Link
WO (1) WO2014077671A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105160141A (en) * 2015-10-22 2015-12-16 上海华虹宏力半导体制造有限公司 Modeling method for sub-circuit model of ultrahigh voltage field-effect transistor
CN109543299A (en) * 2018-11-22 2019-03-29 上海华力微电子有限公司 Interconnect capacitance SPICE modeling method
CN113128155A (en) * 2021-04-21 2021-07-16 南京华大九天科技有限公司 Semiconductor model and model establishing method thereof

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
"BSIM3v3.2.2 Manual. CHAPTER 6: Parameter Extraction", 1 January 1999 (1999-01-01), pages 6 - 1, XP055104580, Retrieved from the Internet <URL:http://www.ee.ucr.edu/~rlake/EE135/SPICE/BerkeleySpice/BSIMv323/chp6.pdf> [retrieved on 20140226] *
ANKELE B ET AL: "Enhanced MOS parameter extraction and SPICE modelling for mixed analogue and digital circuit simulation", MICROELECTRONIC TEST STRUCTURES, 1989. ICMTS 1989. PROCEEDINGS OF THE 1989 INTERNATIONAL CONFERENCE ON EDINBURGH, UK 13-14 MARCH 1989, NEW YORK, NY, USA,IEEE, US, 13 March 1989 (1989-03-13), pages 73 - 78, XP010043014, ISBN: 978-0-87942-714-6, DOI: 10.1109/ICMTS.1989.39285 *
MARTINOIA S ET AL: "A behavioral macromodel of the ISFET in SPICE", SENSORS AND ACTUATORS B: CHEMICAL: INTERNATIONAL JOURNAL DEVOTED TO RESEARCH AND DEVELOPMENT OF PHYSICAL AND CHEMICAL TRANSDUCERS, ELSEVIER S.A, CH, vol. 62, no. 3, 1 March 2000 (2000-03-01), pages 182 - 189, XP004194214, ISSN: 0925-4005, DOI: 10.1016/S0925-4005(99)00377-9 *
MARTINOIA S ET AL: "Modeling ISFET microsensor and ISFET-based microsystems: a review", SENSORS AND ACTUATORS B: CHEMICAL: INTERNATIONAL JOURNAL DEVOTED TO RESEARCH AND DEVELOPMENT OF PHYSICAL AND CHEMICAL TRANSDUCERS, ELSEVIER S.A, CH, vol. 105, no. 1, 14 February 2005 (2005-02-14), pages 14 - 27, XP027810274, ISSN: 0925-4005, [retrieved on 20050214] *
NAIMI S E ET AL: "Modeling of the pH-ISFET thermal drift", MICROELECTRONICS (ICM), 2009 INTERNATIONAL CONFERENCE ON, IEEE, PISCATAWAY, NJ, USA, 19 December 2009 (2009-12-19), pages 288 - 291, XP031631870, ISBN: 978-1-4244-5814-1 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105160141A (en) * 2015-10-22 2015-12-16 上海华虹宏力半导体制造有限公司 Modeling method for sub-circuit model of ultrahigh voltage field-effect transistor
CN105160141B (en) * 2015-10-22 2018-11-09 上海华虹宏力半导体制造有限公司 Super-pressure field-effect tube sub-circuit model modeling method
CN109543299A (en) * 2018-11-22 2019-03-29 上海华力微电子有限公司 Interconnect capacitance SPICE modeling method
CN113128155A (en) * 2021-04-21 2021-07-16 南京华大九天科技有限公司 Semiconductor model and model establishing method thereof

Similar Documents

Publication Publication Date Title
Variyam et al. Prediction of analog performance parameters using fast transient testing
US11657201B2 (en) Computer implemented system and method of identification of useful untested states of an electronic design
US9589096B1 (en) Method and apparatus for integrating spice-based timing using sign-off path-based analysis
US8548788B2 (en) Technology computer-aided design (TCAD)-based virtual fabrication
CN102314522B (en) Optimizing method of analogue integrated circuit design
CN105279345B (en) A kind of soft IP kernel evaluating method of spacecraft numeral
JP2008523516A (en) Stochastic analysis process optimization for integrated circuit design and manufacturing
CN102385650B (en) Constructing mapping between model parameters and electrical parameters
Bounceur et al. Estimation of analog parametric test metrics using copulas
US10713405B2 (en) Parameter generation for semiconductor device trapped-charge modeling
CN103838894A (en) Method for achieving automatic PDK testing
CN102508977B (en) Circuit optimization method for artificial circuit transplant and circuit optimization device for artificial circuit transplant
JP4882747B2 (en) Variation simulation system
WO2008040748A1 (en) Method and apparatus for the simultaneous multi-level and/or multi-simulator design optimization of electronic circuits
WO2014077671A1 (en) A method of generating spice-compatible isfet model
US7404158B2 (en) Inspection method and inspection apparatus for semiconductor integrated circuit
CN108233356B (en) Consistency evaluation method and evaluation platform for photovoltaic inverter controller
US20080141189A1 (en) Method for robust statistical semiconductor device modeling
CN101196936A (en) Fast modeling method of MOS transistor electricity statistical model
CN110110406B (en) Slope stability prediction method for achieving LS-SVM model based on Excel computing platform
CN115688641A (en) Method and system for representing variation parameters on standard cell sheet
CN1530664A (en) Circuit analog method
US8185369B2 (en) Method and apparatus for characterizing properties of electronic devices depending on device parameters
JP4777227B2 (en) Parameter extraction method, circuit operation verification method, and storage medium comprising a program for executing the parameter extraction method
CN107480366A (en) A kind of method and system that leakage current temperature characterisitic is improved for model

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13814655

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13814655

Country of ref document: EP

Kind code of ref document: A1