CN105160141A - Modeling method for sub-circuit model of ultrahigh voltage field-effect transistor - Google Patents
Modeling method for sub-circuit model of ultrahigh voltage field-effect transistor Download PDFInfo
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Abstract
The invention provides a modeling method for a sub-circuit model of an ultrahigh voltage field-effect transistor. The method includes the steps that a bypass resistor and a bypass voltage source which are connected in series are additionally arranged in an original sub-circuit model of the ultrahigh voltage field-effect transistor to constitute a bypass circuit, so that an updated sub-circuit model is formed; the bypass voltage source is a voltage control voltage source, one end of the bypass resistor is connected to the bypass voltage source, and the other end of the bypass resistor is connected to the ground; one end of the bypass voltage source is connected and the other end of the bypass voltage source is used as a bypass node; the original sub-circuit model of the ultrahigh voltage field-effect transistor comprises a drain end parasitic resistor which is connected with the drain end of a transistor and a source end parasitic resistor which is connected with the source end of the transistor.
Description
Technical field
The present invention relates to the modeling field of high voltage analog circuits, more particularly, the present invention relates to a kind of UHV (ultra-high voltage) field effect transistor sub circuit model modeling method.
Background technology
Characteristic after current industry model extends to the withstand voltage LDMOS of superelevation (Laterally Diffused Metal Oxide Semiconductor) voltage is generally undesirable, and the model that can describe quasi-saturation effect can have again good VDS voltage extension characteristics to describe does not have.
Specifically, have a wide range of applications in the power circuit design of high pressure field effect transistor LDMOS in mimic channel, its applied voltage scope is higher, greatly withstand voltage, is used in high-power circuit application.Fig. 1 be a kind of can the current-voltage characteristic curve of overpressure resistant NLDMOS, puncturing of it is withstand voltage higher than 500V, the direct current normal area of application of its voltage is 40V, but in some driving circuits, the overshoot voltage of circuit can reach more than 500V, also in some driving circuit, its moment applied voltage often can be in the state of hectovolt.Therefore, under the state of circuit for generating overshoot, the simulation result of device also needs to reflect objective physical characteristics.From the current-voltage characteristic curve Fig. 1, this NLDMOS has the ubiquitous quasi-saturation effect of high pressure field effect transistor simultaneously, along with the increase of gate source voltage Vgs, source electric current I ds draw close gradually, increase amplitude reduces, and the model emulation result in solid line can describe this phenomenon too.This model is a kind of sub circuit model that industry generally adopts, and consist of MOS transistor and to connect an a drain terminal dead resistance R1 and source dead resistance R2, wherein G represents grid.Drain terminal dead resistance resistance changes with the change of bias voltage VDS, and the resistive voltage formula of drain terminal dead resistance R1 is:
R1=rds* (1+vv1*abs (v (d, s))+vv2*v (d, s) * v (d, s)) formula (1)
Wherein rds is the valuation of drain terminal dead resistance, and vv1, vv2 are the artificial correction factor of voltage, and v (d, s) is LDMOS source and drain end electric current, and abs is the ABS function carried in SPICE emulator.In electronic circuit, r1 has successfully carried out good description to quasi-saturation effect by this describing mode within the scope of 40V.
If but after the source and drain end current and power supply of this model is expanded to 500V, we find that downward trend has appearred in drain current, this is not physics, because the electric current of actual LDMOS only can present saturated but there will not be and significantly decline.But above-mentioned resistive voltage formula cannot avoid this phenomenon in model, because VV1, VV2 are the coefficient of quadratic term respectively, as long as will increase all the time along with the increase resistance of v (d, s).But in actual conditions, after the drain terminal voltage of LDMOS reaches certain numerical value, the depletion region of drain terminal drift region can tend to saturated, therefore resistance can't infinite change large.Solve this problem of model, just must revise resistive voltage formula.
Summary of the invention
Technical matters to be solved by this invention is for there is above-mentioned defect in prior art, provides a kind of and can build the model that has more physics ductility and can bring for circuit design the UHV (ultra-high voltage) field effect transistor sub circuit model modeling method emulating reference more accurately.
In order to realize above-mentioned technical purpose, according to the present invention, provide a kind of UHV (ultra-high voltage) field effect transistor sub circuit model modeling method, comprise: add the bypass resistance and bypass voltage source formation bypass circuit that utilize series connection at former UHV (ultra-high voltage) field effect transistor sub circuit model, to form the sub circuit model of renewal; Wherein bypass voltage source is Voltage-controlled Current Source, and bypass resistance one end is connected to bypass voltage source and other end ground connection; One end, bypass voltage source is connected to one end and is connected to, and the other end is as shunt nodes;
Its Central Plains UHV (ultra-high voltage) field effect transistor sub circuit model comprises the drain terminal dead resistance be connected with transistor drain terminal and the source dead resistance be connected with transistor source.
Preferably, in former UHV (ultra-high voltage) field effect transistor sub circuit model, the resistive voltage formula of drain terminal dead resistance is the first formula as follows:
r1＝rds*(1+vv1*abs(v(d,s))+vv2*v(d,s)*v(d,s))
Wherein rds is the valuation of drain terminal dead resistance, and vv1, vv2 are the artificial correction factor of voltage, and v (d, s) is LDMOS source and drain end electric current, and abs is the ABS function carried in SPICE emulator.
Preferably, the voltage of the voltage V (nvd, 0) of shunt nodes is the second formula as follows:
v(nvd,0)＝'deltaV1-(deltaV2/(ec1/(abs(v(d,s)**a))+ec2*(abs(v(d,s))**b))**exp)'
Wherein, bypass voltage source ec1f controls by V (d, s), the function that voltage V (nvd, 0) is formed for v (d, s) numerical value; DeltaV1, deltaV2, ec1, ec2, a, b, exp7 are correction factor, and wherein deltaV1, deltaV2, ec1, ec2 are mathematics correction factor, and a, b, exp are index correction factor.
Preferably, described second formula is substituted into described first formula and is revised formula as follows:
r1＝rds*(1.0+vr1*v(nvd,0)+vr2*v(nvd,0)*v(nvd,0))*(1+vv1*abs(v(d,s)))
Wherein vr1, vr2 are the correction factor regulating current/voltage quasi saturation district amplitude.
Preferably, the simulation result for the measured data of UHV (ultra-high voltage) field effect transistor and the sub circuit model of renewal is compared, by adjustment parameter d eltaV1, deltaV2, ec1, ec2, a, b, exp, vr1, vr2, obtain fitting result.
Preferably, described measured data is the measured data recorded between 0 to 40V at source-drain voltage.
Preferably, for fitting result, source-drain voltage is extended to 500V, checks the variation tendency of its drain current.
Preferably, model parameter extraction instrument is utilized to be compared by the simulation result for the measured data of UHV (ultra-high voltage) field effect transistor and the sub circuit model of renewal.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its adjoint advantage and feature, wherein:
Fig. 1 schematically shows drain current Id and the same simulation comparison of the test of drain voltage Vds under 25C room temperature of 40V high pressure field effect transistor, and figure dotted line is measured data, and solid line is master mould emulated data.
Fig. 2 schematically shows the simulation curve seen after high-voltage field effect tube model Vds voltage is extended to 500V, and improper whereabouts trend appears in Ids electric current.
Fig. 3 schematically shows the LDMOS sub circuit model according to prior art.
Fig. 4 schematically shows sub circuit model according to the preferred embodiment of the invention, and wherein NVD node voltage V (nvd, 0) is artificial is again applied in the voltage expression of r1.
Fig. 5 schematically shows drain current Id according to 40V high pressure field effect transistor of the present invention and the same simulation comparison of the test of drain voltage Vds under 25C room temperature, figure dotted line is measured data, solid line is master mould emulated data, the adjustment of the parameter newly added in r1 formula, obtains good matched curve in 40V.
Fig. 6 schematically shows, according to of the present invention, source and drain end electric current is extended to the model emulation result after 500V.
It should be noted that, accompanying drawing is for illustration of the present invention, and unrestricted the present invention.Note, represent that the accompanying drawing of structure may not be draw in proportion.Further, in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention clearly with understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
For the electronic circuit structure of the description high-voltage LDMOS shown in Fig. 3, comprising: the drain terminal dead resistance R1 be connected with transistor drain terminal D and the source dead resistance R2 be connected with transistor source.
Wherein
R1=rds* (1+vv1*abs (v (d, s))+vv2*v (d, s) * v (d, s)) formula (1)
Solve the trend that the infinite change of electrical resistance v (d, s) is large, the present invention first antithetical phrase circuit structure revises, and is modified as shown in Figure 4.Utilize the bypass resistance Rnvd of series connection and bypass voltage source ec1f to form bypass circuit, bypass voltage source ec1f is Voltage-controlled Current Source.Bypass resistance Rnvd one end is connected to bypass voltage source ec1f and other end ground connection.Ec1f one end, bypass voltage source is connected to one end and is connected to, and the other end is as shunt nodes NVD.
The object of bypass voltage source ec1f is as independent voltage source in electronic circuit, and this voltage value finally can be reflected in the resistance formula of former r1.The voltage value of this voltage source is with v (d, s) change, and its pass is a mathematic(al) representation, and the voltage of the voltage V (nvd, 0) of shunt nodes NVD is:
v(nvd,0)＝'deltaV1-(deltaV2/(ec1/(abs(v(d,s)**a))+ec2*(abs(v(d,s))**b))**exp)'
Formula (2)
Bypass voltage source ec1f controls by V (d, s), and the function that voltage V (nvd, 0) is formed for v (d, s) numerical value, with the addition of deltaV1, deltaV2, ec1, ec2, a, b, exp7 correction factor simultaneously.Wherein deltaV1, deltaV2, ec1, ec2 are mathematics correction factor, and a, b, exp are index correction factor.
This expression formula makes V (nvd, 0) voltage increase with the increase of v (d, s), but can tend to saturated thereupon, be regulated by the parameter of index correction term a, b, exp, v (nvd can be regulated, 0) saturation rate is changed with v (d, s).The relational expression of v (nvd, 0) is then written in former resistance formula (1), former resistance formula is revised as following form:
r1＝rds*(1.0+vr1*v(nvd,0)+vr2*v(nvd,0)*v(nvd,0))*(1+vv1*abs(v(d,s)))
Formula (3)
Wherein vr1, vr2 is the correction factor regulating current/voltage quasi saturation district amplitude, and deltaV1, deltaV2, ec1, ec2 can change i-v curve is transitioned into saturation region slope from linear zone, measured data (the IDVD curve of 0 to 40V) in Fig. 1 is compared (such as with new sub circuit model (r1 formula upgrades) simulation result, in the model parameter extraction instrument MBP that the data importing in former Fig. 1 generally can be adopted to industry, and new electronic circuit is called in software make it same real data comparison), by adjustment deltaV1, deltaV2, ec1, ec2, a, b, exp, vr1, 9 parameters such as vr2, same acquisition is as the fitting result of Fig. 5.Vds in Fig. 5 is extended, after being extended to 500V, can see that in Fig. 6, electric current is saturated smooth, do not occur declining.Visible, by said method, the LDMOS model having more physics ductility can be realized, bring for circuit design and emulate reference more accurately.
Visible, the present invention is by the voltage expression of the r1 in amendment atom circuit, by V (nvd, 0) join in the expression formula of r1, add vr1, vr2 is the correction factor regulating IDVD quasi saturation district amplitude simultaneously, by the adjustment to all coefficients, LDMOS can well be realized in the continuity of the condition drag of 500V and physics ductility, the model accuracy under normal voltage range can be met again simultaneously.
In addition, it should be noted that, unless stated otherwise or point out, otherwise the term " first " in instructions, " second ", " the 3rd " etc. describe only for distinguishing each assembly, element, step etc. in instructions, instead of for representing logical relation between each assembly, element, step or ordinal relation etc.
Be understandable that, although the present invention with preferred embodiment disclose as above, but above-described embodiment and be not used to limit the present invention.For any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the technology contents of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (8)
1. a UHV (ultra-high voltage) field effect transistor sub circuit model modeling method, is characterized in that comprising:
The bypass resistance and bypass voltage source formation bypass circuit that utilize series connection is added, to form the sub circuit model of renewal at former UHV (ultra-high voltage) field effect transistor sub circuit model; Wherein bypass voltage source is Voltage-controlled Current Source, and bypass resistance one end is connected to bypass voltage source and other end ground connection; One end, bypass voltage source is connected to one end and is connected to, and the other end is as shunt nodes;
Its Central Plains UHV (ultra-high voltage) field effect transistor sub circuit model comprises the drain terminal dead resistance be connected with transistor drain terminal and the source dead resistance be connected with transistor source.
2. UHV (ultra-high voltage) field effect transistor sub circuit model modeling method according to claim 1, is characterized in that, in former UHV (ultra-high voltage) field effect transistor sub circuit model, the resistive voltage formula of drain terminal dead resistance is the first formula as follows:
r1＝rds*(1+vv1*abs(v(d,s))+vv2*v(d,s)*v(d,s))
Wherein rds is the valuation of drain terminal dead resistance, and vv1, vv2 are the artificial correction factor of voltage, and v (d, s) is LDMOS source and drain end electric current, and abs is the ABS function carried in SPICE emulator.
3. UHV (ultra-high voltage) field effect transistor sub circuit model modeling method according to claim 2, is characterized in that, the voltage of the voltage V (nvd, 0) of shunt nodes is the second formula as follows:
v(nvd,0)＝'deltaV1-(deltaV2/(ec1/(abs(v(d,s)**a))+ec2*(abs(v(d,s))**b))**exp)'
Wherein, bypass voltage source ec1f controls by V (d, s), the function that voltage V (nvd, 0) is formed for v (d, s) numerical value; DeltaV1, deltaV2, ec1, ec2, a, b, exp7 are correction factor, and wherein deltaV1, deltaV2, ec1, ec2 are mathematics correction factor, and a, b, exp are index correction factor.
4. UHV (ultra-high voltage) field effect transistor sub circuit model modeling method according to claim 1 and 2, characterized by further comprising:
Described second formula is substituted into described first formula and is revised formula as follows:
r1＝rds*(1.0+vr1*v(nvd,0)+vr2*v(nvd,0)*v(nvd,0))*(1+vv1*abs(v(d,s)))
Wherein vr1, vr2 are the correction factor regulating current/voltage quasi saturation district amplitude.
5. UHV (ultra-high voltage) field effect transistor sub circuit model modeling method according to claim 4, characterized by further comprising:
Simulation result for the measured data of UHV (ultra-high voltage) field effect transistor and the sub circuit model of renewal is compared, by adjustment parameter d eltaV1, deltaV2, ec1, ec2, a, b, exp, vr1, vr2, obtains fitting result.
6. UHV (ultra-high voltage) field effect transistor sub circuit model modeling method according to claim 5, is characterized in that, described measured data is the measured data recorded between 0 to 40V at source-drain voltage.
7. UHV (ultra-high voltage) field effect transistor sub circuit model modeling method according to claim 5, is characterized in that, for fitting result, source-drain voltage is extended to 500V, check the variation tendency of its drain current.
8. UHV (ultra-high voltage) field effect transistor sub circuit model modeling method according to claim 1 and 2, is characterized in that, utilize model parameter extraction instrument to be compared by the simulation result for the measured data of UHV (ultra-high voltage) field effect transistor and the sub circuit model of renewal.
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| CN110765708A (en) * | 2019-12-05 | 2020-02-07 | 上海华虹宏力半导体制造有限公司 | Simulation method |
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| CN110765708B (en) * | 2019-12-05 | 2023-05-23 | 上海华虹宏力半导体制造有限公司 | Simulation method |
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