CN108133101B - Auxiliary layer of inductor layout and method for extracting device parameters - Google Patents
Auxiliary layer of inductor layout and method for extracting device parameters Download PDFInfo
- Publication number
- CN108133101B CN108133101B CN201711392318.9A CN201711392318A CN108133101B CN 108133101 B CN108133101 B CN 108133101B CN 201711392318 A CN201711392318 A CN 201711392318A CN 108133101 B CN108133101 B CN 108133101B
- Authority
- CN
- China
- Prior art keywords
- inductor
- layout
- auxiliary layer
- coil
- device parameters
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Abstract
The invention provides an auxiliary layer of an inductor layout and a method for extracting device parameters. The inductor layout is arranged in an octagon shape, a first outgoing line and a second outgoing line are arranged at two ends of the inductor layout, wherein an auxiliary layer of the inductor layout is arranged in a rectangular shape and longitudinally extends to the outer side of an inductor coil of the inductor layout, and the auxiliary layer is longitudinally adjacent to the inner side walls of the first outgoing line and the second outgoing line at the two ends of the inductor layout. A method for extracting device parameters of an inductor layout includes, in step S1: drawing an auxiliary layer of the inductor layout; step S2: calculating device parameters by an electronic design automation tool (EDA); step S3: and operating the technical file, extracting device parameters and outputting a layout icon. The invention reduces the number of the auxiliary layers, and reduces the potential risk caused by inaccurate drawing of the auxiliary layers, the setting of extra layout design rules, the development of related DRC files and other work, thereby reducing the labor cost, improving the work efficiency and ensuring the product quality.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to an auxiliary layer of an inductor layout and a method for extracting device parameters.
Background
An Inductor is one of the basic elements in an integrated circuit, and is mostly a Planar Inductor (Planar Inductor). The planar inductor comprises a spiral line, a lower layer connecting line and a through hole. Planar inductors can be divided into circular, octagonal and square configurations. Circular planar inductors are difficult to map, so most integrated circuit designers adopt square and octagonal layout structures, and octagonal planar capacitors are widely used.
Compared with a discrete circular inductor, the integrated planar capacitor has the advantages that the inner ring is not a regular geometric circle, and irregular geometric figures have many difficulties for processing Electronic Design automation tools (EDA). How to accurately extract the parameters of the planar capacitor layout device, such as the radius R of the inner ring of the inductor, the number of turns N of the coil and the width W of the coil, becomes a challenge of physical verification of the layout.
In the prior art, multiple auxiliary layers are added on the basis of an inductor layout to help an EDA tool to identify an accurate region, and embedded commands are used for extracting device parameters. Drawing a regular octagon on the auxiliary layer for calculating the inner diameter R; an octagonal ring is drawn between the coils with the auxiliary layer for counting the number of coil turns N.
Although adding multiple auxiliary layers reduces the difficulty of programming EDA tools, the disadvantages are also apparent, respectively: (1) additional design rules are added. The addition of the auxiliary layer needs additional design rules for defining the drawing method of the layer, and only with accurate drawing method, the EDA tool can be assisted to correctly extract the parameters of the inductance device. This is very strict for layout engineers. (2) Increasing the difficulty of checking the design rules. When a design rule is formulated, a corresponding design rule check technical file (DRC) detection layout is required. How to correctly detect the auxiliary layer regular geometric figure can correctly reflect the characteristics of the irregular geometric figure, and is a great challenge to DRC programming. (3) Increasing the risk of circuit design. The auxiliary layer is used for EDA work to assist in identifying the layout geometric figure and does not participate in photomask publishing. If the auxiliary layer cannot be used correctly, namely the inner diameter and the coil distance cannot be covered correctly, the accuracy of extracting device parameters is influenced, inaccurate device parameters are substituted into the SPICE Model for simulation, judgment of a designer on circuit design correction can be misled, and therefore the risk of products is increased.
Therefore, although the design of the auxiliary layer can reduce the programming difficulty of the EDA, too many auxiliary layers will inevitably increase the extra workload and may also pose a risk to the circuit design. Therefore, aiming at the problems in the prior art, the designer of the present invention is based on the experience of the industry for many years to actively research and improve, and the invention provides a method for extracting the auxiliary layer of the inductor layout and the device parameters.
Disclosure of Invention
The invention provides an auxiliary layer of an inductor layout aiming at the defects that in the prior art, excessive auxiliary layers inevitably increase extra workload and may cause risks to circuit design.
It is another object of the present invention to provide a method for extracting device parameters of an inductor layout, which is directed to the defects in the prior art that excessive auxiliary layers will increase extra workload and may cause risks to circuit design.
In order to achieve the purpose of the invention, the invention provides an auxiliary layer of an inductor layout, wherein the inductor layout is arranged in an octagonal shape, and a first outgoing line and a second outgoing line are arranged at two ends of the inductor layout, wherein the auxiliary layer of the inductor layout is arranged in a rectangular shape and longitudinally extends to the outer side of an inductor coil of the inductor layout, and the auxiliary layer is longitudinally adjacent to the inner side walls of the first outgoing line and the second outgoing line at the two ends of the inductor layout.
To achieve still another object of the present invention, the present invention provides a method for extracting device parameters of an inductor layout, comprising,
step S1 is executed: drawing an auxiliary layer of the inductor layout; the inductor layout is arranged in an octagon shape, a first outgoing line and a second outgoing line are arranged at two ends of the inductor layout, an auxiliary layer of the inductor layout is arranged in a rectangular shape and longitudinally extends to the outer side of an inductor coil of the inductor layout, and the auxiliary layer is longitudinally adjacent to the inner side walls of the first outgoing line and the second outgoing line at two ends of the inductor layout;
step S2 is executed: calculating device parameters by an electronic design automation tool (EDA);
step S3 is executed: and operating the technical file, extracting device parameters and outputting a layout icon.
Optionally, the side length of the auxiliary layer at the inner ring of the inductance coil of the inductance layout is used for calculating the radius R of the inner ring.
Optionally, the inner ring radius R is equivalent to a radius of a transformer _ inside (transformer _ holes)/4, the transformer _ layer is an auxiliary layer, and the inductor _ holes is an inner ring region of the inductor.
Alternatively, the inner turn area indicator _ holes of the inductor is calculated by,
ind_rad:1＝HOLES ind_mt INNER EMPTY
ind_rad＝SIZE ind_rad:1BY Y UNDEROVER
ind _ mt is an inductance coil.
Optionally, the coil width W is calculated by using the side length of the auxiliary layer in the inductor coil of the inductor layout.
Optionally, the coil width W is equivalent to transformer _ inside (winding _ layer, inductor _ metals)/N/2, and inductor _ metals are inductance coils.
Optionally, the number of turns N of the coil is calculated by using the side length of the auxiliary layer within the interval between the inductor coils of the inductor layout.
Optionally, the number of turns N is count (indicator _ space)/2+1, and indicator _ space is a side length within an inductor pitch of the inductor layout.
Optionally, the side length indicator _ space within the inductor coil distance of the inductor layout is calculated by ind _ sp ═ EXT ind _ mt ≦ X region, where X is the maximum inductor coil distance.
In summary, compared with the traditional method for extracting parameters of the inductance device, the method has the advantages that the number of the auxiliary layers is reduced, potential risks caused by inaccurate drawing of the auxiliary layers are reduced, extra layout design rules are set, related DRC files are developed, and the like, so that labor cost is reduced, working efficiency is improved, and product quality is guaranteed.
Drawings
FIG. 1 is a schematic diagram of an auxiliary layer structure of an inductor layout according to the present invention;
FIG. 2 is a flow chart of a method for extracting device parameters of an inductor layout according to the present invention.
Detailed Description
The invention will be described in detail with reference to the following embodiments and drawings for illustrating the technical content, structural features, and achieved objects and effects of the invention.
An Inductor is one of the basic elements in an integrated circuit, and is mostly a Planar Inductor (Planar Inductor). The planar inductor comprises a spiral line, a lower layer connecting line and a through hole. Planar inductors can be divided into circular, octagonal and square configurations. Circular planar inductors are difficult to map, so most integrated circuit designers adopt square and octagonal layout structures, and octagonal planar capacitors are widely used.
Compared with a discrete circular inductor, the integrated planar capacitor has the advantages that the inner ring is not a regular geometric circle, and irregular geometric figures have many difficulties for processing Electronic Design automation tools (EDA). How to accurately extract the parameters of the planar capacitor layout device, such as the radius R of the inner ring of the inductor, the number of turns N of the coil and the width W of the coil, becomes a challenge of physical verification of the layout.
In the prior art, multiple auxiliary layers are added on the basis of an inductor layout to help an EDA tool to identify an accurate region, and embedded commands are used for extracting device parameters. Drawing a regular octagon on the auxiliary layer for calculating the inner diameter R; an octagonal ring is drawn between the coils with the auxiliary layer for counting the number of coil turns N.
Although the difficulty of programming the EDA tool is reduced by adding multiple auxiliary layers, the following disadvantages are obvious: (1) additional design rules are added. The addition of the auxiliary layer needs additional design rules for defining the drawing method of the layer, and only with accurate drawing method, the EDA tool can be assisted to correctly extract the parameters of the inductance device. This is very strict for layout engineers. (2) Increasing the difficulty of checking the design rules. When a design rule is formulated, a corresponding design rule check technical file (DRC) detection layout is required. How to correctly detect the auxiliary layer regular geometric figure can correctly reflect the characteristics of the irregular geometric figure, and is a great challenge to DRC programming. (3) Increasing the risk of circuit design. The auxiliary layer is used for EDA work to assist in identifying the layout geometric figure and does not participate in photomask publishing. If the auxiliary layer cannot be used correctly, namely the inner diameter and the coil distance cannot be covered correctly, the accuracy of extracting device parameters is influenced, inaccurate device parameters are substituted into the SPICE Model for simulation, judgment of a designer on circuit design correction can be misled, and therefore the risk of products is increased.
Therefore, although the design of the auxiliary layer can reduce the programming difficulty of the EDA, too many auxiliary layers will inevitably increase the extra workload and may also pose a risk to the circuit design.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating a structure of an auxiliary layer of an inductor layout according to the present invention. The inductor layout 1 is arranged in an octagonal shape, and a first outgoing line 1a and a second outgoing line 1b are arranged at two ends of the inductor layout. The auxiliary layer 2 of the inductor layout 1 is rectangular and extends to the outer side of the inductor coil 12 of the inductor layout 1 along the longitudinal direction, and the auxiliary layer 2 is adjacent to the inner side walls of the first outgoing line 1a and the second outgoing line 1b at two ends of the inductor layout 1 along the longitudinal direction.
Referring to fig. 2 in conjunction with fig. 1, fig. 2 is a flow chart illustrating a method for extracting device parameters of an inductor layout according to the present invention. The method for extracting the device parameters of the inductance layout comprises the following steps:
step S1 is executed: drawing an auxiliary layer 2 of the inductor layout 1; the inductor layout 1 is arranged in an octagonal shape, and a first outgoing line 1a and a second outgoing line 1b are arranged at two ends of the inductor layout. The auxiliary layer 2 of the inductor layout 1 is rectangular and extends to the outer side of the inductor coil 12 of the inductor layout 1 along the longitudinal direction, and the auxiliary layer 2 is adjacent to the inner side walls of the first outgoing line 1a and the second outgoing line 1b at two ends of the inductor layout 1 along the longitudinal direction.
Step S2 is executed: calculating device parameters by an electronic design automation tool (EDA); wherein, the side length of the auxiliary layer 2 at the inner ring of the inductance coil 12 of the inductance layout 1 is used for calculating the radius R of the inner ring; calculating the width W of the coil by using the side length of the auxiliary layer 2 in the inductance coil 12 of the inductance layout 1; the length of the side of the auxiliary layer 2 in the interval of the inductance coil 12 of the inductance layout 1 is used to calculate the number of turns N of the coil.
Step S3 is executed: and operating the technical file, extracting device parameters and outputting a layout icon. The Layout icon can be used for verifying Layout and Schematic diagram comparison check (Layout Vs schema, LVS). Or the back-end circuit simulation is carried out with the net mark with parasitic capacitance and resistance.
Obviously, the method effectively solves the potential safety hazard caused by the identification device of the multiple auxiliary layers and the calculation of the device parameters, simplifies the layout drawing method, reduces the labor cost and improves the working efficiency.
In order to more intuitively disclose the technical scheme of the present invention, and to highlight the beneficial effects of the present invention, the method for extracting the auxiliary layer and the device parameter of the inductor layout is now described with reference to the specific implementation manner as an example.
In a specific embodiment, a layer is defined as an auxiliary layer, and a layout device is identified by replacing a plurality of auxiliary layers. And calculating parameters of the octagonal inductance layout device by using an electronic design automation tool (EDA), wherein the parameters comprise the radius R of an inner ring, the number of turns N of a coil and the width W of the coil. The method specifically comprises the following steps:
step S1 is executed: drawing an auxiliary layer 2 of the inductor layout 1;
the inductor layout 1 is arranged in an octagonal shape, and a first outgoing line 1a and a second outgoing line 1b are arranged at two ends of the inductor layout. The auxiliary layer 2 of the inductor layout 1 is rectangular and extends to the outer side of the inductor coil 12 of the inductor layout 1 along the longitudinal direction, and the auxiliary layer 2 is adjacent to the inner side walls of the first outgoing line 1a and the second outgoing line 1b at two ends of the inductor layout 1 along the longitudinal direction.
Step S2 is executed: calculating device parameters by an electronic design automation tool (EDA); wherein the content of the first and second substances,
the side length of the auxiliary layer 2 at the inner ring of the inductance coil 12 of the inductance layout 1 is used to calculate the radius R of the inner ring,
R＝perimeter_inside(marking_layer,inductor_holes)/4，
wherein, the marking _ layer is an auxiliary layer, and the inductor _ holes is an inner ring area of the inductance coil 12;
the method for calculating the indicator _ holes comprises the following steps:
ind_rad:1＝HOLES ind_mt INNER EMPTY
ind_rad＝SIZE ind_rad:1 BY Y UNDEROVER
where ind _ mt is an inductor coil.
The side length of the auxiliary layer 2 in the inductor coil 12 of the inductor layout 1 is used to calculate the coil width W,
W＝perimeter_inside(marking_layer,inductor_metals)/N/2，
wherein, inductor _ metals is the inductance coil 12.
The side length of the auxiliary layer 2 in the interval of the inductance coil 12 of the inductance layout 1 is used to calculate the number of turns N of the coil,
N＝count(inductor_space)/2+1，
wherein, indicator _ space is the side length in the interval of the inductance coil 12 of the inductance layout 1;
the calculation method of indicator _ space comprises the following steps:
ind _ sp ═ EXT ind _ mt < ═ X region, where X is the maximum pitch of the inductor coils.
Step S3 is executed: and operating the technical file, extracting device parameters and outputting a layout icon. The Layout icon can be used for verifying Layout and Schematic diagram comparison check (Layout Vs schema, LVS). Or the back-end circuit simulation is carried out with the net mark with parasitic capacitance and resistance.
Furthermore, the method uses an EDA physical verification tool calibre to edit the code file, extracts the device parameters of the inductance layout, and compares and verifies the device parameters with the circuit network mark, and comprises the following specific steps:
and executing the step SI: defining an auxiliary layer INDID, and carrying out auxiliary layer drawing on the inductor layout;
executing step SII: the LVS file is edited by using the calibre svrf language, and the key codes are as follows:
①ind_seed＝INDID INTERACT ind_t4m2
②ind_mt＝ind_t4m1 OR ind_t4m2
③ind_sp＝EXT ind_mt<＝X region
④ind_rad:1＝HOLES ind_mt INNER EMPTY
⑤ind_rad＝SIZE ind_rad:1BY Y UNDEROVER
⑥DEVICE symind_smooth ind t4m2(PLUS) t4m2(MINUS)<ind_sp><ind_seed><ind_t4m2><ind_rad>[
PROPERTY W,R,N
N＝COUNT(ind_sp)/2+1
W＝PERIM_IN(ind_seed,ind_t4m2)/N/2
R＝PERIM_IN(ind_seed,ind_rad)/4
]
⑦TRACE PROPERTY symind_smooth W W
⑧TRACE PROPERTY symind_smooth R R
⑨TRACE PROPERTY symind_smooth N N
firstly, defining an auxiliary layer of an inductance device; secondly, the inductance coils are combined together for calculating the coil distance; the maximum distance between the inductance coils does not exceed Xum, so that the distance is attached to ind _ sp parameters; fifthly, generating an inductance inner ring, and enabling the irregular graph of the inner ring to form a regular octagon for accurately calculating the radius; sixthly, the svrf language defines an inductive device and an output port plus/minus, and device parameters are calculated according to a formula; and seventhly, defining the comparison of the layout network mark and the circuit network mark to obtain the device parameters.
Executing the step SIII: inputting the information of the inductance layout and the circuit network label into an LVS file, and operating the LVS file;
the LVS file operation usually has two modes of interface operation and command operation, and in the invention, the command operation is selected as follows: rules of calibre-lvs-hier silver
Executing step SIV: and outputting an operation result, checking the LVS report file, and comparing and verifying the LVS report file to pass.
By the method, namely the layout drawing method of the single-layer auxiliary layer and the combination of program codes, the parameters R, N, W of the inductance device can be accurately extracted and verified through circuit network marking comparison. The method uses one auxiliary layer to replace the traditional multilayer auxiliary layer, provides a new parameter calculation method, and utilizes an EDA tool to realize the extraction of the parameters of the layout inductor.
Obviously, firstly, the invention uses one auxiliary layer to replace the traditional multi-layer auxiliary layer to mark the inductance device, the drawing method is simple and clear, and the labor cost and the error rate are reduced. Secondly, the calculation method of the inductor device parameter R, W, N is realized by using an EDA tool calibre, and the layout mesh drawing result is as follows:
.SUBCKT symind_smooth_CDNS_4574866073710 1 2
X0 1 2symind_smooth w＝6e-06 r＝4.5e-05 n＝3 $X＝-186610 $Y＝-51410 $D＝122
.ENDS
.SUBCKT symind_smooth_CDNS_4574866073715 3 4
X1 3 4symind_smooth w＝8e-06 r＝5.5e-05 n＝5 $X＝-185623 $Y＝-51780 $D＝123
.ENDS
the display of the net mark result is consistent with the size of the actual inductor layout, and the method is proved to be capable of accurately extracting the parameters of the inductor.
In summary, compared with the traditional method for extracting parameters of the inductance device, the method has the advantages that the number of the auxiliary layers is reduced, potential risks caused by inaccurate drawing of the auxiliary layers are reduced, extra layout design rules are set, related DRC files are developed, and the like, so that labor cost is reduced, working efficiency is improved, and product quality is guaranteed.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Claims (6)
1. A method for extracting device parameters of an inductor layout comprises,
step S1 is executed: drawing an auxiliary layer of the inductor layout; the inductor layout is arranged in an octagon shape, a first outgoing line and a second outgoing line are arranged at two ends of the inductor layout, an auxiliary layer of the inductor layout is arranged in a rectangular shape and longitudinally extends to the outer side of an inductor coil of the inductor layout, and the auxiliary layer is longitudinally adjacent to the inner side walls of the first outgoing line and the second outgoing line at two ends of the inductor layout;
step S2 is executed: calculating device parameters through an electronic design automation tool (EDA), wherein the radius R of an inner ring is calculated by utilizing the side length of the auxiliary layer on the inner ring of an inductance coil of the inductance layout; calculating the width W of the coil by using the side length of the auxiliary layer in the inductance coil of the inductance layout; calculating the number N of turns of the coil by using the side length of the auxiliary layer in the interval of the inductance coil of the inductance layout;
step S3 is executed: and operating the technical file, extracting device parameters and outputting a layout icon.
2. The method as claimed in claim 1, wherein the radius R of the inner ring is equal to or greater than 4, the marking _ layer is an auxiliary layer, and the indicator _ layers is an inner ring region of the inductor.
3. The method for extracting device parameters from an inductor layout as claimed in claim 2, wherein the inner winding region indicator _ HOLES of the inductor winding is calculated by using 1. ind _ rad: 1. HOLES ind _ mt INNER EMPTY. ind _ rad. SIZE ind _ rad: 1. BYY UNDEROVERind _ mt as the inductor winding.
4. The method as claimed in claim 1, wherein the coil width W is equivalent to transformer-inside (winding-layer) N/2, and the inductor-metal is an inductor coil.
5. The method as claimed in claim 1, wherein the number of turns N is count (indicator _ space)/2+1, and indicator _ space is a side length within an inductor pitch of the inductor layout.
6. The method as claimed in claim 5, wherein the edge length indicator _ space within the inductor pitch of the inductor layout is calculated by using index _ sp _ EXTind _ mt ═ Xregion, and X is the maximum inductor pitch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711392318.9A CN108133101B (en) | 2017-12-21 | 2017-12-21 | Auxiliary layer of inductor layout and method for extracting device parameters |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711392318.9A CN108133101B (en) | 2017-12-21 | 2017-12-21 | Auxiliary layer of inductor layout and method for extracting device parameters |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108133101A CN108133101A (en) | 2018-06-08 |
| CN108133101B true CN108133101B (en) | 2021-09-24 |
Family
ID=62391145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711392318.9A Active CN108133101B (en) | 2017-12-21 | 2017-12-21 | Auxiliary layer of inductor layout and method for extracting device parameters |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108133101B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108829995B (en) * | 2018-06-25 | 2022-06-14 | 上海华力集成电路制造有限公司 | Integrated circuit inductance device type identification auxiliary layer and inductance device type identification method |
| CN109308374B (en) * | 2018-08-15 | 2023-06-13 | 上海华力集成电路制造有限公司 | Layout parameter extraction method for polygonal spiral inductance device |
| CN112069750A (en) * | 2020-08-14 | 2020-12-11 | 上海华虹宏力半导体制造有限公司 | Layout verification method, device, equipment and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101345242A (en) * | 2003-08-22 | 2009-01-14 | 艾格瑞系统有限公司 | A spiral inductor formed in a semiconductor substrate and a method for forming the inductor |
| CN102622481A (en) * | 2012-03-06 | 2012-08-01 | 中国航天科技集团公司第九研究院第七七一研究所 | Method for designing complementary data redundancy structure type CMOS (Complementary Metal Oxide Semiconductor) standard cell circuit physical library model |
| EP2662873A2 (en) * | 2012-05-08 | 2013-11-13 | Samsung Electro-Mechanics Co., Ltd. | Method of manufacturing coil element and coil element |
| CN105226012A (en) * | 2015-09-12 | 2016-01-06 | 上海华虹宏力半导体制造有限公司 | The extracting method of MOM capacitor |
| CN107425070A (en) * | 2017-07-27 | 2017-12-01 | 电子科技大学 | A kind of half super node MOSFET with assisted oxidation buried regions |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7243321B2 (en) * | 2004-04-07 | 2007-07-10 | Cadence Design Systems, Inc. | IC layout physical verification method |
| CN102402630A (en) * | 2010-09-10 | 2012-04-04 | 北京华大九天软件有限公司 | Method for identifying graphic connection relationship between units in hierarchical layout verification |
| CN103164566A (en) * | 2012-12-04 | 2013-06-19 | 天津蓝海微科技有限公司 | Vector testing auxiliary layer generating method of territory validation rule |
| CN107195563B (en) * | 2017-05-23 | 2020-04-10 | 上海华虹宏力半导体制造有限公司 | Method for extracting parasitic RC network |
-
2017
- 2017-12-21 CN CN201711392318.9A patent/CN108133101B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101345242A (en) * | 2003-08-22 | 2009-01-14 | 艾格瑞系统有限公司 | A spiral inductor formed in a semiconductor substrate and a method for forming the inductor |
| CN102622481A (en) * | 2012-03-06 | 2012-08-01 | 中国航天科技集团公司第九研究院第七七一研究所 | Method for designing complementary data redundancy structure type CMOS (Complementary Metal Oxide Semiconductor) standard cell circuit physical library model |
| EP2662873A2 (en) * | 2012-05-08 | 2013-11-13 | Samsung Electro-Mechanics Co., Ltd. | Method of manufacturing coil element and coil element |
| CN105226012A (en) * | 2015-09-12 | 2016-01-06 | 上海华虹宏力半导体制造有限公司 | The extracting method of MOM capacitor |
| CN107425070A (en) * | 2017-07-27 | 2017-12-01 | 电子科技大学 | A kind of half super node MOSFET with assisted oxidation buried regions |
Non-Patent Citations (1)
| Title |
|---|
| 基于CMOS工艺的抗辐射加固光电探测芯片设计;万宵鹏;《中国优秀硕士学位论文全文数据库 信息科技辑》;20160315(第3期);I135-822 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108133101A (en) | 2018-06-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108133101B (en) | Auxiliary layer of inductor layout and method for extracting device parameters | |
| US8863051B2 (en) | Hierarchical feature extraction for electrical interaction calculations | |
| WO2012015708A1 (en) | Method, apparatus, and article of manufacture for providing in situ, customizable information in designing electronic circuits with electrical awareness | |
| US8898039B1 (en) | Physical topology-driven logical design flow | |
| CN101604419A (en) | A kind of construction project is intended the method that addressing is extracted automatically | |
| JP2018005436A (en) | Circuit design device and circuit design method using the same | |
| US7149989B2 (en) | Method of early physical design validation and identification of texted metal short circuits in an integrated circuit design | |
| US7243321B2 (en) | IC layout physical verification method | |
| CN103903618A (en) | Voice input method and electronic device | |
| CN102663161B (en) | Radio-frequency integrated-circuit triangular mesh generation method | |
| JP2002042148A (en) | Data allocation method and two-dimensional drawing data processing system | |
| CN102483744A (en) | Method, system, and apparatus for searching an electronic document collection | |
| CN109858155B (en) | Simulation method and related device | |
| US7853442B2 (en) | Printed circuit board design instruction support method and device | |
| US20180203952A1 (en) | Non-transitory computer-readable recording medium recording detour wiring check program, detour wiring check method, and information processing apparatus | |
| CN108829995B (en) | Integrated circuit inductance device type identification auxiliary layer and inductance device type identification method | |
| CN109271676A (en) | A kind of detection method and device of zero restricted area of PCB design figure | |
| US20110061031A1 (en) | Method for producing layout of semiconductor integrated circuit with radio frequency devices | |
| US7110933B2 (en) | Line modeling tool | |
| JP6884071B2 (en) | Design support device and design support method | |
| CN101604342B (en) | Method and device for making metal oxide semiconductor (MOS) transistor on integrated circuit simulating platform | |
| CN109308374B (en) | Layout parameter extraction method for polygonal spiral inductance device | |
| US20060090144A1 (en) | Method of automating place and route corrections for an integrated circuit design from physical design validation | |
| JP6435706B2 (en) | Circuit board model generator | |
| US20120233581A1 (en) | Design support apparatus for semiconductor device, design support program, and layout information generating method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |