CN105226012A - The extracting method of MOM capacitor - Google Patents
The extracting method of MOM capacitor Download PDFInfo
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- CN105226012A CN105226012A CN201510579388.XA CN201510579388A CN105226012A CN 105226012 A CN105226012 A CN 105226012A CN 201510579388 A CN201510579388 A CN 201510579388A CN 105226012 A CN105226012 A CN 105226012A
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
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Abstract
The invention provides a kind of extracting method of MOM capacitor, first from integrated circuit diagram, identify MOM capacitor region, then the direct region linked together by the lamination metal of MOM capacitor is as the electrode pin of MOM capacitor, this electrode pin structure contains all outside connection possibility of MOM capacitor, then set up in electrode pin periphery the virtual enclosure wall district surrounding MOM capacitor, the annexation of MOM capacitor and its aerial lug is correctly set up by virtual enclosure wall district, thus correctly can check the connection performance of the MOM capacitor structure likely combined, avoid traversal the trouble of likely combination stack metal structure, improve the extraction rate of MOM capacitor structure, avoid the wafer of production annexation mistake in art production process simultaneously and cause waste paper.
Description
Technical field
The present invention relates to integrated circuit (IC) design field, particularly relate to a kind of extracting method of MOM capacitor.
Background technology
Capacitor is the important composition unit in integrated circuit (being called for short IC), is widely used in the chips such as memory, microwave, radio frequency, smart card and filtering.Along with the continuous progress of semiconductor integrated circuit manufacturing technology, the performance of semiconductor device also constantly promotes.In integrated circuit integrated level lifting process, how highdensity electric capacity is obtained under limited area for capacitor and become an important topic.Existing capacitor generally includes: junction capacitor, gate capacitor, metal-metal (Intra-metal) capacitor etc.Wherein, in the occasion of high capacitance density, the linearity of junction capacitor, gate capacitor and quality factor are all poor, and breakdown potential is forced down, and applicability is not strong; And the linear character of metal-metal (Intra-metal) capacitor will be much better than the capacitor of other types, thus there is better precision, the needs of high capacitance density occasion can better be met.
Above-mentioned metal-metal (Intra-metal) capacitor includes metal-insulator-metal type (metal-insulator-metal, MIM) capacitor and two kinds, metal-oxide-metal (metal-oxide-metal, MOM) capacitor.Wherein, MIM capacitor uses upper/lower layer metallic as capacitor plate, and capacitance determines primarily of capacitor area occupied, therefore, uses MIM capacitor that cost can be caused greatly to increase in the occasion needing bulky capacitor; And the method that MOM capacitor adopts finger and lamination to combine can making capacity is larger on relatively little area electric capacity.
In existing MOM capacitor, metal on same layer be pectination (or claim finger-like, i.e. COMB structure) arrangement, be provided with dielectric between the comb part (or claiming finger portion) of same layer, the combination layer that this metal by arranging in pectination and the dielectric between it form is called metal layer.On same metal layer, two adjacent comb and the dielectric of centre thereof define sub-capacitor, and the total capacitance of every layer equals the summation of the sub-capacitor on this layer.Existing MOM capacitor is generally vertical stack, comprise the multiple metal layers be deposited in together, oxide is between adjacent metallization layer and with the dielectric between layer comb, multilayer MOM capacitor comprises two electrodes, and by via plug (viaplug) structure, two electrodes and all metal layers are linked together, MOM capacitor total capacitance be by the Capacitance parallel connection on multilevel metallization layer after generation, the capacitance obtaining MOM capacitor is added by the capacitance on multilevel metallization layer, MOM capacitor is exactly make use of parasitic capacitance between adjacent metal and upper/lower layer metallic ply area capacitance simultaneously, greatly increase area utilization and capacitance.In the technique of below 0.13um, be less than the thickness of dielectric layer between upper/lower layer metallic with the minimum spacing between layer metal.Therefore, in situation of the same area, the parasitic capacitance between adjacent metal (minimum spacing) is greater than the electric capacity between upper/lower layer metallic ply region.
Usually the auxiliary of EDA (electric design automation) instrument can be relied at present in the back-end physical design of semiconductor integrated circuit; circuit meshwork list (gauze set) is converted to the physical connection (geometric connection) on physical layout; these physical connections are included in the line on same metal level; and the through hole connection etc. of different metal interlayer, and the numerous design rule constraints of demand fulfillment.Design rule fault on domain can make chip cannot tapeout (delivering manufacture), therefore, does not have design rule to break rules to be the basic demand of domain wires design.
But, the laminated metal structure of MOM capacitor, the line realized in integrated circuit diagram on same metal level is made to become very difficult, because the metal level of integrated circuit diagram has multilayer, such as 4 layers, 5 layers, 6 layers, 7 layers etc., and the laminated metal structure of MOM capacitor may be only make use of wherein one deck to be formed, or the two-layer continuously or continuous two-layer above metal that make use of wherein is formed, when the concrete laminated metal structure of uncertain MOM capacitor, aerial lug is connected with MOM capacitor, easily there is connection error, cause waste paper.Metal-layer structure normally according to integrated circuit in prior art, traversal forms likely combining of the laminated metal structure of MOM capacitor by these metal levels, such as, have 7 layers of metal level of M1 to M7 in integrated circuit, the laminated metal structure forming MOM capacitor by it has 28 kinds and may combine:
M1，M1+M2，M1+M2+M3，M1+M2+M3+M4，M1+M2+M3+M4+M5，M1+M2+M3+M4+M5+M6，M1+M2+M3+M4+M5+M6+M7；
M2，M2+M3，M2+M3+M4，M2+M3+M4+M5，M2+M3+M4+M5+M6，M2+M3+M4+M5+M6+M7；
M3，M3+M4，M3+M4+M5，M3+M4+M5+M6，M3+M4+M5+M6+M7；
M4，M4+M5，M4+M5+M6，M4+M5+M6+M7；
M5，M5+M6，M5+M6+M7；
M6，M6+M7；
M7。
Conventional method, when extracting these MOM capacitor, needs extraction 28 times, and to distinguish different MOM capacitor structures, cause extraction rate comparatively slow, consuming time longer, efficiency is lower.
Summary of the invention
The object of the present invention is to provide a kind of extracting method of MOM capacitor, the extraction rate of MOM capacitor can be improved, shorten the integrated circuit (IC) design cycle.
For solving the problem, the present invention proposes a kind of extracting method of MOM capacitor, comprising:
S1, identifies MOM capacitor from integrated circuit diagram, and the lamination metal of described MOM capacitor belongs to the metal wiring layer of integrated circuit diagram;
S2, two regions linked together by the lamination metal of described MOM capacitor are defined as two electrode pins that described MOM capacitor outwards connects, and every layer laminate metal all has one deck auxiliary layer of its correspondence;
S3, at two virtual enclosure wall layers of electrode pin peripheral expansion one, described virtual enclosure wall layer is utilized to set up the annexation of described MOM capacitor and its aerial lug, under described annexation, described aerial lug had both contacted two electrode pins of described MOM capacitor, contact again in described MOM capacitor with the auxiliary layer of aerial lug place metal wiring layer with layer.
Further, in step sl, according to the auxiliary layer in the label layer of described integrated circuit diagram and the device area of label layer mark, from integrated circuit diagram, MOM capacitor is identified.
Further, in step s3, the annexation utilizing described virtual enclosure wall layer to set up described MOM capacitor and its aerial lug comprises:
Utilize described virtual enclosure wall layer to judge whether a metal routing is aerial lug, when metal routing enters the device region of MOM capacitor from virtual enclosure wall outside through virtual enclosure wall, this metal routing is aerial lug;
Judge whether described aerial lug had both contacted two electrode pins of described MOM capacitor in the device region of MOM capacitor, contact again in described MOM capacitor with the auxiliary layer of aerial lug place metal wiring layer with layer, if, then described outside cabling is the line of MOM capacitor for outwards connecting, described aerial lug contact in two electrode pins of described MOM capacitor with the lamination metal of aerial lug place metal wiring layer with layer.
Further, the extracting method of described MOM capacitor also comprises: S4, extract the metal level information of described MOM capacitor according to the inner label of integrated circuit diagram, with the correctness of the annexation set up in verification step S3, thus complete the extraction of MOM capacitor.
Further, in step sl, from integrated circuit diagram, once identify all MOM capacitor, and the process of step S2 and S3 is carried out to each MOM capacitor.
Further, in step s 4 which, the metal level information of all MOM capacitor is extracted according to the inner label of integrated circuit diagram, in verification step S3 to be the correctness of the annexation that each MOM capacitor is set up.
Further, have three layers in described integrated circuit diagram above metal wiring layer, the laminated metal structure of the MOM capacitor in described integrated circuit diagram be likely combined as n* (n+1)/2 kind, n is the metal wiring layer number of plies of integrated circuit diagram.
Further, have M1 to M7 totally 7 layers of metal wiring layer in described integrated circuit diagram, the laminated metal structure identifying each MOM capacitor in described integrated circuit diagram is respectively the one in following 28 kinds of combinations:
M1，M1+M2，M1+M2+M3，M1+M2+M3+M4，M1+M2+M3+M4+M5，M1+M2+M3+M4+M5+M6，M1+M2+M3+M4+M5+M6+M7，
M2，M2+M3，M2+M3+M4，M2+M3+M4+M5，M2+M3+M4+M5+M6，M2+M3+M4+M5+M6+M7，
M3，M3+M4，M3+M4+M5，M3+M4+M5+M6，M3+M4+M5+M6+M7，
M4，M4+M5，M4+M5+M6，M4+M5+M6+M7，
M5，M5+M6，M5+M6+M7，
M6，M6+M7，
M7。
Further, have M1 to M6 totally 6 layers of metal wiring layer in described integrated circuit diagram, the laminated metal structure identifying each MOM capacitor in described integrated circuit diagram is respectively the one in following 21 kinds of combinations:
M1，M1+M2，M1+M2+M3，M1+M2+M3+M4，M1+M2+M3+M4+M5，M1+M2+M3+M4+M5+M6，
M2，M2+M3，M2+M3+M4，M2+M3+M4+M5，M2+M3+M4+M5+M6，
M3，M3+M4，M3+M4+M5，M3+M4+M5+M6，
M4，M4+M5，M4+M5+M6，
M5，M5+M6，
M6。
Further, the live width of described virtual enclosure wall layer is more than or equal to the minimum widith of specifying in the design rule of integrated circuit diagram.
Compared with prior art, the extracting method of MOM capacitor provided by the invention, first from integrated circuit diagram, identify MOM capacitor region, then the direct region linked together by the lamination metal of MOM capacitor is as the electrode pin of MOM capacitor, this electrode pin structure contains all outside connection possibility of MOM capacitor, then set up in electrode pin periphery the virtual enclosure wall district surrounding MOM capacitor, the annexation of MOM capacitor and its aerial lug is correctly set up by virtual enclosure wall district, thus correctly can check the connection performance of the MOM capacitor structure likely combined, avoid traversal the trouble of likely combination stack metal structure, improve the extraction rate of MOM capacitor structure, shorten the integrated circuit (IC) design cycle, avoid the wafer of production annexation mistake in art production process simultaneously and cause waste paper.
Accompanying drawing explanation
Fig. 1 is the flow chart of the extracting method of the MOM capacitor of the specific embodiment of the invention;
Fig. 2 is the domain structure schematic diagram of the MOM capacitor of the specific embodiment of the invention.
Embodiment
For making object of the present invention, feature becomes apparent, and be further described, but the present invention can realize by different forms, should just not be confined to described embodiment below in conjunction with accompanying drawing to the specific embodiment of the present invention.
Please refer to Fig. 1, the invention provides a kind of extracting method of MOM capacitor, comprising:
S1, identifies MOM capacitor from integrated circuit diagram;
S2, two regions linked together by the lamination metal of described MOM capacitor are defined as two electrode pins that described MOM capacitor outwards connects, and every layer laminate metal all has one deck auxiliary layer of its correspondence;
S3, at two virtual enclosure wall layers of electrode pin peripheral expansion one, described virtual enclosure wall layer is utilized to set up the annexation of described MOM capacitor and its aerial lug, under described annexation, described aerial lug had both contacted two electrode pins of described MOM capacitor, contact again in described MOM capacitor with the auxiliary layer of aerial lug place metal level with layer;
S4, extracts the metal level information of described MOM capacitor according to the inner label of integrated circuit diagram, with the correctness of the described annexation set up in verification step S3, thus complete the extraction of described MOM capacitor.
Wherein, described integrated circuit diagram (integratedcircuitlayout) is with the integrated circuit described by the form of X-Y scheme, integrated circuit is made up of multiple physical level usually, these figures represent structure and the line of metal in every one deck, medium, semi-conducting material respectively, and the shape of these figures, size, place layer, position and interconnected relationship just determine the circuit structure of integrated circuit.During IC Layout; the technological standards of the critical size that usual meeting uses required by this integrated circuit; select corresponding hierarchical Design rule, in this hierarchical Design rule, usually can define the numbering of all levels of domain, title, physical meaning and structural information, coordinate information etc.Such as critical size is the technique of 0.13 μm, and the hierarchical Design rule of a certain integrated circuit diagram comprises hundreds of layer: the 1st layer of name is called N-well, represents n trap; 2nd layer of name is called N+diff, represents N-shaped doped region;Generally when IC Layout, the device outer rim of label layer can be provided as in the periphery of each device cell domain, outer rim is only a label layer 10, only be used as the level that a certain device area is identified, on the performance of integrated circuit (IC) chip manufacture process and integrated circuit (IC) chip without any impact, and the setting of label layer also can follow the hierarchical Design rule of integrated circuit diagram, such as device boundaries will conform with the regulations to the distance of label layer.Thus, please refer to Fig. 2, in the step S1 of the present embodiment, can according in integrated circuit diagram for identifying auxiliary layer (metal Shield layer corresponding to metal wiring layer in the label layer 10 of MOM capacitor and label layer 10 region, wherein, if total n layer metal wiring layer in integrated circuit diagram, n is greater than 3, such as 4, 5, 6, 7 etc., then in its design rule, definable ground floor is respectively M1 to n-th layer metal wiring layer, M2, ., Mn, the auxiliary layer that each layer laminate metal pair that may exist in MOM capacitor is answered is M1_S, M2_S, ., Mn_S), MOM capacitor 11 is identified from integrated circuit diagram, namely the domain (or claiming device area) of MOM capacitor is identified.In this step, disposablely can identify all MOM capacitor from integrated circuit diagram, also only can carry out MOM capacitor identification to the appointed area in integrated circuit diagram.If total n layer metal wiring layer in integrated circuit diagram, what then therefrom identify the lamination metal of MOM capacitor has likely combined n* (n+1)/2 kind, such as when this integrated circuit diagram have M1 to M7 totally 7 layers of metal wiring layer time, the lamination metal of the MOM capacitor arranged in this integrated circuit diagram may be any one in following 28 kinds of combinations:
M1，M1+M2，M1+M2+M3，M1+M2+M3+M4，M1+M2+M3+M4+M5，M1+M2+M3+M4+M5+M6，M1+M2+M3+M4+M5+M6+M7；
M2，M2+M3，M2+M3+M4，M2+M3+M4+M5，M2+M3+M4+M5+M6，M2+M3+M4+M5+M6+M7；
M3，M3+M4，M3+M4+M5，M3+M4+M5+M6，M3+M4+M5+M6+M7；
M4，M4+M5，M4+M5+M6，M4+M5+M6+M7；
M5，M5+M6，M5+M6+M7；
M6，M6+M7；
M7。
Such as when this integrated circuit diagram have M1 to M6 totally 6 layers of metal wiring layer time, the lamination metal of the MOM capacitor arranged in this integrated circuit diagram may be any one in following 21 kinds of combinations:
M1，M1+M2，M1+M2+M3，M1+M2+M3+M4，M1+M2+M3+M4+M5，M1+M2+M3+M4+M5+M6，
M2，M2+M3，M2+M3+M4，M2+M3+M4+M5，M2+M3+M4+M5+M6，
M3，M3+M4，M3+M4+M5，M3+M4+M5+M6，
M4，M4+M5，M4+M5+M6，
M5，M5+M6，
M6。
Therefore, need the process each MOM capacitor being carried out to step S2 to S4, correctly check the connection performance of the MOM capacitor likely combined, set up the exact connect ion relation of the MOM capacitor all metal line layer lines corresponding with its lamination metal, the metal line exact connect ion in each lamination metal namely the most at last in MOM capacitor electrode pin and integrated circuit diagram in respective metal wiring layer.
Please continue to refer to Fig. 2, every layer of metal of the lamination metal of MOM capacitor is generally in the structure that two pectinate textures are staggered, comb part is for generation of electric capacity, two comb ridge parts are connected with the lamination metal of other layers, and the comb ridge part of the lamination metal of final MOM capacitor all links together in two regions (the moulding region of the center vertical bar region that the oblique line in Fig. 2 is filled and border half opening), therefore, in step s 2, based on the design feature of MOM capacitor, interconnective for lamination metal comb ridge region is defined as two electrode pins (Pin) 12 of MOM capacitor, wherein, Fig. 2 be positioned at MOM capacitor zone line and the vertical oblique line bar be connected with a part of comb of MOM capacitor as an electrode pin, be positioned at MOM capacitor edge surrounding and the oblique line bar frame be connected with another part comb of MOM capacitor as another electrode pin, two electrode pins all contain all lamination metal information of MOM capacitor, thus can the possibility of all outside connection of all standing MOM capacitor.And when defining PIN in conventional art, usually define with the metal wiring layer in label layer region, but need like this to define repeatedly MOM capacitor, could exhaustive complete likely situation, the inspection operand of the annexation of the MOM capacitor in subsequent step is large, checks that speed is slower.Define lamination metal interconnective comb ridge region in obvious step S2 of the present invention and make electrode pin Pin, can by the contact (or be connected) of the aerial lug in subsequent step with a kind of mode of electrode pin, just can contain the connection possibility of all lamination metals, thus greatly improve inspection speed and the efficiency of the annexation of MOM capacitor in subsequent step S3, shorten the integrated circuit (IC) design cycle.
Please continue to refer to Fig. 2, in the step S3 of the present embodiment, first there is in the peripheral expansion of electrode pin 12 the virtual enclosure wall layer 14 of certain live width, the live width of described virtual enclosure wall layer 14 can be more than or equal to the minimum widith of specifying in the design rule of integrated circuit diagram, and virtual enclosure wall layer 14 directly can contact two electrode pins 12 simultaneously.Utilize this virtual enclosure wall layer 14 can in the region of MOM capacitor and the metal line of periphery be whether outside company, namely MOM capacitor metal line within and outside the region is distinguished, the metal line entering MOM capacitor region from outside through virtual enclosure wall layer 14 is aerial lug 13, and the metal being positioned at virtual enclosure wall region completely may be the lamination metal of MOM capacitor; Then by judging whether be positioned at each layer aerial lug 13 (i.e. each layer metal line of integrated circuit) entering MOM capacitor region from outside through virtual enclosure wall region had both contacted with electrode pin 12, contact with the auxiliary layer corresponding with the metal wiring layer at aerial lug place of MOM capacitor inside again, judge whether aerial lug is the aerial lug of MOM capacitor for outwards connecting, if so, the corresponding lamination metal then in MOM capacitor electrode pin 12 and described aerial lug 13 establish correct annexation.Such as, when checking the connection possibility of MOM capacitor and metal line M1, near the device area that M1 is positioned at MOM capacitor or the metal line M1 passed from MOM capacitor device region, first, distinguish whether M1 is outside virtual enclosure wall layer enclosing region, when M1 is positioned within virtual enclosure wall layer enclosing region completely, M1 is very likely the one deck in the lamination metal of MOM capacitor, when M1 arrives MOM capacitor through virtual enclosure wall layer outside virtual enclosure wall layer enclosing region, this M1 should be the aerial lug connected for device; Then, judge whether both contacted auxiliary layer M1_S corresponding to the metal wiring layer M1 of MOM capacitor as the M1 of aerial lug, contact electrode pin 12 again simultaneously, when all contacting, can think that the M1 as aerial lug is the aerial lug of MOM capacitor for outwards connecting, not other cablings irrelevant with MOM capacitor, now, this outside cabling M1 can establish a connection with the lamination metal M1 in the electrode pin 12 of MOM capacitor, and simultaneously we can know in the laminated metal structure of MOM capacitor and comprise M1 layer.When therefore setting up the annexation of MOM capacitor electrode pin 12 to the corresponding metal wiring layer in integrated circuit diagram, this metal wiring layer must meet two conditions: 1. contact or through virtual enclosure wall layer, namely contacts with electrode pin 12; 2. the metal auxiliary layer M1_S/M2_S corresponding with MOM capacitor ... contact), correctly checked the connection performance likely combining MOM capacitor in integrated circuit diagram thus, avoid the wafer W afer of production annexation mistake in integrated circuit technology production process, and cause waste paper.
In step s 4 which, the metal hierarchical information of each MOM capacitor is extracted further according to the inner label (Lable) of integrated circuit diagram, described metal hierarchical information is compared with the annexation of the MOM capacitor confirmed in step S3, with the annexation set up in determining step S3 is correct, such as: the metal hierarchical information of the MOM capacitor extracted: PropertyMetal=1111111, represent that this capacitor M1 ~ M7 contains, if the aerial lug of any layer or multilayer and the annexation of MOM capacitor in M1 to M7 can be set up in step S3, as long as this aerial lug can contact with two electrode pins, the auxiliary layer (the auxiliary layer Mi_S that namely Mi is corresponding) of MOM capacitor that again can be corresponding with the metal wiring layer at this aerial lug place (being defined as Mi) contacts, the annexation formed thus is all correct, the metal hierarchical information of another MOM capacitor extracted: PropertyMetal=0100000, represent this capacitor only containing M2, only there is the metal line on metal wiring layer M2 can establish a connection with MOM capacitor in this integrated circuit diagram, not only aerial lug M2 can contact with two of a MOM capacitor electrode pin, but also can be corresponding with the M2 in MOM capacitor auxiliary layer M2_S) contact, the annexation of remaining and MOM capacitor is all wrong.Again check the annexation of all MOM capacitor in integrated circuit diagram thus, complete the extraction work of the MOM capacitor in integrated circuit diagram, avoid the wafer W afer of production annexation mistake in integrated circuit technology production process, and cause waste paper.
In sum, the extracting method of MOM capacitor provided by the invention, first from integrated circuit diagram, identify MOM capacitor region, then the direct region linked together by the lamination metal of MOM capacitor is as the electrode pin of MOM capacitor, this electrode pin structure contains all outside connection possibility of MOM capacitor, then set up in electrode pin periphery the virtual enclosure wall district surrounding MOM capacitor, the annexation of MOM capacitor and its aerial lug is correctly set up by virtual enclosure wall district, thus correctly can check the connection performance of the MOM capacitor structure likely combined, avoid traversal the trouble of likely combination stack metal structure, improve the extraction rate of MOM capacitor structure, shorten the integrated circuit (IC) design cycle, avoid the wafer of production annexation mistake in art production process simultaneously and cause waste paper.
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. an extracting method for MOM capacitor, is characterized in that, comprising:
S1, identifies MOM capacitor from integrated circuit diagram, and the lamination metal of described MOM capacitor belongs to the metal wiring layer of integrated circuit diagram;
S2, two regions linked together by the lamination metal of described MOM capacitor are defined as two electrode pins that described MOM capacitor outwards connects, and every layer laminate metal all has one deck auxiliary layer of its correspondence;
S3, at two virtual enclosure wall layers of electrode pin peripheral expansion one, described virtual enclosure wall layer is utilized to set up the annexation of described MOM capacitor and its aerial lug, under described annexation, described aerial lug had both contacted two electrode pins of described MOM capacitor, contact again in described MOM capacitor with the auxiliary layer of aerial lug place metal wiring layer with layer.
2. the extracting method of MOM capacitor as claimed in claim 1, is characterized in that, in step sl, according to the auxiliary layer in the label layer of described integrated circuit diagram and the device area of label layer mark, from integrated circuit diagram, identifies MOM capacitor.
3. the extracting method of MOM capacitor as claimed in claim 1, it is characterized in that, in step s3, the annexation utilizing described virtual enclosure wall layer to set up described MOM capacitor and its aerial lug comprises:
Utilize described virtual enclosure wall layer to judge whether a metal routing is aerial lug, when metal routing enters the device region of MOM capacitor from virtual enclosure wall outside through virtual enclosure wall, this metal routing is aerial lug;
Judge whether described aerial lug had both contacted two electrode pins of described MOM capacitor in the device region of MOM capacitor, contact again in described MOM capacitor with the auxiliary layer of aerial lug place metal wiring layer with layer, if, then described outside cabling is the line of MOM capacitor for outwards connecting, described aerial lug contact in two electrode pins of described MOM capacitor with the lamination metal of aerial lug place metal wiring layer with layer.
4. the extracting method of MOM capacitor as claimed in claim 1, it is characterized in that, also comprise: S4, the metal level information of described MOM capacitor is extracted according to the inner label of integrated circuit diagram, with the correctness of the annexation set up in verification step S3, thus complete the extraction of MOM capacitor.
5. the extracting method of MOM capacitor as claimed in claim 2, is characterized in that, in step sl, from integrated circuit diagram, once identify all MOM capacitor, and carry out the process of step S2 and S3 to each MOM capacitor.
6. the extracting method of MOM capacitor as claimed in claim 5, it is characterized in that, in step s 4 which, extract the metal level information of all MOM capacitor according to the inner label of integrated circuit diagram, in verification step S3 to be the correctness of the annexation that each MOM capacitor is set up.
7. the extracting method of MOM capacitor as claimed in claim 1, it is characterized in that, have three layers in described integrated circuit diagram above metal wiring layer, the laminated metal structure of the MOM capacitor in described integrated circuit diagram be likely combined as n* (n+1)/2 kind, n is the metal wiring layer number of plies of integrated circuit diagram.
8. the extracting method of MOM capacitor as claimed in claim 7, it is characterized in that, have M1 to M7 totally 7 layers of metal wiring layer in described integrated circuit diagram, the laminated metal structure identifying each MOM capacitor in described integrated circuit diagram is respectively the one in following 28 kinds of combinations:
M1，M1+M2，M1+M2+M3，M1+M2+M3+M4，M1+M2+M3+M4+M5，M1+M2+M3+M4+M5+M6，M1+M2+M3+M4+M5+M6+M7，
M2，M2+M3，M2+M3+M4，M2+M3+M4+M5，M2+M3+M4+M5+M6，M2+M3+M4+M5+M6+M7，
M3，M3+M4，M3+M4+M5，M3+M4+M5+M6，M3+M4+M5+M6+M7，
M4，M4+M5，M4+M5+M6，M4+M5+M6+M7，
M5，M5+M6，M5+M6+M7，
M6，M6+M7，
M7。
9. the extracting method of MOM capacitor as claimed in claim 7, it is characterized in that, have M1 to M6 totally 6 layers of metal wiring layer in described integrated circuit diagram, the laminated metal structure identifying each MOM capacitor in described integrated circuit diagram is respectively the one in following 21 kinds of combinations:
M1，M1+M2，M1+M2+M3，M1+M2+M3+M4，M1+M2+M3+M4+M5，M1+M2+M3+M4+M5+M6，
M2，M2+M3，M2+M3+M4，M2+M3+M4+M5，M2+M3+M4+M5+M6，
M3，M3+M4，M3+M4+M5，M3+M4+M5+M6，
M4，M4+M5，M4+M5+M6，
M5，M5+M6，
M6。
10. the extracting method of MOM capacitor as claimed in claim 1, it is characterized in that, the live width of described virtual enclosure wall layer is more than or equal to the minimum widith of specifying in the design rule of integrated circuit diagram.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN107785363A (en) * | 2016-08-30 | 2018-03-09 | 无锡华润上华科技有限公司 | A kind of MOM capacitor domain and its construction unit, modeling method |
| CN107785363B (en) * | 2016-08-30 | 2020-11-10 | 无锡华润上华科技有限公司 | MOM (metal oxide semiconductor) capacitor layout, structure unit and modeling method thereof |
| CN106682331A (en) * | 2016-12-30 | 2017-05-17 | 北京厚德微电技术有限公司 | Extraction of static protection structure of integrated circuit layout and intelligent design verifying method |
| CN106934122A (en) * | 2016-12-30 | 2017-07-07 | 北京华大九天软件有限公司 | A kind of method for accelerating conductor fig annexation in generation domain |
| CN106934122B (en) * | 2016-12-30 | 2020-01-14 | 北京华大九天软件有限公司 | Method for accelerating generation of conductor graph connection relation in layout |
| CN107368635A (en) * | 2017-07-05 | 2017-11-21 | 上海华虹宏力半导体制造有限公司 | The method for detecting low pressure well region and high-pressure trap area hybrid junction |
| CN107368635B (en) * | 2017-07-05 | 2021-07-02 | 上海华虹宏力半导体制造有限公司 | Method for detecting mixed connection of low-voltage well region and high-voltage well region |
| CN108133101A (en) * | 2017-12-21 | 2018-06-08 | 上海华力微电子有限公司 | A kind of method that the auxiliary layer and device parameters of inductance domain extract |
| CN108133101B (en) * | 2017-12-21 | 2021-09-24 | 上海华力微电子有限公司 | Auxiliary layer of inductor layout and method for extracting device parameters |
| CN110162913A (en) * | 2019-05-30 | 2019-08-23 | 上海华虹宏力半导体制造有限公司 | A kind of capacitor layout design method |
| WO2022110114A1 (en) * | 2020-11-30 | 2022-06-02 | 华为技术有限公司 | Circuit layout identification method and identification device |
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