CN107368635B - Method for detecting mixed connection of low-voltage well region and high-voltage well region - Google Patents
Method for detecting mixed connection of low-voltage well region and high-voltage well region Download PDFInfo
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- CN107368635B CN107368635B CN201710543028.3A CN201710543028A CN107368635B CN 107368635 B CN107368635 B CN 107368635B CN 201710543028 A CN201710543028 A CN 201710543028A CN 107368635 B CN107368635 B CN 107368635B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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Abstract
The invention provides a method for detecting the mixed connection of a low-voltage well region and a high-voltage well region, which comprises the following steps: obtaining a circuit layout, wherein the circuit layout is provided with a low-voltage well region and a high-voltage well region; judging whether a device is arranged in the low-voltage well region or not; and when no device exists in the low-voltage well region, detecting whether the metal interconnection line on the low-voltage well region is electrically connected with the metal interconnection line on the high-voltage well region, and if the metal interconnection lines on the same layer are electrically connected, carrying out mixed connection on the low-voltage well region and the high-voltage well region. According to the invention, when the low-voltage well region is provided with a device, whether the low-voltage well region and the high-voltage well region are in mixed connection or not can be directly detected through circuit check, and when the low-voltage well region is not provided with the device, the connection error between the low-voltage well region and the high-voltage well region is detected by judging the connection of the metal interconnection wires, so that the risk of chip failure is avoided.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a method for detecting mixed connection of a low-voltage well region and a high-voltage well region.
Background
Electronic Design Automation (EDA) means the use of computers to Design and simulate the performance of Electronic circuits on integrated circuits, and EDA has evolved to handle the demanding and complex semiconductor integrated circuit Design work. After an integrated circuit has been designed and physically laid out, tests are required to verify that the integrated circuit is functioning properly. In the existing integrated circuit design, the connection relationship among the circuit components can be detected through the EDA.
In the manufacturing process of the device, the layout design is carried out on the device, the process manufacturing is carried out according to the layout, in the process manufacturing process, due to the deviation of various process equipment and process conditions and the like, the structure of the device and the layout design come in and go out, for example, in the manufacturing process of connecting the well region and the back section, the problem that the low-voltage well region is mixed with the high potential of the high-voltage well region occurs, and the device breakdown and the like are caused.
Disclosure of Invention
The invention aims to provide a method for detecting the mixed connection of a low-voltage well region and a high-voltage well region, and solves the technical problem that the low-voltage well region and the high-voltage well region cannot be detected in the prior art.
In order to solve the above technical problem, the present invention provides a method for detecting the mixed junction of a low voltage well region and a high voltage well region, comprising:
obtaining a circuit layout, wherein the circuit layout is provided with a low-voltage well region and a high-voltage well region;
judging whether a device is arranged in the low-voltage well region or not;
and when no device exists in the low-voltage well region, detecting whether the metal interconnection line on the low-voltage well region is electrically connected with the metal interconnection line on the high-voltage well region, and if the metal interconnection lines on the same layer are electrically connected, carrying out mixed connection on the low-voltage well region and the high-voltage well region.
Optionally, the low-voltage well region is an N-type well region.
Optionally, the high voltage well region is an N-type well region.
Optionally, the hvw region and the hvw region are adjacent to each other and physically separated.
Optionally, when determining whether a device is in the low-voltage well region, if an active region in the low-voltage well region overlaps with the polysilicon, the low-voltage well region has the device; if the active region in the low-voltage well region does not overlap with the polysilicon, the low-voltage well region does not have a device.
Optionally, when the low-voltage well region has a device therein, the current of the circuit layout is simulated, and when the current is greater than the standard current, the low-voltage well region and the high-voltage well region are in mixed connection.
Optionally, a PMOS transistor is disposed in the low-voltage well region, and the low-voltage well region serves as a substrate of the PMOS transistor and is connected out.
Optionally, the low-voltage well region is provided with 3-6 layers of metal interconnection lines, and the adjacent metal interconnection lines are electrically connected through the through holes.
Optionally, the high-voltage well region is provided with 3-6 layers of metal interconnection lines, and the adjacent metal interconnection lines are electrically connected through the through holes.
Compared with the prior art, in the method for detecting the mixed connection of the low-voltage well region and the high-voltage well region, when a device is arranged in the low-voltage well region, the current of a circuit layout is simulated, and when the current is larger than the standard current, the low-voltage well region and the high-voltage well region are mixed connected; and when no device exists in the low-voltage well region, detecting whether the metal interconnection line on the low-voltage well region is electrically connected with the metal interconnection line on the high-voltage well region, and if so, carrying out mixed connection on the low-voltage well region and the high-voltage well region. According to the invention, when the low-voltage well region is provided with a device, whether the low-voltage well region and the high-voltage well region are in mixed connection or not can be directly detected through circuit check, and when the low-voltage well region is not provided with the device, the connection error between the low-voltage well region and the high-voltage well region is detected by judging the connection of the metal interconnection wires, so that the risk of chip failure is avoided.
Drawings
FIG. 1 is a flowchart illustrating a method for detecting a cross-connect between a low voltage well and a high voltage well according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a circuit structure of a transistor in the LDW region according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the metal interconnection lines between the LDW region and the HVW region according to an embodiment of the present invention.
Detailed Description
The method of detecting a muddled low-voltage well region and a hvw well region of the present invention will now be described in more detail with reference to the schematic drawings, in which preferred embodiments of the present invention are shown, it being understood that a person skilled in the art may modify the invention described herein while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The core idea of the invention is to provide a method for detecting the mixed connection of a low-voltage well region and a high-voltage well region, when a device is arranged in the low-voltage well region, the current of a circuit layout is simulated, and when the current is larger than the standard current, the low-voltage well region and the high-voltage well region are mixed connected; and when no device exists in the low-voltage well region, detecting whether the metal interconnection line on the low-voltage well region is electrically connected with the metal interconnection line on the high-voltage well region, and if so, carrying out mixed connection on the low-voltage well region and the high-voltage well region. According to the invention, when the low-voltage well region is provided with a device, whether the low-voltage well region and the high-voltage well region are in mixed connection or not can be directly detected through circuit check, and when the low-voltage well region is not provided with the device, the connection error between the low-voltage well region and the high-voltage well region is detected by judging the connection of the metal interconnection wires, so that the risk of chip failure is avoided.
The method for detecting the mixed connection of the low-voltage well region and the high-voltage well region of the invention is specifically described below with reference to the accompanying drawings 1 to 3, fig. 1 is a flow chart of the detection method, fig. 2 to 3 are different detection embodiments of whether the device exists in the low-voltage well region, and the detection method of the invention comprises the following steps:
step S1 is executed to obtain a circuit layout, where the circuit layout has a Low Voltage Well (Low Voltage Well) and a High Voltage Well (High Voltage Well), and in this embodiment, the Low Voltage Well is an N-type Well (Low Voltage N Well, LVNW), and the High Voltage Well is an N-type Well (High Voltage N Well hvnw). Of course, in other embodiments of the present invention, the hvw and hvw regions may also be P-type well regions. The low voltage well region LVNW and the high voltage well region HVNW are adjacent to each other and physically separated from each other, and the low voltage well region LVNW and the high voltage well region HVNW may be separated from each other by a shallow trench isolation structure STI.
Step S2 is executed to determine whether a device is located in the low voltage well region LVNW, and when the LVNW has a device in the low voltage well region, a current of the circuit layout is simulated, and when the current ratio is greater than a standard current, the low voltage well region LVNW is connected to the high voltage well region HVNW. When judging whether a device is arranged in the low-voltage well region, if an active region (ACT) in the low-voltage well region is overlapped with polycrystalline silicon (Poly), the device is arranged in the low-voltage well region; if the active region in the low-voltage well region does not overlap with the polysilicon, the low-voltage well region does not have a device.
In this embodiment, a PMOS transistor is provided in the low-voltage well region LVNW as an example, and as shown in fig. 2, the low-voltage well region LVNW has a PMOS transistor therein, a source of the PMOS transistor is connected to a power source terminal, a drain of the PMOS transistor is connected to a drain of an NMOS transistor, a gate of the PMOS transistor is connected to a gate of the NMOS transistor, a source of the NMOS transistor is connected to a ground terminal, and the low-voltage well region LVNW is connected as a substrate of the PMOS transistor. When the PMOS transistor and the NMOS transistor are simulated, if the source current Id of the PMOS transistor suddenly increases and is larger than the standard current of the PMOS transistor, the substrate of the PMOS transistor is connected with a high potential, that is, the low voltage well region LVNW and the high voltage well region HVNW are connected in a mixed manner. When the low-voltage well region LVNW is provided with a device structure, whether mixed connection exists can be determined directly through current detection of the device, and the method is simple and easy to implement. In addition, when a device exists in the low voltage well region LVNW, whether the low voltage well region LVNW is in hybrid connection with the high voltage well region or not can be determined by comparing the circuit layout with the circuit structure.
Step S3 is executed, when there is no device in the low-voltage well region LVNW, the connection relationship between the metal interconnection line on the low-voltage well region LVNW and the metal interconnection line on the high-voltage well region HVNW is detected, and if there is an overlap between the metal interconnection line on the low-voltage well region LVNW and the same layer of metal interconnection line between the metal interconnection lines on the high-voltage well region HVNW, the low-voltage well region LVNW is connected to the high-voltage well region HVNW. Specifically, referring to fig. 3, the metal interconnection lines on the low-voltage well region LVNW are found out in the circuit layout, where the low-voltage well region LVNW has 3 to 6 layers of metal interconnection lines, for example, five layers of metal interconnection lines including M1, M2, M3, M4, and M5, the metal interconnection lines on each layer are electrically connected through vias MV1, MV2, MV3, and MV4, and the metal interconnection line M1 is connected to an NTAP pad in the substrate through a via CONT. Similarly, metal interconnection lines on the high-voltage well region HVNW are found out in the circuit layout, the high-voltage well region HVNW is provided with 3-6 layers of metal interconnection lines, for example, five layers of metal interconnection lines including M1 ', M2 ', M3 ', M4 ' and M5 ', the metal interconnection lines M1 ', M2 ', M3 ', M4 ' and M5 ' are connected through holes MV1 ', MV2 ', MV3 ' and MV4 ', and the metal interconnection line M1 ' is connected with a bonding pad NTAP ' in the substrate through a through hole CONT ', so that devices in the high-voltage well region HVNW are led out. In the testing process, the top metal interconnection line M5 of the low-voltage well region LVNW is used as one Node1, and the top metal interconnection line M5 ' of the high-voltage well region HVNW is used as the other Node2, as long as there is an overlap of the same layer of metal between the metal interconnection lines M1, M2, M3, M4, M5 and the metal interconnection lines M1 ', M2 ', M3 ', M4 ', M5 ', that is, there is a layer of electrical connection between the metal interconnection lines M1, M2, M3, M4, M5 and the metal interconnection lines M1 ', M2 ', M3 ', M4 ', M5 ', which results in the mixed connection between the low-voltage well region LVNW and the high-voltage well region HVNW, so as to mark the low voltage, and to prompt the modification of the design of the low-voltage well region.
In summary, according to the method for detecting the mixed connection between the low-voltage well region and the high-voltage well region provided by the invention, when a device is arranged in the low-voltage well region, the current of a circuit layout is simulated, and when the current is larger than the standard current, the low-voltage well region and the high-voltage well region are mixed connected; and when no device exists in the low-voltage well region, detecting whether the metal interconnection line on the low-voltage well region is electrically connected with the metal interconnection line on the high-voltage well region, and if so, carrying out mixed connection on the low-voltage well region and the high-voltage well region. According to the invention, when the low-voltage well region is provided with a device, whether the low-voltage well region and the high-voltage well region are in mixed connection or not can be directly detected through circuit check, and when the low-voltage well region is not provided with the device, the connection error between the low-voltage well region and the high-voltage well region is detected by judging the connection of the metal interconnection wires, so that the risk of chip failure is avoided.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (8)
1. A method for detecting the mixed connection of a low-voltage well region and a high-voltage well region is characterized by comprising the following steps:
obtaining a circuit layout, wherein the circuit layout is provided with a low-voltage well region and a high-voltage well region;
judging whether a device is arranged in the low-voltage well region or not;
when no device exists in the low-voltage well region, detecting whether the metal interconnection lines on the low-voltage well region are overlapped with the metal interconnection lines on the high-voltage well region on the same layer, and if the metal interconnection lines on the same layer are overlapped, performing mixed connection on the low-voltage well region and the high-voltage well region;
when the low-voltage well region is provided with a device, the current of the circuit layout is simulated, and when the current is larger than the standard current, the low-voltage well region and the high-voltage well region are in mixed connection.
2. The method of claim 1 wherein the LDW region is an N-type well region.
3. The method of claim 1 wherein the hvw well region is an N-well region.
4. The method of claim 1, wherein the hvw and hvw regions are adjacent to each other and physically separated.
5. The method of claim 1, wherein when determining whether there is a device in the LDW region, if there is an overlap between an active region in the LDW region and polysilicon, there is a device in the LDW region; if the active region in the low-voltage well region does not overlap with the polysilicon, the low-voltage well region does not have a device.
6. The method of claim 1, wherein the LDW region has a PMOS transistor therein and the LDW region is connected as a substrate of the PMOS transistor.
7. The method as claimed in claim 1, wherein the LDW region and the HVW region have 3-6 metal interconnection lines, and adjacent metal interconnection lines are electrically connected through the via hole.
8. The method of claim 1, wherein the hvw well region has 3-6 metal interconnects, and adjacent metal interconnects are electrically connected through vias.
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