CN104573242A - PCB design layout audit system - Google Patents
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Abstract
The invention discloses a PCB design layout audit system, the PCB design layout audit system comprises an automatic DFM audit module and a man-machine interaction audit module; the automatic DFM audit module comprises a line audit module, a via hole audit module, a copper sheet audit module, a silk screen audit module, a solder resist audit module and a steel mesh audit module; the man-machine interaction audit module comprises a netlist audit module, a layout audit module, a signal audit module, a structure IDF output module, a device height reporting module, a locating and wiring related interaction audit module, a silk screen related interaction audit module and a production related interaction audit module. The audit system is the PCB audit tool based on the cadence allegro design platform, the system has ipc interaction communication of the allegro skill program via the windows program, the system integrates the automatic DFM audit function and the man-machine interaction audit function for having audit on the design result of PCB conveniently, the once success rate of the PCB design is raised and the integral development cycle and development cost of the electronic products are shortened.
Description
Technical field
The invention belongs to the PCB design field in electronic product development technique, particularly relate to a kind of PCB design domain auditing system.
Background technology
Existing both at home and abroad have pcb design layout DFM audit facility, is to carry out pcb and design net result by importing odb++ data that pcb design system exports or gerber data third party data and carry out DFM and automatically audit.
There is following shortcoming in above-mentioned audit facility: before examination & verification, Data Preparation is loaded down with trivial details, and the result after examination & verification is also not easily located with pcb design system alternately.The problem of auditing out, after the change of pcb design system, also need to export odb++ data again or gerber data audit confirmation again, so repeatedly repeatedly, Review Cycle is very long.
Summary of the invention
In order to solve the above-mentioned problems in the prior art, the object of this invention is to provide a kind of PCB design domain auditing system, it can be embedded into completely in pcb design system cadence allegro environment and runs, realize seamless function to connect, Yep Checker instrument is used just as use allegro, without the need to exporting third party's data, examination & verification can be started under pcb design environment.Examination & verification problem out, very clear in allegro, and can directly modify, and carry out searching and locating without the need to cross-system.
To achieve these goals, the technical solution used in the present invention is: a kind of PCB design domain auditing system, comprises automatic DFM (Design For Manufacture manufacturability design) auditing module and man-machine interactively auditing module; Described automatic DFM auditing module comprises cabling auditing module, via hole auditing module, copper sheet auditing module, silk-screen auditing module, welding resistance auditing module and steel mesh auditing module; Described man-machine interactively auditing module comprises net table auditing module, layout auditing module, signal auditing module, structure I DF (Intermediate Data Format in the middle of exchange data layout) output module, element height Reports module, placement-and-routing are correlated with mutual auditing module, silk-screen is correlated with mutual auditing module, produce relevant mutual auditing module.
Preferred technical scheme, when carrying out described automatic DFM auditing module examination & verification, windows program is according to the examination & verification classification chosen and the audit point needed, the demand of allegro skill program audit is informed by ipc communication, then examination & verification is completed by the allegro skill program audit point program calling each auditing module one by one, and form auditing result and auditing statements, finally by ipc communication (communication between Interprocess Communication process), auditing result is fed back to windows program, complete selected all examination & verification demands, when carrying out the examination & verification of described man-machine interactively, windows program informs the demand of allegro skill program audit by ipc communication according to the mutual audit point chosen, then the mutual review procedure that allegro skill routine call is corresponding is allowed, complete man-machine interactively examination & verification, finally by ipc communication, auditing result is fed back to windows program.
Further preferred technical scheme, whether described automatic DFM auditing module comprises decoupling capacitance and to punch nearby auditing module.
Further optimal technical scheme, first described automatic DFM auditing module determines whether moves back even electric capacity; Then search in electric capacity pin peripheral extent and whether have the via hole the same with electric capacity pin network, if there is via hole, just judge to punch nearby; If there is no via hole, just judges not punch nearby.
Further preferred version again, described automatic DFM auditing module comprises automatic search and identifies electric power network module.
Described automatic DFM auditing module comprises automatic search and identifies clock network module.
Described automatic DFM auditing module comprises automatic search and recognition differential subnetwork module.
Described automatic DFM auditing module comprises audits each layer cabling of electric power network automatically whether all by overstriking module.
The net table auditing module of man-machine interactively auditing module comprises the single-ended interconnection network module of searching in net table, check two pin devices whether short circuit module, check whether two pin devices exist and leak network connecting module, check whether three pin devices exist and leak network connecting module, judge whether the device of identical value value has same package title module, check whether non-metallic hole is connected with mixed-media network modules mixed-media, check whether that existence is only connected to the module of the network of electric capacity.
Described PCB design version auditing system is provided with non-mode shortcut command.
Adopt above technical scheme, the present invention has following beneficial effect:
1. auditing system of the present invention is the PCB audit facility based on cadence allegro design platform, and system passes through the ipc interactive communication of windows program and allegro skill program, realizes each side audit function to allegro pcb design result.All functions are integrated in allegro environment simultaneously, improve the review operations of system.This PCB design version auditing system is integrated with the function of automatic DFM audit function and man-machine interactively examination & verification.Greatly facilitate the examination & verification of the design result to PCB, improve the one-time success rate of PCB design, shorten R&D cycle and the R & D Cost of electronic product entirety.
2. audit facility of the present invention provide not only the automatic audit function of DFM, corresponding audit function is provided to each stage of pcb design, include principle diagram design complete after the examination & verification of net table, layout examination & verification after pcb layout completes, and the function of the examination & verification of man-machine interactively is flexibly provided.
3. auditing system of the present invention can be embedded into completely in pcb design software cadence allegro environment and runs, and realizes seamless function and connects.Yep Checker instrument is used just as use allegro.Without the need to exporting third party's data, examination & verification can be started under pcb design environment.Examination & verification problem out, very clear in allegro, and can directly modify, and without the need to carrying out searching and locating across software.
4. the audit function modular program that audit facility of the present invention is all is by allegro skill language compilation, can directly run under the pcb design environment of allegro, avoid external similar examination & verification software to need to carry out examination & verification situation by third party odb++ data or gerber data, simplify the flow process of examination & verification, accelerate the progress of examination & verification.
5. the expansion that the audit point of auditing system of the present invention can be unlimited, is not limited only to the function that external similar examination & verification software DFM audits, can also relates to the examination & verification in each stage of PCB design, substantially increase review efficiency, realizes zero-waiting examination & verification.
Accompanying drawing explanation
Fig. 1 is the workflow schematic diagram of a kind of PCB design domain of the present invention auditing system;
Fig. 2 is the function structure schematic block diagram of a kind of PCB design domain of the present invention auditing system.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with instantiation also with reference to accompanying drawing, the present invention is described in more detail.Should be appreciated that, these describe just exemplary, and do not really want to limit the scope of the invention.In addition, in the following description, the description to known features and technology is eliminated, to avoid unnecessarily obscuring concept of the present invention.
As shown in Figure 1 or 2: a kind of PCB design domain of the present invention auditing system, comprises automatic DFM auditing module and man-machine interactively auditing module; Described automatic DFM auditing module comprises cabling auditing module, via hole auditing module, copper sheet auditing module, silk-screen auditing module, welding resistance auditing module and steel mesh auditing module; Described man-machine interactively auditing module comprises net table auditing module, layout auditing module, signal auditing module, structure I DF output module, element height Reports module, placement-and-routing are correlated with mutual auditing module, silk-screen is correlated with mutual auditing module, produce relevant mutual auditing module.
Above-mentioned auditing system adopts C# language to carry out the exploitation of system interface, by the power of C# language, can develop powerful system interface effectively, fast.The exploitation of audit function module is carried out by cadence skill language, because skill language directly can run under allegro pcb environment, examination just can directly be carried out under pcb design environment, and carry out without the need to exporting third party's data at special examination & verification platform, improve the efficiency of examination & verification greatly.By ipc communication, complete the two-way communication between C# interface program and cadence skill modular program, complete man-machine between perfection mutual.Auditing system of the present invention at present with auditing module have 100 multinomial, can also infinite expanding audit function as required.The function program of bright spot is had to elaborate especially to fraction below:
1, automatic examination & verification decoupling capacitance whether all punching functions nearby:
In PCB design, cabling and punching are carried out in the place of close pad that all needs of decoupling capacitance, to reduce the distributed inductance of decoupling capacitance, ensure the decoupling effect of decoupling capacitance.On auditing system realizes, first need auditing system to need automatically to judge that those devices are electric capacity, and then whether the surrounding of automatically searching electric capacity pin have the via hole with pin identical network.
In system, determine whether decoupling capacitance by method below.
The pin of a, capacitor element should equal 2;
What the pin of b, capacitor element connected should be electric power network;
If the pin of c device be straight cutting pad we straight cutting electric capacity is ignored because straight cutting electric capacity, be do not need punching;
If d user be provided with the checktools of device NODRC attribute we think that he need not check whether this device punches;
It should be noted that, according to algorithm above, the electric capacity found out also may be inductance, magnetic bead, the 0 Europe resistance for power supply bridge joint.According to the algorithm of the 4th, if the punching of the electric capacity found that there is cannot be changed really, or be exactly do not need punching, we just can arrange the NODRC attribute of their checktools.
After finding electric capacity, then search around electric capacity pin in certain limit, whether have the via hole the same with electric capacity pin network.
2, review procedure automatic search identify electric power network:
For one piece of circuit board, the power supply signal on plate, clock signal, differential signal is the vital signal of 3 class.For these signals, we need emphasis to audit.Yep Checker can find these signals fast.
Auditing system judges that a network is electric power network, the principle that Main Basis is following:
If A connect pin count be less than 4 we think that it is not electric power network;
If B connect only have the device number of 2 pin points be less than 2 we think that it is not electric power network;
If the electric capacity quantity of C tie point be less than one we think that it is not electric power network;
If the device of D tie point is all we of 2 pin think that it is not electric power network;
If the network that E connects has been provided with differential nature, so we think that it is not electric power network;
If containing " CLK " printed words, we think that it is not electric power network in the network name that F connects
If G user be provided with the checktools of network NODRC attribute we think that it is not electric power network;
After 7 conditions are as above fallen in screening, remaining network audit system thinks electric power network.
3, review procedure automatic search identify clock network:
When PCB examination & verification, need that examination & verification is carried out to each clock signal and confirm, to confirm that length, the topological structure of clock signal meet design requirement.
Auditing system judges that a network is clock network, the principle that Main Basis is following:
Network name contains CLK;
The NET_SPACING_TYPE attribute of network is CLK;
Clock network crosses the network after resistance, if pin point is less than or equal to 4, also thinks clock network;
4, review procedure automatic search recognition differential subnetwork:
When PCB examination & verification, need that examination & verification is carried out to every a pair differential signal and confirm, to confirm length and the differential lines spacing of differential signal, meet design requirement.
Auditing system judges that a network is differential networks, the principle that Main Basis is following:
The last letter of network name is " P " " N ", "+" "-", " P " " M ";
The NET_SPACING_TYPE attribute of network is DIFF;
The diffpair attribute of network is true;
Differential networks crosses the network after resistance, if pin point is less than or equal to 4, also thinks differential networks;
5, whether each layer cabling of electric power network is automatically audited all by overstriking
Check that whether each layer cabling of electric power network be all by overstriking, under normal circumstances, each layer cabling of power supply, wider than common signal lead live width, meet electric current current-carrying function, by manual examination and verification, examination & verification is not comprehensive usually, and can spend a large amount of audit times.
On auditing system realizes, the first design rule of reading circuit plate, obtains the design live width of normal signal.Then auditing system scans and automatic search each layer of electric power network identified one by one, the live width size of each section of power supply cabling, and and the design lines of normal signal is roomy littlely contrasts.
6, under pcb design environment, the net table for schematic diagram carries out auditing system to be audited automatically
There will be the impalpable minor error of naked eyes in principle diagram design process, under pcb design environment, auditing system is carried out to schematic diagram net table and automatically audit and just can find these mistakes fast.
Auditing system has the net table audit function of 8 sports at present, and infinite expanding can audit item as required.
Section 1 function: for searching the single-ended interconnection network in net table, namely a network only has a pin;
To carry out the principle design of scheme first, this situation often occurs.Just there is problems in following situation:
The first situation: because design proposal scale is larger, network is only defined somewhere, and has leaked and undertaken effectively to connecting by them, and relies on artificial mode, because design scale is large, is looked for by these single-terminal networks complete just more difficult, compares spended time.And this can all navigate to all problems soon by auditing system.
The second situation: both sides network name is inconsistent, causes a network to become 2 single-terminal networks.Many spaces after such as somewhere network name, and an other place does not have space.This situation passes through the artificial normally problem of can not auditing out, because space is invisible.Certainly the network on both sides is that the network name that naked eyes can identify is inconsistent in most of the cases.
All-network on auditing system scanning board, and find out the network only having a pin.
Section 2 function: for checking the device of two pin, whether the network on pin is the same.If the same, illustrate that device has been shorted, this is problematic.
When principle design, by the device of two pin, the pin at the two ends such as such as resistance, electric capacity, inductance connects by mistake.Usually, when picture schematic diagram, the two terminal device such as mobile resistance, electric capacity, inductance cause, and are not easily discovered.All devices on auditing system scanning board, find out the device only having 2 pin, and the network name of these two pin is the same.
Whether Section 3 function: for checking the device of two pin, only have a pin to be connected to network, and another one pin does not connect, this minor error that usually there will be when drawing schematic diagram.Such as electric capacity one end does not connect with ground symbol or power supply symbol.All devices on auditing system scanning board, find out the device only having 2 pin, and have individual pin to have network to connect, and another one pin does not have network to connect.
Section 4 function: for checking single pin device, whether do not have network to connect.
Single pin device normally test point, test point does not have and network connects, and just there will be this problem.Sometimes manually also not easily check out.All devices on auditing system scanning board, find out the device only having 1 pin, and this pin does not have network to connect.
Section 5 function: for checking the device being more than or equal to 3 pin, only has a pin to have network.
Be more than or equal to the device of 3 pin, in the application of reality, usually need the signal meeting 2 pin or more.If only have a pin to have network to connect, that is normally problematic.All devices on auditing system scanning board, find out the device being more than or equal to 3 pin, and this device only has 1 pin to have network to connect.
Section 6 function: for checking in schematic diagram the device having identical value value, but specify different encapsulation.This function is used for the schematic diagram that ORCAD draws, the schematic diagram that HDL draws, and usually the value value of device is not led.So this function, be generally used for the schematic diagram that ORCAD draws.Certainly, this problem found out, not necessarily wrong, for principle diagram design slip-stick artist reference.All devices on auditing system scanning board, find out the device of identical value value, then judge that whether the encapsulation title of these devices is the same.
Section 7 function: whether the non-metallic hole on inspection plate has been defined network.
Non-metallic hole on plate is the screw hole of plank surrounding or the pilot hole of connector normally, and owing to being non-metallic, so can not define network, if be defined network attribute, but in fact also cannot be communicated with, all is problematic.All-network on auditing system scanning board, and find out the pin point that each network connects and whether have non-metallic hole.
Section 8 function: for checking the network being only connected to electric capacity in schematic diagram
If a network is only connected to electric capacity, be not connected with device, so these electric capacity are exactly isolated useless.This problem, the electric power network normally connected due to electric capacity and the title of electric power network of device is inconsistent causes.All-network on auditing system scanning board, finds out the device that network connects, and these devices are all electric capacity.On auditing system, recognition means is the mode of electric capacity is that first it is the device of 2 pin pins, and its REF numbering starts with C.
7, after net table imports allegro, judge why device cannot normally release
After net table imports allegro from schematic diagram; need them to release to come on plate; in the process swung in, usually understand some device cannot put out; these problems are by manually going to confirm why cannot normally show; compare spended time, device (such as the BGA device of the hundreds of pin) problem that pin number is not corresponding that particularly pin pin is many.
From three aspects, auditing system judges why device cannot normally release.
The first situation, auditing system has searched for all paths, storehouse of specifying, and does not find the encapsulation of needs, provides ERROR prompting and can not find encapsulation storehouse.
The second situation, auditing system, in the path, storehouse of specifying, have found encapsulation storehouse.Distributing inconsistent by analyzing the encapsulation storehouse pin number netted in the distribution of the device pin number in showing and path, storehouse, providing WARNING prompting.
The third situation, auditing system, in the path, storehouse of specifying, have found encapsulation storehouse, and pin number distribution is also no problem.So can not show reason may be, does not find pad, plank drawing scope can not put on out not, or basic just no problem.Provide WARNING prompting.
8, non-mode shortcut command is set, convenient design and examination & verification
For convenience of design and examination & verification, auditing system provides a large amount of shortcut commands, comprises the shortcut command of auditing system interface button and keyboard, to facilitate slip-stick artist to the operation of design drawing and control.
Shortcut command, combining exactly by some specific function, then by registration one order, calls these program modules by this order, realizes specific function fast.Such as following order and corresponding function:
LA: represent all electrical layer of display;
L0: represent and close all electrical layer;
L1, L2, L3 ...: represent the electrical layer that display numeral is corresponding; If need to open multiple electrical layer simultaneously, only need to increase space between each letter.Such as: L1 245: represent and open 1245 electrical layer simultaneously.
S: display silk-screen aspect;
First S, rear LT: display silk-screen TOP layer;
First S, rear LB: display silk-screen BOTTOM layer;
SO:Text Outline switch;
SD:Ref and device line indicator cock;
Nearly nearly hundred such shortcut command functions do not enumerate here.
9, audit REF to put and whether there is intersection and put mistake
REF puts intersection, the order that device is put and device R EF to put order inconsistent.This still more often occurs, but is not easy by naked eyes identification.Program draws the line between device and REF exactly, checks whether REF puts correct for naked eyes on realizing, warning is provided to putting of intersection simultaneously, when man-machine interactively examination & verification, only need the part of the line intersection checked between device and REF, whether REF puts correctly.
10, layout examination & verification is carried out by principle map sheet
Under normal circumstances, principle design slip-stick artist, when design concept figure, can be drawn in the relevant device of practical function together.And when layout, be also need, with reference to schematic diagram, the device that function is correlated with to be carried out the layout concentrated.If there is the device of the schematic diagram of same one page, the space of a whole page of PCB is scattered distribution, the device layout that this situation just may exist part is unreasonable.Had this function, design engineer just can find this kind of problem fast, and improves layout.
On auditing system realizes, by extracting the information that in net table, device is relevant with the page, seeing the device of same page, setting up a group, having several pages of schematic diagrams just to set up several group.When examination & verification, just carry out corresponding man-machine interactively operation for these group, and 3 kinds of convenient examination & verifications of highlighted function are provided.
TempHighlight: interim highlighted display;
PermHighlight: use the highlighted display of certain color;
Dehighlight: cancel highlighted display;
11, one by one to electric power network, clock network, differential networks, and the examination & verification of free network interaction
Automatically electric power network is recognized, clock network, differential networks for auditing system, and the network signal that slip-stick artist pays close attention to, need to carry out man-machine interactively examination & verification one by one.
Auditing system lists all network signals automatically recognizing network or call in slip-stick artist's concern at option panel, slip-stick artist clicks corresponding network name can correspond to network cabling on plate automatically, and provide and TempHighlight or PermHighlight is carried out to this network or Dehighlight mode shows, thus facilitate man-machine interactively to audit requirement that whether each network meets design.
Auditing system provides electric power network, clock network, the function of the highlighted and output report of differential networks simultaneously, further facilitates the examination & verification of slip-stick artist to distinctive signal.
Should be understood that, above-mentioned embodiment of the present invention only for exemplary illustration or explain principle of the present invention, and is not construed as limiting the invention.Therefore, any amendment made when not departing from thought of the present invention and scope, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.In addition, claims of the present invention be intended to contain fall into claims scope and border or this scope and border equivalents in whole change and amendment.
Claims (10)
1. a PCB design domain auditing system, is characterized in that, it comprises automatic DFM auditing module and man-machine interactively auditing module; Described automatic DFM auditing module comprises cabling auditing module, via hole auditing module, copper sheet auditing module, silk-screen auditing module, welding resistance auditing module and steel mesh auditing module; Described man-machine interactively auditing module comprises net table auditing module, layout auditing module, signal auditing module, structure I DF output module, element height Reports module, placement-and-routing are correlated with mutual auditing module, silk-screen is correlated with mutual auditing module, produce relevant mutual auditing module.
2. a kind of PCB design domain auditing system according to claim 1, it is characterized in that, when carrying out described automatic DFM auditing module examination & verification, windows program is according to the examination & verification classification chosen and the audit point needed, the demand of allegro skill program audit is informed by ipc communication, then examination & verification is completed by the allegro skill program audit point program calling each auditing module one by one, and form auditing result and auditing statements, finally by ipc communication, auditing result is fed back to windows program, complete selected all examination & verification demands; When carrying out the examination & verification of described man-machine interactively, windows program informs the demand of allegro skill program audit by ipc communication according to the mutual audit point chosen, then the mutual review procedure that allegro skill routine call is corresponding is allowed, complete man-machine interactively examination & verification, finally by ipc communication, auditing result is fed back to windows program.
3. a kind of PCB design domain auditing system according to claim 1, is characterized in that, whether described automatic DFM auditing module comprises decoupling capacitance and to punch nearby auditing module.
4. a kind of PCB design domain auditing system according to claim 3, is characterized in that, first described automatic DFM auditing module determines whether moves back even electric capacity; Then search in electric capacity pin peripheral extent and whether have the via hole the same with electric capacity pin network, if there is via hole, just judge to punch nearby; If there is no via hole, just judges not punch nearby.
5. a kind of PCB design domain auditing system according to claim 1, is characterized in that: described automatic DFM auditing module comprises automatic search and identifies electric power network module.
6. a kind of PCB design domain auditing system according to claim 1, is characterized in that: described automatic DFM auditing module comprises automatic search and identifies clock network module.
7. a kind of PCB design domain auditing system according to claim 1, is characterized in that: described automatic DFM auditing module comprises automatic search and recognition differential subnetwork module.
8. a kind of PCB design domain auditing system according to claim 1, is characterized in that: described automatic DFM auditing module comprises audits each layer cabling of electric power network automatically whether all by overstriking module.
9. a kind of PCB design domain auditing system according to claim 1, it is characterized in that: the net table auditing module of man-machine interactively auditing module comprises the single-ended interconnection network module of searching in net table, check the module of two pin devices whether short circuit, check whether two pin devices exist leakage network connecting module, check whether three pin devices exist leakage network connecting module, judge whether the device of identical value value has same package title module, check whether non-metallic hole is connected with mixed-media network modules mixed-media, check whether that existence is only connected to the module of the network of electric capacity.
10. a kind of PCB design domain auditing system according to claim 1, is characterized in that: described PCB design domain auditing system is provided with non-mode shortcut command.
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106250645A (en) * | 2016-08-09 | 2016-12-21 | 浪潮集团有限公司 | A kind of method detecting power supply live width |
| CN106294926A (en) * | 2016-07-19 | 2017-01-04 | 无锡军安电子科技有限公司 | A kind of line class problem inspection method of printed circuit board |
| CN107368635A (en) * | 2017-07-05 | 2017-11-21 | 上海华虹宏力半导体制造有限公司 | The method for detecting low pressure well region and high-pressure trap area hybrid junction |
| CN107644137A (en) * | 2017-09-26 | 2018-01-30 | 郑州云海信息技术有限公司 | A kind of mating interface defines inspection method and system |
| CN108133103A (en) * | 2017-12-21 | 2018-06-08 | 大连芯巧电子科技有限公司 | A kind of Electronic Design DFM detecting systems, method and medium |
| CN108563909A (en) * | 2018-05-07 | 2018-09-21 | 济南浪潮高新科技投资发展有限公司 | A kind of method and device detecting distance between screw hole and PCB encapsulation |
| CN108762873A (en) * | 2018-05-29 | 2018-11-06 | 郑州云海信息技术有限公司 | A kind of device and method of the layout review in PCB design |
| CN111967214A (en) * | 2020-08-14 | 2020-11-20 | 上海佳研实业有限公司 | Software system capable of realizing printed circuit board aided design |
| CN112307707A (en) * | 2020-09-22 | 2021-02-02 | 中国电子科技集团公司第二十九研究所 | Manufacturability examination method and system for multi-chip assembly |
| CN113706193A (en) * | 2021-08-16 | 2021-11-26 | 深圳市云采网络科技有限公司 | SMT paster processing cost calculation method and electronic equipment |
| CN116822442A (en) * | 2023-07-18 | 2023-09-29 | 涟水县苏杭科技有限公司 | Quality control system and method for PCB design and production |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102819552A (en) * | 2012-06-26 | 2012-12-12 | 深圳市百能信息技术有限公司 | Method and system for automatically examining and verifying Printed Circuit Board (PCB) project files |
| US20130024832A1 (en) * | 2011-07-19 | 2013-01-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | DFM Improvement Utility with Unified Interface |
| CN103593525A (en) * | 2013-11-14 | 2014-02-19 | 信利半导体有限公司 | Secondary processing method and device of DFM analysis report |
-
2015
- 2015-01-14 CN CN201510018178.3A patent/CN104573242B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130024832A1 (en) * | 2011-07-19 | 2013-01-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | DFM Improvement Utility with Unified Interface |
| CN102819552A (en) * | 2012-06-26 | 2012-12-12 | 深圳市百能信息技术有限公司 | Method and system for automatically examining and verifying Printed Circuit Board (PCB) project files |
| CN103593525A (en) * | 2013-11-14 | 2014-02-19 | 信利半导体有限公司 | Secondary processing method and device of DFM analysis report |
Non-Patent Citations (2)
| Title |
|---|
| 张文怡: "DFM 技术在PCB 设计中的应用", 《2010中国高端SMT学术会议》 * |
| 阳小懂: "CAM350自动DFM检测", 《百度文库》 * |
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