CN105701317A - Method and system for correcting signal missing in schematic diagram designing - Google Patents
Method and system for correcting signal missing in schematic diagram designing Download PDFInfo
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- CN105701317A CN105701317A CN201610114478.6A CN201610114478A CN105701317A CN 105701317 A CN105701317 A CN 105701317A CN 201610114478 A CN201610114478 A CN 201610114478A CN 105701317 A CN105701317 A CN 105701317A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Abstract
The invention discloses a method and system for correcting signal missing in schematic diagram designing. The method includes the following steps that 1, network names in a net list are searched for one by one; 2, whether the number of Pins under each the network name is larger than one or not is judged; 3, if not, it is judged that the signal at the Pin position is missed in schematic diagram designing; 4, a check result is output. The situation of network name missing in a schematic diagram can be output directly, and missing connection, caused by carelessness or non-conforming software formats, of signal lines in schematic diagram designing of a hardware engineer is avoided.
Description
Technical field
The present invention relates to a kind of error correction method and system, particularly relate to a kind of method and system that signal in principle diagram design is missed error correction。
Background technology
Many moneys schematic diagram and PCB (PrintedCircuitBoard printed circuit board (PCB)) design software is had at present in electronics industry, the CarpturCIS design principle figure of ripe commonly used Cadence company of scheme company, application Allegro software carries out PCB design operation, however Cadence company CapturCIS do not possess the function checking that single-point connects。
The general work pattern of currently designed company is that a people draws schematic diagram, and another person draws PCB。The people of single picture schematic diagram is because being limited to software function, it is impossible to check that single-point connects。
It is illustrated in figure 1 a common IC (IntegratedCircuit, integrated circuit) chip schematic diagram in principle diagram design software。Winning one of them part as shown in Figure 2, in fig. 2, the electric line segment that 1 is the pull-out of pin foot, 2 is network label, and 3 is input, and output type accords with, and 4 is paging code。
Functions illustrates as follows
1: electrically line segment。In principle diagram design when needs circumscribing peripheral device and device are more, it is necessary to use electric line segment。And when this signal need not connect peripheral components or during network, it is possible to logically introducing " being not connected to symbol (Isnoconnect) " defines this pin foot and can connect by sky, and corresponding system is regardless of distribution network name。The X-shape that symbol actual displayed is attached on relevant pin foot it is not connected to as shown in 1 shown in pin60.pin61.pin62；
2: network label。When multibus connects, it is possible to substitute electric line segment with network label and connect, two identical network label logically companies of being intended in software definition single page；
3: input, output type accords with: defining certain signal pin according to IC specifications is input or output type, facilitates the differentiation of network connection side tropism；
4: paging code。Being used for arranging when schematic diagram divides multipage, heterogeneous networks label requires in this paging code numeral and accurately finds the identical network label in other pages and formulate it and be connected with each other。
The principle that realizes of principle diagram design itself is that according to material specification book image, IC is melted into the symbol (label) in schematic diagram, and by demonstration, design planning signal flows to and produces netlist。In engineer is designed, because of when system is relatively big or the amendment number of occurrence is more, forget to add page break when being likely to because of network label word input error, omission or multipage design, it is possible to bring fatal mistake when the netlist produced in these situations embodies PCB design。Therefore, it is necessary in fact to propose a kind of technological means, so that whether direct feedback principle G-Design misses RST, it is to avoid because of careless or software format, Hardware Engineer requires that not being inconsistent the holding wire brought misses situation when principle diagram design。
Summary of the invention
For the deficiency overcoming above-mentioned prior art to exist, the purpose of the present invention is in that to provide a kind of method and system that signal in principle diagram design is missed error correction, it can situation that directly network name is missed in output principle figure, it is to avoid Hardware Engineer when principle diagram design because careless or software format requires that not being inconsistent the holding wire brought misses situation。
For reaching above-mentioned purpose, the present invention proposes a kind of method that signal in principle diagram design is missed error correction, comprises the steps:
Step one, searches one by one to the network name in netlist；
Step 2, it is judged that under each network name, whether Pin foot quantity is more than 1；
Step 3, if it is not, then judge that this Pin foot place signal is missed as principle diagram design；
Step 4, outgoing inspection result。
Further, in step 3, if so, then judge to continue to search for next network name without missing。
Further, in step 4, when all-network name searches end, export this inspection result。
Further, in step one, the network name in the network attribute file in this netlist is searched one by one。
Further, the method utilizes SKILL language to realize, and calls function by SKILL formula and the network name in network attribute file is searched one by one。
Further, in step 3, when judging that this Pin foot place signal is missed as principle diagram design, recorded to enactment document。
Further, in step 4, outgoing inspection result is that the network printing single-point connects report or highlighted single node network or generates journal file and export。
For reaching above-mentioned purpose, the present invention also provides for one and signal in principle diagram design is missed error correction system, including:
Spider module, searches one by one to the network name in netlist；
Judge module, it is judged that under each network name, whether Pin foot quantity is more than 1；
Miss inspection module, check whether each Pin foot place signal is that principle diagram design is missed according to the judged result of this judge module；
Output module, exports this and misses the inspection result checking module。
Further, this misses inspection module, when the judged result in this judge module is no, it is determined that this Pin foot place signal is that principle diagram design is missed, and when the judged result of this judge module is for being, then judges that each Pin foot place under this network name is without missing。
Further, the network name in the network attribute file in this netlist is searched by this spider module one by one。
Compared with prior art, the present invention is a kind of misses the method and system of error correction by the network name in netlist is searched one by one to signal in principle diagram design, automatic decision also exports single-point connection, the insurmountable signal of principle diagram design software solving existing main flow misses problem, it is to avoid artificial heavy debugging task。
Accompanying drawing explanation
Fig. 1 show common IC chip schematic diagram in principle diagram design software；
Fig. 2 is the part-structure figure of Fig. 1；
Fig. 3 is the flow chart of steps of a kind of method that signal in principle diagram design is missed error correction of the present invention；
Fig. 4 is the schematic flow sheet of the specific embodiment of the invention；
Fig. 5 is the menu bar schematic diagram realizing the method that signal in principle diagram design is missed error correction by the present invention in the specific embodiment of the invention；
Fig. 6 is a kind of system architecture diagram that signal in principle diagram design is missed error correction system of the present invention。
Detailed description of the invention
Below by way of specific instantiation accompanying drawings embodiments of the present invention, those skilled in the art can be understood further advantage and effect of the present invention easily by content disclosed in the present specification。The present invention also can pass through other different instantiation and be implemented or apply, and the every details in this specification also based on different viewpoints and application, can carry out various modification and change under the spirit without departing substantially from the present invention。
Fig. 3 is the flow chart of steps of a kind of method that signal in principle diagram design is missed error correction of the present invention。As it is shown on figure 3, a kind of method that signal in principle diagram design is missed error correction of the present invention, comprise the steps:
Step 301, searches one by one to the network name in netlist。
The medium that schematic diagram and PCB interconnect is netlist。In the specific embodiment of the invention, under Candence company principle diagram design software interface, netlist is made up of three files: pstchip.dat, pstxprt.dat, pstxnet.dat, and wherein pstxnet.dat is network attribute file。Basic format is:
Above form may be interpreted as:
Network is called N17399829, and under this network name, definition has the 1pin foot of device C139 and the 64pin foot of device U8 respectively, and application equivalence statement is expressed as follows:
NET_NAME, is used for defining network name, i.e. network label。
' network label strings ', wherein, network label strings is N17399829, and when User Defined, secondary number system can distribute a flowing water signal automatically。
' folder name: network label ', it is QCA8334.SCHEMATIC1 (SCH_1): N17399829 here。
NODE_NAMEUxxx, NODE_NAME defines the pin foot of device here, and Ux is chip, and xx is pin foot number。
' folder name: network label ' it is FAP-2543CPA_0120-3.SCHEMATIC1 (SCH_1): N17399829 here。
NODE_NAMEUyyy, NODE_NAME defines the pin foot of device here, and Uy is chip, and yy is pin foot number。
In this step, namely the network name in the net meter file pstxnet.dat in netlist is searched one by one。
Step 302, it is judged that under each network name, whether Pin foot quantity is more than 1。
Step 303, if the Pin foot quantity under a certain network name is equal to 1, then judges that this Pin foot place signal is missed as principle diagram design, if the Pin foot quantity under a certain network name is more than 1, then judges to continue to search for next network name without missing。Even under certain network name during only one of which NODE_Name, then judge that signal is missed as principle diagram design herein, if having two or more NODE_Name under certain network name, then without missing the situation continued next network name of lookup。At this it is noted that User Defined is the pin connected without network will not show that in netlist network name and system do not divide flowing water signal network name。It is preferred that when determining that certain Pin foot place signal principle figure design is missed, by inspection result record to enactment document。
Step 304, outgoing inspection result, for instance the network printing single-point connects report or highlighted single node network or generates daily record log file output etc.。It is preferred that when all-network name searches end, outgoing inspection result。
Fig. 4 is the schematic flow sheet of the specific embodiment of the invention。In this specific embodiment, step S1, all-network name in display net list；Step S2, searches N (N=0.1...) individual network name；Step S3, if the Pin foot quantity under this network name is more than 1, then enters step S4, otherwise enters step S5；Step S4, searches the N+1 network name, and enters step S3 and judge that under this network name, whether Pin foot quantity is more than 1, and when the N+1 network name is absent from, enters step S6；Step S5, if the Pin foot quantity under this network name is equal to 1, then it represents that this Pin foot place signal is that principle diagram design is missed, record is to enactment document, and enters S4；Step S6, it is judged that whether all-network name searches is terminated, if not having, then returns step S2 and continues to search for, otherwise, enter step S7；Step S7, outgoing inspection result, for instance highlighted single node network and generation daily record log file output, or the network printing single-point connect report。
In the specific embodiment of the invention, the method that signal in principle diagram design is missed error correction of the present invention utilizes SKILL language to realize, and calls function by Skill formula and the network name in network attribute file pstxnet.dat is searched one by one。SKILL language is as the open language of Allegro software, and user can edit and be embodied on backstage on mastery routine interface。Being loaded once SKILL formula calls function, the efficiency of user operation will improve greatly。
SKILL formula loading method in Allegro software in the detailed description below specific embodiment of the invention:
(1) connect, by realizing single-point, the file checked, the specific embodiment of the invention puts into local variable group folders for spnchk.il file, is generally and installs, with Cadence software, the catalogue that later catalogue is identical。Assuming that Cadence software is arranged on C dish, its path is: C: home pcbenv skill；
(2) amendment C: home pcbenv allegro.ilinit file under path, allegro.ilinit file adds line code: load (" c:/home/pcbenv/skill/align_sym.il ")；
(3) run CadenceAllegroPCB design software, Skill-Test is loaded in menu bar。Method is: the preset path of configuration allegro.men file, assume that Cadence software is arranged on C dish, its path corresponds to: C: Cadence SPB_16.6 share local pcb menus, the relevant position of this file add fast report check result pre-set code:
This code act as and adds corresponding option in menu bar。
(4) in menu bar, the order (ReportSinglePin) quickly to the order (Skill-Test) of signal drain electrode error correction and report check result is performed, it is possible to realize the function of this Skill formula, as shown in Figure 5。
Fig. 6 is a kind of system architecture diagram that signal in principle diagram design is missed error correction system of the present invention。As shown in Figure 6, signal in principle diagram design is missed error correction system by present invention one, including: spider module 601, judge module 602, miss inspection module 603 and output module 604。
Wherein, spider module 601 is for searching one by one the network name in netlist。The medium that schematic diagram and PCB interconnect is netlist, in the specific embodiment of the invention, under Candence company principle diagram design software interface, netlist is made up of three files: pstchip.dat, pstxprt.dat, pstxnet.dat, wherein pstxnet.dat is network attribute file, and spider module 601 is then that the network name in the network attribute file pstxnet.dat of this netlist is searched one by one。
Judge module 602, is used for judging that under each network name, whether Pin foot quantity is more than 1。If only one of which Pin foot under certain network name, then it represents that this Pin foot is the situation that single-point connects, therefore judge module 602 are used for judging that under each network name, whether Pin foot quantity is more than 1。
Miss inspection module 603, check whether each Pin foot place signal is that principle diagram design is missed for the judged result according to this judge module 602。That is, miss inspection module 603 when the judged result of this judge module 602 is no, namely under this network name during only one of which Pin foot, judge that this Pin foot place signal is missed as principle diagram design, and when the judged result of this judge module 602 is for being, when namely having the Pin foot more than 1 under this network name, then judge that these Pin foot places are without missing。It is preferred that when missing inspection module 603 and determining that certain Pin foot place signal principle figure design is missed, by this inspection result record to enactment document。
Output module 604, exports this and misses the inspection result checking module。It is preferred that output module 604 is when all-network name searches end, outgoing inspection result。The mode of outgoing inspection result such as prints the network of single-point and connects report or highlighted single node network or generate daily record log file output etc.。
In sum, the present invention is a kind of misses the method and system of error correction by the network name in netlist is searched one by one to signal in principle diagram design, automatic decision also exports single-point connection, the insurmountable signal of principle diagram design software solving existing main flow misses problem, it is to avoid artificial heavy debugging task。
Above-described embodiment all under the spirit and category of the present invention, can carried out modifying and change by any those skilled in the art。Therefore, the scope of the present invention, should as listed by claims。
Claims (10)
1. the method that signal in principle diagram design is missed error correction, it is characterised in that comprise the steps:
Step one, searches one by one to the network name in netlist；
Step 2, it is judged that under each network name, whether Pin foot quantity is more than 1；
Step 3, if it is not, then judge that this Pin foot place signal is missed as principle diagram design；
Step 4, outgoing inspection result。
2. a kind of method that signal in principle diagram design is missed error correction as claimed in claim 1, it is characterised in that: in step 3, if so, then judge to continue to search for next network name without missing。
3. a kind of method that signal in principle diagram design is missed error correction as claimed in claim 2, it is characterised in that: in step 4, in all-network name search terminate time, export this inspection result。
4. a kind of method that signal in principle diagram design is missed error correction as claimed in claim 3, it is characterised in that: in step one, the network name in the network attribute file in this netlist is searched one by one。
5. a kind of method that signal in principle diagram design is missed error correction as claimed in claim 1, it is characterised in that: the method utilizes SKILL language to realize, and calls function by Skill formula and the network name in network attribute file is searched one by one。
6. a kind of method that signal in principle diagram design is missed error correction as claimed in claim 2, it is characterised in that: in step 3, when judging that this Pin foot place signal is missed as principle diagram design, recorded to enactment document。
7. a kind of method that signal in principle diagram design is missed error correction as claimed in claim 6, it is characterised in that: in step 4, outgoing inspection result is that the network printing single-point connects report or highlighted single node network or generates journal file and export。
8. one kind signal in principle diagram design is missed error correction system, it is characterised in that including:
Spider module, searches one by one to the network name in netlist；
Judge module, it is judged that under each network name, whether Pin foot quantity is more than 1；
Miss inspection module, check whether each Pin foot place signal is that principle diagram design is missed according to the judged result of this judge module；
Output module, exports this and misses the inspection result checking module。
9. signal in principle diagram design is missed error correction system by one as claimed in claim 8, it is characterized in that: this misses inspection module, when judged result in this judge module is no, judge that this Pin foot place signal is missed as principle diagram design, when the judged result of this judge module is for being, then judge that under this network name, each Pin foot place is without missing。
10. signal in principle diagram design is missed error correction system by one as claimed in claim 8, it is characterised in that: the network name in the network attribute file in this netlist is searched by this spider module one by one。
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610114478.6A CN105701317A (en) | 2016-03-01 | 2016-03-01 | Method and system for correcting signal missing in schematic diagram designing |
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| CN201610114478.6A CN105701317A (en) | 2016-03-01 | 2016-03-01 | Method and system for correcting signal missing in schematic diagram designing |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106707142A (en) * | 2017-03-07 | 2017-05-24 | 济南浪潮高新科技投资发展有限公司 | Method for inspecting electrical connection information of PIN devices in PCB (Printed Circuit Board) |
| CN106872878A (en) * | 2017-02-21 | 2017-06-20 | 济南浪潮高新科技投资发展有限公司 | The method and system of automatic detection electrical connection in a kind of PCB |
| CN107644137A (en) * | 2017-09-26 | 2018-01-30 | 郑州云海信息技术有限公司 | A kind of mating interface defines inspection method and system |
| CN108846202A (en) * | 2018-06-13 | 2018-11-20 | 郑州云海信息技术有限公司 | A kind of method and device for checking simulation ground and being digitally electrically connected |
| CN109657359A (en) * | 2018-12-21 | 2019-04-19 | 郑州云海信息技术有限公司 | The method and apparatus that identification encapsulation updates in a kind of PCB design |
| CN113434346A (en) * | 2021-05-26 | 2021-09-24 | 成都天奥信息科技有限公司 | Automatic detection method and system for differential signal polarity connection |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106872878A (en) * | 2017-02-21 | 2017-06-20 | 济南浪潮高新科技投资发展有限公司 | The method and system of automatic detection electrical connection in a kind of PCB |
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| CN108846202B (en) * | 2018-06-13 | 2022-02-18 | 郑州云海信息技术有限公司 | Method and device for checking electrical connection between analog ground and digital ground |
| CN109657359A (en) * | 2018-12-21 | 2019-04-19 | 郑州云海信息技术有限公司 | The method and apparatus that identification encapsulation updates in a kind of PCB design |
| CN113434346A (en) * | 2021-05-26 | 2021-09-24 | 成都天奥信息科技有限公司 | Automatic detection method and system for differential signal polarity connection |
| CN113434346B (en) * | 2021-05-26 | 2023-08-04 | 成都天奥信息科技有限公司 | Automatic detection method and system for differential signal polarity connection |
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