JP2008257302A - Apparatus for automatically simplifying layout - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus for automatically simplifying layout that allows automatically creating data for new simulations without depending on an operator's know-how or skill, and enhancing simulating efficiency. <P>SOLUTION: The apparatus 10 for automatically simplifying layout includes: a simulation kind selecting means 2 for selecting the kind of simulation to be verified; a layout information storage means 1; a net diagram obtaining means 3a for obtaining a net diagram; a layer diagram obtaining means 3b for obtaining a layer diagram; a conversion diagram information storage means 4; an automatic simplifying process means 5; an analysis information storage means 6 for storing information about connections inside a semiconductor chip, delay values, operating requirements, electric characteristics or consumed power, or information on the analysis of the viscosity of a sealant; and an analysis means 7 for running simulations based on figure information from the automatic simplifying process means 5, analysis information from the analysis information storage means 6, and layout information from the layout information storage means 1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an automatic layout simplification device for verifying the characteristics of a semiconductor device in which a semiconductor chip is mounted on a wiring board with bonding wires, and more particularly to an electrical simulation for analyzing the electrical characteristics of a semiconductor device and other simulations. The present invention relates to an automatic layout simplification device for performing simulation after differentiating package layout simplification processing and performing each simplification processing.

  In a conventional semiconductor device manufacturing system, an evaluation process for evaluating a semiconductor substrate in advance is provided before the mounting process, and prior evaluation data obtained in the evaluation process and design data relating to the semiconductor substrate are input. In addition, based on the current mounting conditions in the mounting process, an analysis process for analyzing damage such as internal stress generated in the semiconductor substrate during mounting by simulation is provided, and internal damage obtained in this analysis process is generated. The mounting conditions in the mounting process are changed so as to be suppressed (see, for example, Patent Document 1).

  In this conventional semiconductor device manufacturing system, if design data is applied as it is when performing simulation, the amount of information is large, and it takes a lot of time for processing by a simulator. Therefore, design information is generally simplified. .

In particular, when a simulation is performed on a semiconductor device represented by a three-dimensional shape, the three-dimensional shape, which is design information, is simplified to a figure that can be executed by the simulator, and is used as new data for the simulator. You need to run the simulator after entering it. This simplification relies on the know-how and intuition of the person who performs the simulation, and is determined by manual calculation.
JP 2007-13016 A

  As described above, in order to execute a simulation for a semiconductor device represented by a three-dimensional shape, it is necessary to separately manage design information and simulation data, and it takes time to re-input. There was a point. In addition, simplification until the simulation operates successfully requires input by trial and error, and the same characteristic data is not always obtained if the person performing the simulation is different for the same semiconductor device. There was a problem.

  The present invention has been made to solve the above-described problems, and can automatically create new simulation data without relying on the know-how and intuition of the operator, thereby improving the efficiency of the simulation. An automatic layout simplification device that can be improved is provided.

  In the automatic layout simplification device according to the present invention, the connection information between the terminals is obtained from the layout information storage means storing the layout information of each component in the semiconductor device and the layout information stored in the layout information storage means. A figure corresponding to each layer of the wiring board among the figures based on the net, which is connection information between terminals, is obtained for each layer from the net figure obtaining means for obtaining the figure by the net and the layout information stored in the layout information storage means. The layer graphic acquisition means for acquiring, the conversion graphic information storage means for storing the conversion graphic information for simplifying the graphic, and the curved graphic or the curved line based on the conversion graphic information stored in the conversion graphic information storage means Automatic simplification processing means for simplifying a figure into a figure having a plane or a straight line; Connection information, delay value, operating conditions, electrical characteristics or power consumption, or analysis information storage means for storing information on the viscosity of the sealing material, and graphic information from the automatic simplification processing means, Analysis means for executing a simulation based on the analysis information from the analysis information storage means and the layout information from the layout information storage means.

  In the automatic layout simplification device according to the present invention, if necessary, a simulation type selection unit that selects a type of simulation to be verified based on input information, and a terminal based on selection information of the simulation type selection unit Net figure acquisition means for acquiring a figure by a net as connection information between the layout information, and the automatic simplification processing means extracts a portion corresponding to a via from the acquired figure and converts the figure Via conversion means for converting to a cuboid based on information, ball conversion means for extracting a portion corresponding to the ball from the acquired figure and converting it to a cube based on the conversion figure information, corresponding to a bonding wire among the acquired figures Extract the part and bend the bending part of the bonding wire based on the converted graphic information. A first wire converting means for connecting a plurality of rectangular parallelepipeds as a unit to convert them into a composite that is an integrated shape, and extracting a portion corresponding to a corner of a wiring pattern from the acquired figure and based on the converted figure information This is wiring corner conversion means for converting into a bent shape.

  In the automatic layout simplification device according to the present invention, if necessary, a simulation type selection unit that selects a type of simulation to be verified based on input information, and a terminal based on selection information of the simulation type selection unit Layer graphic acquisition means for acquiring, for each layer from the layout information, a figure corresponding to each layer of the wiring board among figures by the net as connection information between the automatic simplification processing means, Via conversion means for extracting a portion corresponding to a via from the converted graphic and converting it into a rectangular solid based on the converted graphic information, extracting a portion corresponding to the ball from the acquired graphic and converting it to a cube based on the converted graphic information Ball conversion means, each layer of the wiring board corresponding to the wiring pattern of the acquired figure Wiring pattern conversion means for extracting each grid in the grid and converting the wiring pattern in each grid into a square having the same area as the total area of the wiring patterns in each grid based on the converted graphic information, and among the acquired figures A second wire that extracts a plurality of the bonding wires generated from the same side on the upper surface of the semiconductor chip and converts the plurality of straight portions into one rectangular body for each curved portion of the bonding wire based on the converted graphic information. It is a conversion means.

  In the automatic layout simplification device according to the present invention, if necessary, the conversion figure of the portion corresponding to the via is a square of the via that is circumscribed or inscribed on the bottom surface of the via before conversion. A rectangular parallelepiped where the height matches the height of the via after conversion, or the center of the bottom of the via before conversion and the center of the bottom of the via after conversion match, and the height of the via before conversion and the height of the via after conversion And the volume of the via before conversion and the volume of the via after conversion match.

  In the automatic layout simplification device according to the present invention, the conversion figure corresponding to the ball is converted to a cube circumscribing or inscribed in the ball before conversion, or the center of the ball before conversion, as necessary. It is a cube in which the center of the subsequent ball coincides and the volume of the ball before conversion coincides with the volume of the ball after conversion.

  In the automatic layout simplification device according to the present invention, the connection information between the terminals is obtained from the layout information storage means storing the layout information of each component in the semiconductor device and the layout information stored in the layout information storage means. A figure corresponding to each layer of the wiring board among the figures based on the net, which is connection information between terminals, is obtained for each layer from the net figure obtaining means for obtaining the figure by the net and the layout information stored in the layout information storage means. The layer graphic acquisition means for acquiring, the conversion graphic information storage means for storing the conversion graphic information for simplifying the graphic, and the curved graphic or the curved line based on the conversion graphic information stored in the conversion graphic information storage means Automatic simplification processing means for simplifying a figure into a figure having a plane or a straight line; Connection information, delay value, operating conditions, electrical characteristics or power consumption, or analysis information storage means for storing information on the viscosity of the sealing material, and graphic information from the automatic simplification processing means, Analyzing information from the analyzing information storing means and analyzing means for executing a simulation based on the layout information from the layout information storing means, thereby providing new simulation data separately from the design information. It is not necessary for the operator to manually create the data, and the data can be automatically created, so that the efficiency of the simulation can be improved. In particular, a curved surface (curve) that is a part of a figure can be converted into a plane (straight line), and the number of polygons (polygons) used when disassembling and drawing the surface to convert a solid object into data is greatly increased. It is possible to reduce the processing speed and speed up the processing for the simulation.

  In the automatic layout simplification device according to the present invention, if necessary, a simulation type selection unit that selects a type of simulation to be verified based on input information, and a terminal based on selection information of the simulation type selection unit Net figure acquisition means for acquiring a figure by a net as connection information between the layout information, and the automatic simplification processing means extracts a portion corresponding to a via from the acquired figure and converts the figure Via conversion means for converting to a cuboid based on information, ball conversion means for extracting a portion corresponding to the ball from the acquired figure and converting it to a cube based on the conversion figure information, corresponding to a bonding wire among the acquired figures Extract the part and bend the bending part of the bonding wire based on the converted graphic information. A first wire converting means for connecting a plurality of rectangular parallelepipeds as a unit to convert them into a composite that is an integrated shape, and extracting a portion corresponding to a corner of a wiring pattern from the acquired figure and based on the converted figure information Because it is a wiring corner conversion means that converts to a bent shape, it is not necessary for the operator to manually create new simulation data separately from the design information, and the simulation efficiency can be created automatically. Can be improved. Further, it is possible to discriminate between electric simulation and other simulations, and to simplify the net figure to the extent (part) that does not affect the electric simulation. In particular, a curved surface (curve) that is part of a net figure can be converted to a flat surface (straight line), and the number of polygons (polygons) used when disassembling the surface to draw solid objects is greatly increased. And the processing for the electric simulation can be speeded up.

  In the automatic layout simplification device according to the present invention, if necessary, a simulation type selection unit that selects a type of simulation to be verified based on input information, and a terminal based on selection information of the simulation type selection unit Layer graphic acquisition means for acquiring, for each layer from the layout information, a figure corresponding to each layer of the wiring board among figures by the net as connection information between the automatic simplification processing means, Via conversion means for extracting a portion corresponding to a via from the converted graphic and converting it into a rectangular solid based on the converted graphic information, extracting a portion corresponding to the ball from the acquired graphic and converting it to a cube based on the converted graphic information Ball conversion means, each layer of the wiring board corresponding to the wiring pattern of the acquired figure Wiring pattern conversion means for extracting each grid in the grid and converting the wiring pattern in each grid into a square having the same area as the total area of the wiring patterns in each grid based on the converted graphic information, and among the acquired figures A second wire that extracts a plurality of the bonding wires generated from the same side on the upper surface of the semiconductor chip and converts the plurality of straight portions into one rectangular body for each curved portion of the bonding wire based on the converted graphic information. By using the conversion means, it is not necessary for the operator to manually create new simulation data separately from the design information, and the data can be automatically created, and the efficiency of the simulation can be improved. Further, it is possible to discriminate between the electric simulation and the other simulation, and to simplify the layer graphic and the bonding wire to the extent (part) that does not affect the simulation other than the electric simulation. In particular, the curved surface (curve) that is part of the layer figure can be converted to a flat surface (straight line), and the number of polygons (polygons) used when disassembling and drawing the surface to convert a solid object into data is greatly increased. The processing for simulations other than electrical simulation can be speeded up.

  In the automatic layout simplification device according to the present invention, if necessary, the conversion figure of the portion corresponding to the via is a square of the via that is circumscribed or inscribed on the bottom surface of the via before conversion. A rectangular parallelepiped where the height matches the height of the via after conversion, or the center of the bottom of the via before conversion and the center of the bottom of the via after conversion match, and the height of the via before conversion and the height of the via after conversion , And the via conversion volume to be simplified is specified by the rectangular parallelepiped in which the volume of the via before conversion and the volume of the via after conversion match.

  In the automatic layout simplification device according to the present invention, the conversion figure corresponding to the ball is converted to a cube circumscribing or inscribed in the ball before conversion, or the center of the ball before conversion, as necessary. A ball conversion figure to be simplified is specified by a cube in which the center of the subsequent ball coincides and the volume of the ball before conversion coincides with the volume of the ball after conversion.

(First embodiment of the present invention)
FIG. 1 is a diagram showing the configuration of an automatic layout simplification apparatus according to the first embodiment for carrying out the present invention. FIG. 2 is a conversion graphic common to each simulation stored in the conversion graphic information storage means shown in FIG. It is explanatory drawing for demonstrating an example of information, (a) is explanatory drawing which shows the conversion figure of via | veer, (b) is explanatory drawing which shows the conversion figure of a ball | bowl, FIG. 3 is the conversion figure information memory | storage shown in FIG. It is explanatory drawing for demonstrating an example of the conversion figure information in the electrical simulation stored in the means, (a) is explanatory drawing which shows the conversion figure of the corner of a wiring pattern, (b) shows the conversion figure of a bonding wire FIG. 4 is an explanatory diagram for explaining an example of a wiring pattern conversion graphic in a simulation other than the electrical simulation stored in the conversion graphic information storage means shown in FIG. FIG. 5 is an explanatory diagram for explaining an example of a bonding wire conversion figure in a simulation other than the electrical simulation stored in the conversion figure information storage means shown in FIG. 1, and FIG. 6 is a second wire conversion means shown in FIG. FIG. 7 is a flowchart showing the continuation of the simplification algorithm used for the second wire conversion means shown in FIG.

  The layout information storage unit 1 stores layout information of each component in the semiconductor device 100 that is a target for performing the simulation. Specifically, the wiring board 101 shape information and number-of-layers information, wiring-prohibited area information, layout information and shape information of each semiconductor chip 102 arranged on the upper surface 101a of the wiring board 101 are already designed. , Arrangement information and terminal attribute information of terminals 102a and bond fingers 103a (connection destination of bonding wire 103 from semiconductor chip 102), arrangement information of bonding wire 103, shape information and shape parameters, wiring board on each semiconductor chip 102 101, placement information, shape information, and terminal attribute information of balls 104, which are external terminals disposed on the lower surface of 101, placement information and shape information of vias 105 disposed on wiring board 101, and each wiring of wiring board 101 The wiring information of the wiring pattern 106 disposed on the substrate layer is stored.

  Here, the shape information of the wiring substrate 101 is information indicating what shape the wiring substrate 101 has. For example, in the case of a rectangular substrate, the dimensions are vertical and horizontal. Further, the number-of-layers information of the wiring board 101 is information indicating how many layers the wiring board 101 is formed. Further, the wiring prohibited area information is information regarding a prohibited area where the wiring pattern 106 cannot be arranged on each wiring board layer.

  Further, the arrangement information of the semiconductor chip 102 is information relating to the arrangement coordinates of each semiconductor chip 102. Specifically, it is coordinate information of a point representing the position of the semiconductor chip 102 (for example, one of the vertices at the bottom of the semiconductor chip 102). The shape information of the semiconductor chip 102 is information related to the shape of each semiconductor chip 102. Specifically, in the case of a rectangular parallelepiped semiconductor chip 102, the information is vertical, horizontal, and height. Furthermore, the arrangement information of the bond fingers 103a of the semiconductor chip 102 indicates relative coordinates with respect to a representative point of the semiconductor chip 102.

  Further, the terminal attribute information of the terminal 102a (and the ball 104 of the wiring board 101) of the semiconductor chip 102 includes the terminal 102a (and the ball 104) provided on the semiconductor chip 102 (and the wiring board 101) and the respective input. This is information indicating which terminal 102a (and ball 104) is being output.

  Also, shape information and layer number information of the wiring board 101, arrangement information and shape information of each semiconductor chip 102 arranged on the upper surface 101a of the wiring board 101, arrangement information of the terminals 102a and bond fingers 103a of each semiconductor chip 102 And terminal attribute information, bonding wire 103 arrangement information, shape information and shape parameters, via 105 arrangement information and shape information, arrangement information of balls 104 arranged on the lower surface of the wiring board 101, shape information and terminal attribute information, Wiring information of the wiring pattern 106 arranged on each wiring board layer of the wiring board 101, wiring prohibited area information, and the like are generated by the layout design CAD device 20.

  The simulation type selection means 2 selects the type of simulation to be verified with respect to the semiconductor device 100 to be simulated based on input information input by the input device 30 such as a mouse or a keyboard. The simulation types include electrical simulation that analyzes electrical characteristics such as package electrical characteristics and input signal delay time, thermal extraction such as chip junction temperature extraction, package thermal characteristics, and wiring board heat distribution. Thermal simulation for analyzing characteristics, stress simulation for analyzing mechanical characteristics such as stress value, warpage amount, deformation shape and stress location on the wiring board 101, and sealing the semiconductor chip 102 and the soldered component on the wiring board 101 There are fluid simulations that analyze fluids such as the behavior of sealing materials.

  In the first embodiment, the simulation is classified into an electrical simulation and other simulations, and when the electrical simulation is selected, selection information is output to the net graphic acquisition means 3a. When a simulation other than the electrical simulation is selected, selection information is output to the layer graphic acquisition means 3b. In this way, electrical simulation and other simulations are classified as follows: electrical simulation requires that the simulation be carried out after maintaining the connection information between terminals. This is because the pattern 106 and the bonding wire 103 cannot be greatly simplified as will be described later.

  The net figure acquisition unit 3a connects between the terminal 102a of the semiconductor chip 102, the terminal of the electronic component (not shown) or the ball 104 which is an external terminal based on the selection information (when electric simulation is performed) of the simulation type selection unit 2. A net graphic (hereinafter referred to as a net graphic) as the actual state of connection information (hereinafter referred to as a net) is acquired from the layout information stored in the layout information storage means 1. The net graphic information is output to the via conversion means 5a, the ball conversion means 5b, the wiring corner conversion means 5c, and the first wire conversion means 5d in the automatic simplification processing means 5 described later.

  Based on the selection information of the simulation type selection means 2 (when a simulation other than an electrical simulation is performed), the layer graphic acquisition means 3b selects a graphic (hereinafter referred to as a layer graphic) corresponding to each layer of the wiring board 101 from the net graphic. Each layer is acquired from the layout information. Further, the layer graphic information is output to the via conversion means 5a, the ball conversion means 5b, the wiring pattern conversion means 5e, and the second wire conversion means 5f in the automatic simplification processing means 5 described later.

  The converted graphic information storage means 4 stores converted graphic information for simplifying the net graphic or the layer graphic. As this conversion graphic information, the substantially cylindrical via 105 disposed on the wiring board 101 is converted into a rectangular parallelepiped via 115. For example, as shown in FIG. A square circumscribing the bottom surface of 105 is used as a bottom surface, and converted into a rectangular parallelepiped via 115 in which the height of the via 105 before conversion coincides with the height of the via 115 after conversion. In the first embodiment, the via 115 after conversion is a square circumscribing the bottom surface of the via 105 before conversion, and the height of the via 105 before conversion matches the height of the via 115 after conversion. Although converted into a rectangular parallelepiped via 115, a square inscribed in the bottom surface of the via 105 before conversion is used as a bottom surface, and the height of the via 105 before conversion coincides with the height of the via 115 after conversion. The center of the bottom surface of the via 105 before conversion may coincide with the center of the bottom surface of the via 115 after conversion, and the height of the via 105 before conversion matches the height of the via 115 after conversion. The volume of the via 105 before conversion may be converted to a rectangular parallelepiped via 115 in which the volume of the via 115 after conversion matches.

  Further, as other converted graphic information, a substantially spherical ball 104 disposed on the lower surface of the wiring board 101 is converted into a cubic ball 114. For example, as shown in FIG. Conversion into a cubic ball 114 circumscribing the ball 104 before conversion. In the first embodiment, the converted ball 114 is a cubic ball 114 circumscribing the ball 104 before conversion, but is converted into a cubic ball 114 inscribed in the ball 104 before conversion. Alternatively, the ball 104 may be converted into a cubic ball 114 in which the center of the ball 104 before conversion matches the center of the ball 114 after conversion, and the volume of the ball 104 before conversion matches the volume of the ball 114 after conversion. May be.

  Further, as other converted graphic information, when an electrical simulation is performed, a curved shape (hereinafter referred to as a curved shape) corner 106a of the wiring pattern 106 disposed in each layer of the wiring substrate 101 is bent. For example, as shown in FIG. 3A, an edge of a substantially rectangular linear pattern 106b arranged in series via the corner 106a is converted into a corner 116a having the shape (hereinafter referred to as a bent shape). The portion 106c is converted into a bent corner 116a which is a region extending and surrounded until the portion 106c intersects.

  In addition, as other converted graphic information, a substantially cylindrical bonding wire having a curved portion 103b that connects the terminal 102a of the semiconductor chip 102 and the bond finger 103a on the wiring substrate 101 when performing an electrical simulation. 103 is converted into a composite bonding wire 113 having a shape in which a plurality of rectangular parallelepipeds are connected and integrated with the bending portion 103b of the bonding wire 103 as a bent portion 113d. For example, as shown in FIG. 3 (b), a pair of straight portions 103c arranged in series via a curved portion 103b in the bonding wire 103 before conversion is replaced with a square that circumscribes the bottom surface of each straight portion 103c. As a pair of rectangular parallelepipeds matched with the length of each straight line portion 103c, the side surfaces 113e of the pair of rectangular parallelepipeds are arranged on the same plane, and the side surfaces 113e of each rectangular parallelepiped intersect the corresponding rectangular parallelepiped side surfaces 113e. Until then, a plurality of rectangular parallelepipeds are connected and converted into an integrated composite bonding wire 113 as a bent portion 113d of a polygonal column that is an extended and surrounded region. In the first embodiment, a part of the straight portion 113c of the composite body, which is the bonding wire 113 after conversion, is a square that circumscribes the bottom surface of the straight portion 103c of the bonding wire 103 before conversion, before conversion. The length of the straight line portion 103c and the length of the straight line portion 113c after conversion are converted into a rectangular parallelepiped, and a square inscribed in the bottom surface of the straight line portion 103c in the bonding wire 103 before conversion is used as the bottom surface. The length of the straight line portion 103c before conversion and the length of the straight line portion 113c after conversion may be converted into a rectangular parallelepiped, or the converted bonding wire 113 may be converted to the center line of the bonding wire 103 before conversion. And the center line of the bonding wire 113 after conversion match, the total length of the bonding wire 103 before conversion and the bonding wire after conversion 113 total length and match of, may be converted to the complex is a bent rectangular volume between the bonding wires 113 after the volume and conversion of the pre-conversion of the bonding wires 103 are matched.

  Furthermore, as other converted graphic information, when a simulation other than an electrical simulation is performed, a square wiring pattern 116 having the same area as the total area of the wiring patterns 106 in each grid in each layer of the wiring board 101 is obtained. Thus, the wiring pattern 106 in each grid is converted. For example, as shown in FIG. 4, the wiring patterns 106 in each grid are arranged in the corresponding grid so that the center of the corresponding grid matches the center of the square, and the grid lines and the sides of the square are parallel to each other. The wiring pattern 116 is converted into a square wiring pattern 116 disposed at the position of. In FIG. 4, since the total area of the wiring pattern 106 is different for each grid, the square wiring pattern 116 after conversion has a difference in the square area (size) for each grid.

  As other converted graphic information, when a simulation other than an electrical simulation is performed, a plurality of bonding wires 103 generated from the same side on the upper surface of the semiconductor chip 102 are provided for each curved portion 103 b of the bonding wire 103. The plurality of straight portions 103c are converted into a single rectangular body into bonding wires 113 made up of a plurality of rectangular bodies. For example, as shown in FIG. 5, a rectangular body is formed from five terminals 102a on the same side of the upper surface of the semiconductor chip 102 to the first curved portion 103b, and the first curved portion 103b is bonded to the first curved portion 103b. The finger 103a up to one rectangular body is converted into two rectangular bonding wires 113.

  The automatic simplification processing means 5 is a wiring corner conversion means 5c which is a processing means for simplifying the corner 106a of the wiring pattern 106 for electric simulation, and a first wire conversion means which is a processing means for simplifying the bonding wire 103. 5d, a wiring pattern conversion means 5e that is a processing means that simplifies the wiring pattern 106 for simulations other than electrical simulation, a second wire conversion means 5f that is a processing means that simplifies the bonding wire 103, and each simulation. Therefore, the net obtained by the net graphic acquisition means 3a and the layer graphic acquisition means 3b comprises a via conversion means 5a that is a processing means that simplifies the via 105 and a ball conversion means 5b that is a processing means that simplifies the ball 104. Graphic information and layer graphic information, alignment Based on the conversion graphic information stored in the conversion graphic information storage unit 4, via 105, the ball 104, the corner 106a, simplifies respective wiring patterns 106 and the bonding wires 103.

  Via conversion means 5a extracts a portion corresponding to via 105 from the acquired graphic from the net graphic information from net graphic acquisition means 3a or the layer graphic information from layer graphic acquisition means 3b, and converted graphic information storage means 4 The cylindrical via 105 is converted into a rectangular parallelepiped via 115 based on the converted graphic information from.

  The ball converting means 5b extracts the portion corresponding to the ball 104 from the acquired graphic from the net graphic information from the net graphic acquiring means 3a or the layer graphic information from the layer graphic acquiring means 3b, and the converted graphic information storage means 4 The spherical ball 104 is converted into a cubic ball 114 based on the converted graphic information from.

  The wiring corner conversion means 5c extracts a portion corresponding to the corner 106a of the wiring pattern 106 from the acquired graphic from the net graphic information from the net graphic acquisition means 3a, and converts it into the converted graphic information from the converted graphic information storage means 4. Based on this, the curved corner 106a is converted into a bent corner 116a.

  The first wire converting means 5d extracts a portion corresponding to the bonding wire 103 from the acquired graphic from the net graphic information from the net graphic acquiring means 3a, and based on the converted graphic information from the converted graphic information storage means 4. Then, the bending portion 103b of the bonding wire 103 is used as a bending portion 113d, and a plurality of rectangular parallelepipeds are connected to each other and converted into a composite bonding wire 113.

  The wiring pattern conversion means 5e extracts, from the layer graphic information from the layer graphic acquisition means 3b, a portion corresponding to the wiring pattern 106 in the acquired graphic for each grid in each layer of the wiring board 101, and the converted graphic information storage means 4 Is converted to a square wiring pattern 116 having the same area as the total area of the wiring patterns 106 in each grid.

  The second wire converting unit 5f extracts a plurality of bonding wires 103 generated from the same side on the upper surface of the semiconductor chip 102 from the acquired graphic from the layer graphic information from the layer graphic acquiring unit 3b, and converts the converted graphic information. Based on the converted graphic information from the storage means 4, the plurality of linear portions 103 c are converted into one rectangular body for each bending portion 103 b of the bonding wire 103, and are converted into bonding wires 113 made up of a plurality of rectangular bodies.

  Here, a simplified algorithm of the bonding wire 103 by the second wire conversion means 5f will be described with reference to FIGS. Hereinafter, in FIG. 5, the direction parallel to the long side of the top surface of the semiconductor chip 102 placed on the top is taken as the X axis, and the direction parallel to the short side of the top surface of the semiconductor chip 102 placed on the top is taken as the Y axis. In the following description, the direction perpendicular to the upper surface of the uppermost semiconductor chip 102 is defined as the Z axis.

  First, it is determined whether or not the arrangement direction of the terminals 102a on the semiconductor chip 102 in the plurality of simplified bonding wires 103 generated from the same side of the semiconductor chip 102 is parallel to the X axis (step S1).

  If it is determined in step S1 that the arrangement direction is parallel to the X-axis, “n = 0” is set (step S2), and the n-th curve from the terminal 102a group located on the same side of the semiconductor chip 102 is obtained. A plurality of bonding wires 103 positioned between the portion 103b group and the (n + 1) -th bending portion 103b group are formed into one rectangle (step S3). Note that n is a natural number, and in the following description, the number of the bending portion 103b and the bond finger 103a of the bonding wire 103 counted from the terminal 102a of the semiconductor chip 102 (if n = 0, the semiconductor is It corresponds to the terminal 102a of the chip 102), but it may represent the number corresponding to the bending portion 103b and the terminal 102a from the bond finger 103a.

  In this case, the coordinates of the vertexes of the rectangle to be converted are (Xn1, Yn1, Zn1), (Xn2, Yn2, Zn2), (Xn2, Yn1, Zn1), and (Xn1, Yn2, Zn2), respectively. Xn1 is the smaller X coordinate of the minimum X coordinate in the n-th curved portion 103b group (terminal 102a group in the case of n = 0) and the minimum X coordinate in the (n + 1) -th curved portion 103b group, and Yn1 Is the Y coordinate obtained by averaging the Y coordinates in the nth curved portion 103b group (terminal 102a group when n = 0), and Zn1 is the nth curved portion 103b group (terminal 102a group when n = 0). ) Is the average Z coordinate. Xn2 is the larger X coordinate of the maximum X coordinate in the n-th curved portion 103b group (the terminal 102a group in the case of n = 0) and the maximum X coordinate in the (n + 1) -th curved portion 103b group. Yn2 is a Y coordinate obtained by averaging the Y coordinates in the (n + 1) th bending portion 103b group, and Zn2 is a Z coordinate obtained by averaging the Z coordinates in the (n + 1) th bending portion 103b group.

  Then, from the terminal 102a group located on the same side of the semiconductor chip 102, which is the portion of the bonding wire 103 to be converted into a rectangular body, the n-th curved portion 103b group (the terminal 102a group when n = 0) and The total volume of the bonding wire 103 between the (n + 1) th bending portion 103b group (the cross-sectional area of the bonding wire 103 × the nth bending portion 103b (the terminal 102a group when n = 0)) and the (n + 1) th bending portion 103b. And the area of the rectangle is calculated from the four apexes. Further, the thickness of the rectangular body to be simplified is calculated by dividing the calculated total volume of the conversion portion of the bonding wire 103 by the calculated rectangular area, and the n-th curved portion 103b group (n = In the case of 0, the bonding wire 103 between the terminal 102a group) and the (n + 1) th bending portion 103b group is formed into a rectangular body (step S4).

  Then, it is determined whether or not the (n + 1) th corresponds to the bond finger 103a (step S5). If it is determined in step S5 that the (n + 1) th does not correspond to the bond finger 103a, “n + 1” is set (step S6), and the process returns to step S3.

  If it is determined in step S5 that the (n + 1) th corresponds to the bond finger 103a, the bonding wire 103 generated from the terminal 102a group in which the arrangement direction not converted into the rectangular body is parallel to the X axis is Then, it is determined whether or not the semiconductor chip 102 exists on the opposite side and the other semiconductor chip 102 (step S7).

  If it is determined in step S7 that the bonding wire 103 that has not been converted to the rectangular body exists on the opposite side of the semiconductor chip 102 and the other semiconductor chip 102, the bonding wire 103 that has not been converted to the rectangular body is As an object (step S8), the process returns to step S2.

  If it is determined in step S7 that the bonding wire 103 that has not been converted to a rectangular body does not exist on the opposite side of the semiconductor chip 102 and the other semiconductor chip 102, or in step S1, the arrangement direction is parallel to the X axis. If it is determined that it is not, it is determined whether or not the arrangement direction of the terminals 102a on the semiconductor chip 102 in the plurality of simplified bonding wires 103 generated from the same side of the semiconductor chip 102 is parallel to the Y axis. (Step S9).

  If it is determined in step S9 that the arrangement direction is parallel to the Y-axis, “n = 0” is set (step S10), and the n-th curve from the terminal 102a group located on the same side of the semiconductor chip 102 is obtained. A plurality of bonding wires 103 positioned between the portion 103b group and the (n + 1) th bending portion 103b group are formed into one rectangle (step S11).

  In this case, the coordinates of the vertexes of the rectangle to be created are (Xn1, Yn1, Zn1), (Xn2, Yn2, Zn2), (Xn1, Yn2, Zn1), and (Xn2, Yn1, Zn2), respectively. Xn1 is an X coordinate obtained by averaging the X coordinates in the nth bending portion 103b group (the terminal 102a group when n = 0), and Yn1 is the nth bending portion 103b group (the terminal 102a when n = 0). Group) and the smallest Y coordinate of the (n + 1) th bending portion 103b group, the smaller Y coordinate, and Zn1 is the nth bending portion 103b group (if n = 0, the terminal 102a group) ) Is the average Z coordinate. Xn2 is an X coordinate obtained by averaging the X coordinates in the (n + 1) th bending portion 103b group, and Yn2 is the maximum Y coordinate in the nth bending portion 103b group (the terminal 102a group when n = 0) and the The larger Y coordinate among the maximum Y coordinates in the (n + 1) th bending portion 103b group, and Zn2 is the Z coordinate obtained by averaging the Z coordinates in the (n + 1) th bending portion 103b group.

  Then, from the terminal 102a group located on the same side of the semiconductor chip 102, which is the portion of the bonding wire 103 to be converted into a rectangular body, the n-th curved portion 103b group (the terminal 102a group when n = 0) and The total volume of the bonding wire 103 between the (n + 1) th bending portion 103b group (the cross-sectional area of the bonding wire 103 × the nth bending portion 103b (the terminal 102a group when n = 0)) and the (n + 1) th bending portion 103b. And the area of the rectangle is calculated from the four apexes. Further, the thickness of the rectangular body to be simplified is calculated by dividing the calculated total volume of the conversion portion of the bonding wire 103 by the calculated rectangular area, and the n-th curved portion 103b group (n = In the case of 0, the bonding wire 103 between the terminal 102a group) and the (n + 1) th bending portion 103b group is formed into a rectangular body (step S12).

  Then, it is determined whether or not the (n + 1) th corresponds to the bond finger 103a (step S13). If it is determined in step S13 that the (n + 1) th does not correspond to the bond finger 103a, “n + 1” is set (step S14), and the process returns to step S11.

  If it is determined in step S13 that the (n + 1) th corresponds to the bond finger 103a, the bonding wire 103 generated from the terminal 102a group in which the arrangement direction not converted to the rectangular body is parallel to the Y axis is Then, it is determined whether or not the semiconductor chip 102 exists on the opposite side and the other semiconductor chip 102 (step S15).

  If it is determined in step S15 that the bonding wire 103 that has not been converted into the rectangular body exists on the opposite side of the semiconductor chip 102 and the other semiconductor chip 102, the bonding wire 103 that has not been converted into the rectangular body is As an object (step S16), the process returns to step S10.

  If it is determined in step S15 that the bonding wire 103 that has not been converted into the rectangular body does not exist on the opposite side of the semiconductor chip 102 and the other semiconductor chip 102, or in step S1, the arrangement direction is parallel to the Y axis. If not, the simplification process for the bonding wire 103 is terminated.

  In the first embodiment, in step S1, the terminals 102a on the semiconductor chip 102 in the plurality of bonding wires 103 to be simplified are generated from the same side of the semiconductor chip 102 before the Y axis. Is determined to be parallel to the X-axis. However, it may be determined first whether or not it is parallel to the Y-axis, or a group of terminals 102a having an alignment direction parallel to one of the axes. Only a plurality of bonding wires generated from the above may be converted into a rectangular body.

  The analysis information storage means 6 is input by the input device 30 and the connection information, delay values, operating conditions, electrical characteristics or power consumption inside the semiconductor chip 102 in the semiconductor device 100 that performs the simulation, or on the wiring board 101 The analysis information such as the viscosity of the sealing material (not shown) for packaging the semiconductor chip 102 is stored.

  The analysis means 7 includes graphic information from the via conversion means 5a, ball conversion means 5b, first wire conversion means 5d and wiring corner conversion means 5c, analysis information from the analysis information storage means 6, and layout information storage means. Based on the layout information from 1, an electrical simulation is executed and the analysis result is output to the display device 40. Further, the graphic information from the via conversion means 5a, the ball conversion means 5b, the wiring pattern conversion means 5e and the second wire conversion means 5f, the analysis information from the analysis information storage means 6, and the layout information storage means 1 Based on the layout information, a simulation other than the electrical simulation is executed, and the analysis result is output to the display device 40.

  Next, an automatic simplification processing method of the automatic layout simplification apparatus 10 according to the first embodiment for carrying out the present invention will be described. In the first embodiment, a case where an electric simulation or a thermal simulation is performed will be described as an example. FIG. 8 is a flowchart showing the flow of the automatic simplification processing method in the first embodiment for carrying out the present invention, and FIG. 9 is a flowchart showing the continuation of the flowchart shown in FIG.

  First, the simulation type selection unit 2 determines whether or not the simulation performed on the semiconductor device 100 to be simulated is an electric simulation based on the input information from the input device 30 (step S101).

  If it is determined in step S101 that the simulation to be performed is an electrical simulation, the simulation type selection unit 2 outputs selection information to the net graphic acquisition unit 3a. Then, the net graphic acquisition unit 3a determines whether or not a net exists in the semiconductor device 100 that is the target of the electric simulation based on the layout information from the layout information storage unit 1 (step S102).

  If it is determined in step S102 that a net exists in the semiconductor device 100 that is the object of the electrical simulation, the net graphic acquisition unit 3a acquires a net graphic from the layout information (step S103).

  Then, the net graphic acquisition unit 3a determines whether or not there is a portion corresponding to the bonding wire 103 in the acquired net graphic (step S104).

  If it is determined in step S104 that there is a portion corresponding to the bonding wire 103 in the acquired net graphic, the net graphic acquiring means 3a outputs net graphic information to the first wire converting means 5d. Then, the first wire converting means 5d extracts a portion corresponding to the bonding wire 103 from the acquired net graphic, and corresponds to the extracted bonding wire 103 based on the converted graphic information from the converted graphic information storage means 4. After the part is converted into a composite, it is registered in the layout information storage means 1 (step S105). Then, the process returns to step 102.

  If it is determined in step S104 that there is no portion corresponding to the bonding wire 103 in the acquired net graphic, the net graphic acquiring unit 3a determines whether there is a portion corresponding to the via 105 in the acquired net graphic. It is determined whether or not (step S106).

  If it is determined in step S106 that there is a portion corresponding to the via 105 in the acquired net graphic, the net graphic acquisition means 3a outputs net graphic information to the via conversion means 5a. Then, the via conversion means 5a extracts a portion corresponding to the via 105 from the acquired net graphic, and converts the portion corresponding to the extracted via 105 into a rectangular parallelepiped based on the converted graphic information from the converted graphic information storage means 4. After that, it is registered in the layout information storage means 1 (step S107). Then, the process returns to step 102.

  If it is determined in step S106 that there is no portion corresponding to the via 105 in the acquired net graphic, the net graphic acquiring unit 3a determines whether there is a portion corresponding to the ball 104 in the acquired net graphic. Is determined (step S108).

  If it is determined in step S108 that there is a portion corresponding to the ball 104 in the acquired net graphic, the net graphic acquiring means 3a outputs net graphic information to the ball converting means 5b. Then, the ball converting means 5b extracts a portion corresponding to the ball 104 from the acquired net graphic, and converts the portion corresponding to the extracted ball 104 into a cube based on the converted graphic information from the converted graphic information storage means 4. After that, it is registered in the layout information storage means 1 (step S109). Then, the process returns to step 102.

  If it is determined in step S108 that there is no portion corresponding to the ball 104 in the acquired net graphic, the net graphic acquisition unit 3a corresponds to the corner 106a of the wiring pattern 106 in the acquired net graphic. It is determined whether or not there is (step S110).

  If it is determined in step S110 that there is a portion corresponding to the corner 106a of the wiring pattern 106 in the acquired net graphic, the net graphic acquisition means 3a outputs the net graphic information to the wiring corner conversion means 5c. . Then, the wiring corner conversion unit 5c extracts a portion corresponding to the corner 106a of the wiring pattern 106 from the acquired net graphic, and based on the converted graphic information from the converted graphic information storage unit 4, the extracted corner of the wiring pattern 106 is extracted. The portion corresponding to 106a is converted into a bent shape and then registered in the layout information storage means 1 (step S111). Then, the process returns to step 102.

  If it is determined in step S102 that no net exists in the semiconductor device 100 that is the target of the electrical simulation, the via conversion unit 5a, the ball conversion unit 5b, the wiring corner conversion unit 5c, or the first wire conversion unit 5d If the symmetrical part of the net figure is converted, the converted graphic information is output to the analyzing means 7 and electric simulation is performed.

  If it is determined in step S101 that the simulation to be performed is not an electrical simulation, the simulation type selection unit 2 performs the simulation for the semiconductor device 100 to be simulated based on the input information from the input device 30. It is determined whether it is a simulation (step S112).

  When it is determined in step S112 that the simulation to be performed is a thermal simulation, the simulation type selection unit 2 outputs selection information to the layer graphic acquisition unit 3b. Based on the layout information from the layout information storage unit 1, the layer graphic acquisition unit 3b sets the layer count to 0 (the first layer) among the layers of the wiring board 101 in the semiconductor device 100 that is the target of the thermal simulation. (Target) (step S113), it is determined whether or not a layer graphic exists in the target layer (step S114).

  If it is determined in step S114 that a layer graphic exists in the target layer, the layer graphic acquisition unit 3b acquires the layer graphic of the target layer from the layout information (step S115).

  Then, the layer graphic acquisition unit 3b determines whether or not there is a portion corresponding to the via 105 in the acquired layer graphic (step S116).

  If it is determined in step S116 that there is a portion corresponding to the via 105 in the acquired layer graphic, the layer graphic acquisition means 3b outputs the layer graphic information to the via conversion means 5a. Then, the via conversion means 5a extracts a portion corresponding to the via 105 from the acquired layer graphic, and converts the portion corresponding to the extracted via 105 into a rectangular parallelepiped based on the conversion graphic information from the conversion graphic information storage means 4. (Step S117). Then, the process returns to step 114.

  When it is determined in step S116 that there is no portion corresponding to the via 105 in the acquired layer graphic, the layer graphic acquisition unit 3b determines whether there is a portion corresponding to the ball 104 in the acquired layer graphic. Is determined (step S118).

  If it is determined in step S118 that there is a portion corresponding to the ball 104 in the acquired layer graphic, the layer graphic acquisition means 3b outputs the layer graphic information to the ball conversion means 5b. Then, the ball converting means 5b extracts the portion corresponding to the ball 104 from the acquired layer graphic, and converts the extracted portion corresponding to the ball 104 into a cube based on the converted graphic information from the converted graphic information storage means 4. (Step S119). Then, the process returns to step 114.

  If it is determined in step S118 that there is no portion corresponding to the ball 104 in the acquired layer graphic, the layer graphic acquisition unit 3b determines whether there is a portion corresponding to the wiring pattern 106 in the acquired layer graphic. It is determined whether or not (step S120).

  If it is determined in step S120 that there is a portion corresponding to the wiring pattern 106 in the acquired layer graphic, the layer graphic acquisition means 3b outputs the layer graphic information to the wiring pattern conversion means 5e. Then, the wiring pattern conversion unit 5e extracts a portion corresponding to the wiring pattern 106 in the obtained layer graphic for each designated grid in the layer that is the target of the wiring substrate 101, and converts the converted graphic information from the converted graphic information storage unit 4. Based on the graphic information, the wiring pattern 106 in each grid is converted into a square having the same area as the total area of the wiring pattern 106 in each grid (step S121). Then, the process returns to step 114.

  If it is determined in step S114 that there is no layer graphic in the target layer, the layer graphic acquisition means 3b is based on the layout information from the layout information storage means 1 in the semiconductor device 100 that is the target of the thermal simulation. Of each layer of the wiring board 101, the layer count is set to +1 (targeting the next layer) (step S122). Then, it is determined whether or not the layer is over (step S123).

  If it is determined in step S123 that the layer is not over, the process returns to step S114. If it is determined that the layer is over, a representative figure is registered in the layout information storage unit 1 for each grid in each layer (step S125).

  Then, the layer graphic acquisition unit 3b outputs the layer graphic information to the second wire conversion unit 5f. The second wire converting means 5f extracts a plurality of bonding wires 103 generated from the same side on the upper surface of the semiconductor chip 102 from the obtained layer graphic by the simplified algorithm shown in FIG. 6 and FIG. Based on the converted graphic information, the plurality of linear portions 103c are converted into one rectangular body for each bending portion 103b of the bonding wire 103 (step S125).

  Then, the second wire conversion means 5f converts the symmetric bonding wire 103, and the via conversion means 5a, the ball conversion means 5b, or the wiring pattern conversion means 5e converts the target portion of the layer graphic. If there is, the converted graphic information is output to the analysis means 7 and thermal simulation is performed. If it is determined in step S112 that the simulation to be performed is not a thermal simulation, the process ends without performing the automatic simplification process.

  In the first embodiment, in step S101, it is determined whether the simulation to be performed is an electrical simulation prior to the thermal simulation. However, it is determined first whether the simulation is a thermal simulation. Alternatively, the automatic simplification process may be performed only for one of the simulations.

  Further, in the automatic simplification process for the electric simulation shown in FIG. 8, the first is the bonding wire 103, the second is the via 105, the third is the ball 104, and the fourth is the wiring corner 106a. However, the present invention is not limited to this order, and may be changed as appropriate.

  In addition, in the automatic simplification process for the thermal simulation shown in FIG. 9, the first and second vias 105, the second balls 104, and the third wiring patterns 106 are used to determine the presence / absence and to convert the figures. However, the order is not limited to this, and may be changed as appropriate.

It is a figure which shows the structure of the layout automatic simplification apparatus in 1st Embodiment for implementing this invention. It is explanatory drawing for demonstrating an example of the conversion figure information common to each simulation stored in the conversion figure information storage means shown in FIG. 1, (a) is explanatory drawing which shows the conversion figure of a via, (b) is It is explanatory drawing which shows the conversion figure of a ball | bowl. It is explanatory drawing for demonstrating an example of the conversion figure information in the electric simulation stored in the conversion figure information storage means shown in FIG. 1, (a) is explanatory drawing which shows the conversion figure of the corner of a wiring pattern, (b) These are explanatory drawings which show the conversion figure of a bonding wire. It is explanatory drawing for demonstrating an example of the conversion figure of the wiring pattern in simulation other than the electrical simulation stored in the conversion figure information storage means shown in FIG. It is explanatory drawing for demonstrating an example of the conversion figure of the bonding wire in simulations other than the electrical simulation stored in the conversion figure information storage means shown in FIG. It is a flowchart which shows the simplification algorithm used for the 2nd wire conversion means shown in FIG. It is a flowchart which shows the continuation of the simplification algorithm used for the 2nd wire conversion means shown in FIG. It is a flowchart which shows the flow of the automatic simplification processing method in 1st Embodiment for implementing this invention. It is a flowchart which shows the continuation of the flowchart shown in FIG.

Explanation of symbols

1 Layout information storage means
2 Simulation type selection means
3a Net figure acquisition means
3b Layer graphic acquisition means
4 Conversion figure information storage means
5 Automatic simplification processing means
5a Via conversion means
5b Ball conversion means
5c Wiring corner conversion means
5d 1st wire conversion means
5e Wiring pattern conversion means
5f Second wire conversion means
6 Information storage means for analysis
7 Analysis means
10 Automatic layout simplification device
20 Layout design CAD equipment
30 Input device
40 Display Device 100 Semiconductor Device 101 Wiring Substrate 101a Top Surface 102 Semiconductor Chip 102a Terminal 103, 113 Bonding Wire 103a Bond Finger 103b Bending Part 103c, 113c Straight Line Part 113d Bending Part 113e Side Face 104, 114 Ball 105, 115 Via 106 Wiring Pattern 106a 116a Corner 106b Linear pattern 106c Edge

Claims (5)

In an automatic layout simplification device that verifies the characteristics of a semiconductor device in which a semiconductor chip is mounted on a wiring board by bonding wires,
Layout information storage means for storing layout information of each component in the semiconductor device;
Net figure acquisition means for acquiring a figure by a net that is connection information between terminals from the layout information stored in the layout information storage means;
Layer graphic acquisition means for acquiring, for each layer, a figure corresponding to each layer of the wiring board among the figures by the net that is connection information between terminals, from the layout information stored in the layout information storage means;
Conversion graphic information storage means storing conversion graphic information for simplifying the graphic;
Automatic simplification processing means for simplifying the figure having a curved surface or a curve to a figure having a plane or a straight line based on the converted figure information stored in the converted figure information storage means;
Analysis information storage means for storing connection information inside the semiconductor chip, delay value, operating conditions, electrical characteristics or power consumption, or information for analyzing the viscosity of the sealing material;
Analysis means for executing a simulation based on graphic information from the automatic simplification processing means, analysis information from the analysis information storage means, and layout information from the layout information storage means;
An automatic layout simplification device characterized by comprising: In the automatic layout simplification device according to claim 1,
Simulation type selection means for selecting the type of simulation to be verified based on the input information;
Based on the selection information of the simulation type selection means, net figure acquisition means for acquiring a figure by a net that is connection information between terminals from the layout information;
With
The automatic simplification processing means extracts a portion corresponding to a via from the acquired graphic and converts it into a rectangular parallelepiped based on the converted graphic information, and extracts a portion corresponding to the ball from the acquired graphic. Ball converting means for converting to a cube based on the converted graphic information, extracting a portion corresponding to the bonding wire from the acquired graphic, and connecting a plurality of rectangular parallelepipeds using the bending portion of the bonding wire as a bent portion based on the converted graphic information And a wire corner for extracting a portion corresponding to the corner of the wiring pattern from the acquired figure and converting it into a bent shape based on the converted figure information. An automatic layout simplification device characterized by being a conversion means. In the automatic layout simplification device according to claim 1 or 2,
Simulation type selection means for selecting the type of simulation to be verified based on the input information;
Based on the selection information of the simulation type selection means, layer graphic acquisition means for acquiring, for each layer, the graphic corresponding to each layer of the wiring board among the figures by the net that is the connection information between the terminals,
With
The automatic simplification processing means extracts a portion corresponding to a via from the acquired graphic and converts it into a rectangular parallelepiped based on the converted graphic information, and extracts a portion corresponding to the ball from the acquired graphic. Ball converting means for converting into a cube based on the converted graphic information, a portion corresponding to the wiring pattern in the acquired graphic is extracted for each grid in each layer of the wiring board, and the wiring pattern in each grid is based on the converted graphic information A wiring pattern conversion means for converting the pattern into a square having the same area as the total area of the wiring patterns in each grid, and extracting a plurality of the bonding wires generated from the same side on the upper surface of the semiconductor chip from the acquired figure Based on the converted graphic information, a plurality of straight portions are formed into one rectangular body for each bending portion of the bonding wire. Automatic layout simplified apparatus which is a second wire conversion means for to conversion. In the automatic layout simplification device according to claim 2 or 3,
The conversion figure of the part corresponding to the via is a rectangular parallelepiped in which the height of the via before conversion and the height of the converted via coincide with the square circumscribed or inscribed on the bottom of the via before conversion, or the via before conversion The center of the bottom of the base coincides with the center of the bottom of the via after conversion, the height of the via before conversion and the height of the via after conversion match, and the volume of the via before conversion and the volume of the via after conversion An automatic layout simplification device, characterized in that they are rectangular parallelepipeds that match. In the automatic layout simplification device according to any one of claims 2 to 4,
The converted figure of the part corresponding to the ball is a cube circumscribing or inscribed to the ball before conversion, or the center of the ball before conversion and the center of the ball after conversion match, and the volume of the ball before conversion and after conversion An automatic layout simplification device, characterized in that it is a cube whose volume of the ball matches.

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