JP2003030264A - Method and device for arranging lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a designer to perform rearranging work with high efficiency by clearly displaying information about a critical path in a state the arrangement position of a block is changed/corrected. SOLUTION: An LSI arranging method has a step S1 for reading circuit information as read information, a step S2 for displaying the arrangement information of the block on the basis of the read information, a step S3 for selecting one unarranged or arranged block, a step S4 for temporarily and provisionally arranging the selected block at a desired arrangement place, a step S5 for performing a simple delay calculation to calculate a wiring delay value, a step S6 for comparing the delay value obtained in the step S5 with a delay constraint value and recognizing wiring in which the delay value is larger as a critical path to display the wiring, a step S7 for deciding whether a block position is proper on the basis of critical path information, a step S8 for making the a block arrangement position a determined position, and a step S9 for deciding whether all blocks have been arranged and finishing the processing in the case no unarranged block exists.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI arranging method and apparatus, and more particularly to an LSI arranging method and apparatus in an LSI layout (floor plan) design.

[0002]

2. Description of the Related Art With the progress of LSI technology, it has become possible to manufacture high-performance and high-speed logic LSIs. In order to develop these logic LSIs, it is necessary to confirm the speed performance of the logic LSI at the design stage. For this reason, automatic layout (layout) design considering timing is performed from the floor plan stage in LSI design,
It is common to perform a simulation based on the layout result, detect a critical path that is a wiring path that exceeds a delay constraint value given in advance, and perform a re-layout to eliminate the critical path.

As an example of this type of LSI placement device,
Referring to FIG. 15 showing a block diagram of a conventional LSI placement device described in Japanese Patent Application Laid-Open No. 4-251961, a control unit 9 for controlling the entire device is shown in this conventional LSI placement device.
1 and a logical delay calculation unit 92 that calculates a logical delay value,
A critical path determination unit 93 that determines a critical path by comparing a logical delay value and a circuit constraint condition, and a block arrangement that arranges blocks so that a wiring delay is equal to or less than a limit value by referring to logical connection information and critical path information. Section 94 and storage means 9 for storing various information necessary for arrangement
9 and.

The storage means 99 comprises logical connection information 95, logical delay information 96, critical path information 97, and placement results 98 for storing placement results.

Next, referring to FIG. 15 and FIG. 16 which is a flow chart showing the processing flow of the conventional LSI placement device, the conventional LSI placement method which is the operation of the conventional LSI device will be described. The logical connection information 95 is read from the means 99 (step P1), and the logical delay calculation unit 92 calculates the logical delay value based on the logical connection information (step P2).

Next, the critical path determination unit 93 compares the calculated logical delay value with a predetermined circuit constraint condition, selects a critical path, and stores it in the critical path information 97 (step P3).

Finally, the block placement section 94 refers to the logical connection information 95 and the critical path information 97 and places blocks as follows. That is, the blocks that form the critical path are arranged so that the wiring delay is equal to or less than the limit value (step P4), and the blocks that do not form the critical path are arranged so that the wiring becomes easy. (Step P5).

However, the conventional LSI arranging method and apparatus have the following problems.

The first problem is that the prior art cannot reduce the number of times of redoing the placement work (the number of trials).

The reason is that in the prior art, the block layout position is automatically determined.

In general, no matter what delay calculation method is used, it is impossible to obtain a completely accurate delay value because there is no information on actual placement and routing at the stage of floorplanning. Even if the automatic placement considering the timing is performed at the floor plan stage, there is no guarantee that the result will be directly reflected in the reduction of the number of detected critical paths.

Furthermore, in the situation where the circuit scale is increasing as in recent years, it is rare enough to say that it is impossible to create a layout that satisfies all of them with a single automatic layout. In most cases, it is necessary to correct the arrangement position of the block, but in the conventional technique, the automatic arrangement is always performed by the same algorithm, and therefore the improvement of the arrangement cannot be expected.

[0013]

DISCLOSURE OF THE INVENTION The conventional LSI described above
Although the placement method and apparatus of (1) automatically determine the placement position of the block, it is impossible to obtain a completely accurate delay value because the information of the actual placement and routing does not exist at the stage of floorplanning. Even if the automatic placement considering the above is performed at the floor plan stage, the result is not directly reflected in the reduction of the number of detected critical paths, so that the number of trials of the placement work cannot be reduced.

Further, in the recent situation of large circuit scale,
It is almost impossible to create a layout that satisfies all with one automatic placement. In most cases, it is necessary to correct the placement position of the block, but in the conventional technology, there is no room for the designer to participate. However, there is a drawback that improvement of the arrangement cannot be expected because the automatic arrangement is always performed by the same algorithm.

An object of the present invention is to provide an LSI placement method that enables a designer to perform a high-efficiency relocation work by displaying information regarding a critical path in a state where a block placement position is changed or corrected in an easy-to-understand manner. To provide a device.

[0016]

L of the invention according to claim 1
The SI arranging method is as follows. In the LSI arranging method of arranging blocks in a floor plan which is a layout design of an LSI, a block to be arranged is arranged at a desired place for arrangement, and this arrangement position is temporarily determined, To obtain delay information about the block by performing dynamic delay calculation, extract a critical path that is a wiring path that exceeds a delay constraint value given in advance from the delay information, and extract the block including the extracted critical path. Is displayed on the display screen, and the arrangement position of the block is corrected so that the critical path is eliminated.

According to a second aspect of the present invention, in the method of arranging the LSI according to the first aspect, the delay calculation multiplies the wiring length by a predetermined delay coefficient of each wiring to obtain a delay value of the wiring. It is characterized in that it seeks.

According to a third aspect of the invention, in the method of arranging the LSI according to the first aspect, the display screen divides the delay value of each wiring into groups in a predetermined range, and the delay value is a parameter. It is characterized by displaying a histogram in which the number of wirings corresponding to is represented by a bar graph.

According to a fourth aspect of the present invention, in the method of arranging the LSI according to the first aspect, the display screen highlights the critical path according to the degree to which the delay constraint value is exceeded. It is a feature.

According to a fifth aspect of the present invention, there is provided an LSI arranging method, wherein in the LSI arranging method for arranging blocks in a floor plan, which is a layout design of the LSI, information regarding a circuit to be the floor plan is used as read information. An information reading step of reading, a block displaying step of displaying the placement information of the first block including the placement position of the block on the display screen based on the reading information, and a block selecting step of selecting one unplaced block or one already placed block And a placement temporary fixing step of temporarily arranging the block selected in the block selecting step at a desired location to place it in a temporary fixed state, and executing a simple delay calculation after the block is brought into the temporary fixed state and wiring. And a simple delay calculating step for obtaining a delay value of The extension value and the delay constraint value included in the read information are compared, the wiring having the larger delay value is recognized as a critical path, and the placement information of the second block including the recognized critical path is displayed on the display screen. With reference to the critical path information display step of displaying and the information of the critical path displayed on the display screen, it is determined whether the position of the block is valid, and if the position of the block is not valid, the block is selected. Returning to the step, when the placement position validity determining step and the placement position validity determining step determine that the placement position of the block is appropriate, all the blocks It is judged whether or not the block has been placed, and if there is an unplaced block, the process returns to the block selection step and the Case is characterized in that it has a termination determination step for terminating the process.

According to a sixth aspect of the invention, in the LSI arranging method according to the fifth aspect, the read information is block connection state information in which input and output connection destinations of each block and connection wirings thereof are connected. The logical connection information including the block, the layout information including the block specific information that is the information of the shape size coordinate position specific to each block, and the delay coefficient required for calculating the delay constraint value and the delay value imposed on the wiring. And delay information including.

According to a seventh aspect of the present invention, in the method of arranging the LSI according to the fifth aspect, the simple delay calculating step determines positions of both ends of the wiring connected to the block due to the arrangement of the block. A wiring extraction step of extracting a target wiring which is a fixed wiring or a moved wiring, a both-end coordinate inspection step of checking coordinate positions of both ends of the target wiring from the read information, and a coordinate position of both ends of the target wiring It is characterized by including a wiring length calculation step of calculating a wiring length and a wiring delay value calculation step of multiplying the wiring length by a predetermined delay coefficient to calculate a delay value of the target wiring.

The invention according to claim 8 is the method for arranging LSIs according to claim 5, wherein the critical path information display step groups the delay values of the respective wirings into groups in a predetermined range on the display screen. And a histogram in which the number of wirings corresponding to the delay value as a parameter is represented by a bar graph is also displayed.

According to a ninth aspect of the present invention, in the LSI placement method according to the fifth aspect, a delay value based on the delay constraint value is set between the critical path information displaying step and the placement position validity determining step. It is characterized in that a critical path extracting step for extracting the critical path which is a large wiring and a critical path highlighting step for highlighting the extracted critical path on the screen are inserted.

The invention according to claim 10 is the same as claim 5
In the LSI arranging method described above, the critical path information display step includes a wiring direction classification step of classifying the wirings connected to the block according to a designated direction, and each wiring classified by the wiring direction classification step. hand,
A histogram creation step to create a histogram,
And a histogram display step of displaying the created histogram.

The invention according to claim 11 is the invention according to claim 7.
In the described LSI arranging method, the wiring length calculating step obtains the length of a line segment connecting two coordinates on a plane by the Manhattan distance method.

The invention according to claim 12 is the invention according to claim 7.
In the LSI arranging method described above, the wiring length calculating step obtains the length of a line segment connecting two coordinates on a plane by the Steiner tree method.

According to a thirteenth aspect of the present invention, there is provided an LSI placement device for arranging blocks in a floor plan, which is a layout design of the LSI, which operates by an input device including a keyboard and a mouse and program control. A data processing device, a storage device for storing various kinds of information, and an output device including a display, wherein the data processing device includes logical connection information including a netlist, layout information such as a size of each block, and a critical path. Layout information management means for managing the layout positions of all blocks by receiving the delay information necessary for determining, and analyzing the logical connection information, the layout information and the delay information and outputting the analysis result, The changed layout position when the layout position of the block is changed by input from the input device Information to analyze the information and output the changed arrangement position information, and display the result on the output device, and a simple delay calculation based on the arrangement information when the arrangement position of the block is temporarily determined. A logical connection information storage means for storing the analysis result from the layout information management means, the delay device including a delay calculation means for outputting a delay calculation result and a delay information management means for managing critical path information; An arrangement information storage unit that stores arrangement information including arrangement positions of all blocks and the changed arrangement position information, and a delay information storage unit that stores delay information including the delay calculation result.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings.

In the LSI arranging method and apparatus of the present embodiment, in the LSI arranging method for arranging blocks in the floor plan which is the layout design of the LSI, the blocks to be arranged are arranged at desired places for arrangement, This placement position is set to a provisionally determined state, simple delay calculation is executed to obtain delay information regarding the block, and a critical path that is a wiring route that exceeds a delay constraint value given in advance is extracted from the delay information. , By displaying the layout information of the block including the extracted critical path on the display screen and modifying the layout position of the block so that the critical path is resolved, the critical path in the state where the block layout position is changed or modified It is characterized by providing a configuration that makes it possible for designers to display information related to Is shall.

What is important here is that, unlike the automatic placement program, the present invention is to provide (display) information to the designer in an easy-to-understand manner, and leave the final determination of the placement position to the designer. It means that it is being done.

In this way, by displaying the information of the critical path in an easy-to-understand manner each time the block is arranged,
Allows you to give one guideline for creating a layout with no critical paths.

Next, the LSI according to the first embodiment of the present invention
2 which is a block diagram of the arrangement device of FIG. 1, the LSI arrangement device of the present embodiment shown in this figure includes an input device 1 such as a keyboard and a mouse, a data processing device 2 that operates under program control, and various types of devices. A storage device 3 for storing information and an output device 4 such as a display are provided.

The data processing device 2 includes a layout information management means 21 for managing the layout positions of all blocks, a layout position changing means 22 for changing the block layout positions, and a delay calculating means 23 for performing a simple delay calculation. And delay information management means 24 for managing the critical path information.

The storage device 3 is a logical connection information storage means 31 for storing logical connection information obtained from a net list or the like.
And a placement information storage means 32 for storing placement information including placement locations of all blocks, and a delay information storage means 33 for storing delay information including a delay calculation result.

Further, as external information input to the LSI placement device, logical connection information 11 such as a netlist, layout information 12 such as the size of each block, and delay information 13 necessary for determining a critical path. Have and.

With reference to FIG. 2, a description will be given of a schematic operation including mutual relations of the above-mentioned means of the present embodiment.
First, the arrangement information management means 21 of the data processing device 2 has the logical connection information 11, the layout information 12, and the delay information 1.
3, the logical connection information 11, the layout information 12, the delay information 13 and the like are analyzed, and the analysis result is stored in the logical connection information storage means 31, the layout information storage means 32 and the delay information storage of the storage device 3. It stores in each of the means 33. At the same time, these pieces of information are supplied to the output device 4 and displayed on a display or the like.

Next, the designer inputs the input device 1 such as a mouse.
When the arrangement position of the block is changed by using, the arrangement position changing unit 22 analyzes the changed arrangement position information, outputs the changed arrangement position information, and the arrangement information storage unit 32.
To store. At the same time, the result is displayed on the output device 4.

When the designer places the block layout position in the tentatively fixed state, the delay calculation means 23 performs a simple delay calculation based on the current layout information, and stores the calculation result in the delay information storage means 33. To do.

The delay information management means 24 takes out the information of the critical path in the current block arrangement state from the delay information storage means 33, arranges it in an easy-to-understand form such as a histogram format, and presents it to the designer through the output device 4. .

Next, referring to FIG. 1 which is a flow chart showing the processing flow of this embodiment, the LSI of this embodiment
Explaining the entire operation of the arrangement method in detail, first, the information (hereinafter referred to as read information) regarding the circuit to be the floor plan is read (information read step S1). Here, the read information is the logical connection information 11, the layout information 12, and the delay information 13.

The logical connection information 11 includes block connection state information indicating how each block is connected. For example, "input terminal A1 of block A and block B
The output terminal B2 of is connected by the wiring N1 ”.

The layout information 12 includes block-specific information that is information on the shape, size, and coordinate position specific to each block. For example, "the block A is a quadrangle having a size of vertical X and horizontal Y", "the center of the block A has coordinates (X1, Y
It is arranged in 1) ”. These pieces of information are mainly used when the block is displayed on the output device 4.

The delay information 13 includes the constraint value of the delay imposed on the wiring and the delay coefficient necessary for calculating the delay value. For example, it is information that "when passing through the wiring N1, it should be 0.01 nanoseconds or less" and "the delay value per unit length of the wiring of this material is 0.02 nanoseconds". This information calculates the delay value of the wiring,
It is used to judge whether or not it is a critical path.

Next, based on the read information read in step S1, the position of the block is displayed as block layout information on the output device 4 (block display step S2).
Blocks whose positions have not been determined are displayed on another screen as unplaced blocks. In the initial state, all blocks are in a non-arranged state.

Next, the designer uses the input device 1 such as a mouse to select one unplaced block which is not yet arranged. Alternatively, one already-arranged block that is already arranged is selected (block selecting step S3). The arrangement position of the block selected here is determined in the subsequent processing.

Next, the block selected in step S3 is temporarily placed at a desired location by using the input device 1 such as a mouse (temporary placement confirmation step S4). Since the arrangement here is temporary, it is called a "temporary fixed state".

When the block is in the tentatively determined state, a simple delay calculation is executed to obtain a wiring delay value (simple delay calculation step S5).

The simple delay calculating method will be described with reference to FIG. 3, which shows the details of the simple delay calculating step S5. First, among the wirings connected to the block, the block is arranged, The wiring whose position is confirmed or the moved wiring is extracted (wiring extraction step S51).

From the information read in step S1, the coordinate positions of both ends of the above wiring are checked (both ends coordinate check step S52).

The wiring length is calculated from the coordinate positions of both ends of the wiring. The length of the line segment connecting the two coordinates on the plane can be simply obtained by a method such as the "Manhattan distance" method or the "Steiner tree" method (wiring length calculation step S5.
3).

The value obtained by multiplying the wiring length obtained in step S53 by the delay coefficient becomes the delay value of the wiring (wiring delay value calculation step S54).

The processing from step S51 to step S54 is performed for all wirings connected to the block (processing end determination step S55).

Next, referring to the calculation result of step S5,
The delay value obtained in step S5 is compared with the delay constraint value obtained in step S1, and the wiring having the larger delay value is recognized as a critical path. Information on these delay values is obtained for all the blocks, and for example, a histogram (frequency distribution table) in which the delay values are arranged in the Y-axis direction as parameters and the number of wires for each delay value is displayed in a graph in the X-axis direction ) Is created and displayed on the output device 4 together with the block layout information (critical path information display step S
6).

Referring to FIG. 4 which is an explanatory view showing an example of a screen display including the histogram H1, in this example, the vertical (Y)
The number of wires for each delay time shown in the axial direction is represented by the length of the bar graph in the horizontal (X) axis direction.

The designer refers to the information of the critical path displayed on the output device 4 to determine whether or not the current block position is valid (placement position validity determining step S).
7). Instead of automatically moving to the optimum position on the program side, displaying the current critical path status is a guideline for the designer to create a better layout. If the position of the block is not appropriate and it is desired to move to another place, the process returns to the process of selecting the block (block selecting step S3). If it is determined that the block layout position is appropriate, the process proceeds to the next process.

When it is determined in step S7 that the layout position of the block is appropriate, the designer sets the layout position of the block in a fixed state (layout position fixing step S8).

When the position of the block is determined, the new layout position is written in the layout information 12. It is determined whether or not all the blocks have been arranged. If there is a block that has not been arranged, the process returns to the process of selecting another block (block selection step S3), and if there is no block, the process ends (end judgment). Step S9).

This operation is repeated for all blocks.

Even when a hierarchical design is performed,
Steps S1 to S9 for each layer (for each macro)
By repeating the processes up to, the entire circuit can be processed.

Next, referring to FIG. 5 showing a block diagram of an example of the logical connection information 11, a specific operation of this embodiment will be described. First, the arrangement information management means 21.
Reads the logical connection information 11 and the delay information 13 before starting the block placement, and creates a list of delay constraint values for each wiring (step S1). For example, in FIG.
When the logical connection information as shown in is read, the delay constraint value list is as shown in FIG.

Referring to FIG. 5, in this figure, blocks B1 to B5 to be arranged, wirings N1 to N9, external input terminals IN1 and IN2, and external output terminal OUT are shown.
1 and OUT2 are shown.

FIG. 6 is a table showing a list of delay constraint values.
Referring to (A), this figure shows delay constraint values for each of the wirings N1 to N9. The delay constraint values shown in this figure are shown in parentheses for each corresponding wire in FIG.

Further, the delay coefficient (delay value per unit length) used in the simple delay calculation is also read before starting the block arrangement. The delay coefficient is a value that is uniquely determined by the material used for wiring (such as aluminum), and may be determined by transistor-level circuit simulation, or by making a prototype to actually measure the delay value.

Next, the layout information 12 is read, the size information of each block and the information of the already arranged blocks are acquired, and displayed on the graphic display (step S2).

Referring to FIG. 7 showing an example of the graphic display, FIG. 7A shows a block B1.
Indicates that only the block B2 is already arranged and the other blocks are not arranged.

Using the input device 1 such as a mouse, one block is selected from the unarranged blocks or one block to be moved is selected from the already arranged blocks (step S3). FIG. 7B shows a state in which the unplaced block B3 is selected.

Next, the selected block is placed in a desired place and put in a provisional fixed state (step S4). There is no limitation on the method of setting the temporary fixed state, but for example, it is performed by single-clicking the mouse.

When the placement position of the block is in the tentatively determined state, the delay value is recalculated for the wiring connected to the block (step S5). The wiring that may have changed the delay value is only the wiring that is directly connected to the target block (because other wiring has not moved). The delay value of the wiring is simply calculated by “wiring length × delay coefficient”. Since the coordinates of both ends are fixed, the wiring length is simply substituted by the Manhattan distance or the distance obtained by the Steiner tree. Here, the method for obtaining the wiring length does not matter. For one delay coefficient, one that is read in advance as a uniform coefficient is used (determined by technology and wiring material).

The delay value of the wiring recalculated in this way is reflected in the list. For example, in FIG. 7B, assuming that the block B3 is in the tentative confirmation state, the block B3
The wiring directly connected to is wiring N4, N5, N6, N7
Therefore, a simple delay value is obtained for these four wirings.

Referring to FIG. 8 showing an example of the simple delay calculation, the wiring length of the wiring N4 shown in the example of this figure is obtained by the Manhattan distance, and the difference between the X coordinate and the Y coordinate at both ends is calculated. The sum of the values, ie 3.0 nm and 2.0 nm
Which is 5.0 nm. Further, if the delay coefficient is 0.5, the delay value of the wiring N4 is 5.0 × 0.5 =
It becomes 2.5 ns.

Next, the calculation result is stored in the "simple calculated delay value" column of the list. If the delay value of the wiring N4 is 2.
Assuming that the delay value of the wiring N5 is 5 ns, the delay value of the wiring N5 is 2.8 ns, the delay value of the wiring N6 is 2.0 ns, and the delay value of N7 is 2.5 ns, the list shown in FIG. ) Will be rewritten as.

Referring to this figure, the wirings N4 and N5 are
Since each has a delay value larger than the delay constraint value, it can be seen that both are critical paths.

Here, the delay value of each wiring connected to the block in the temporarily determined state is displayed as a histogram (frequency distribution table) on the screen (step S6).

In the histogram, the delay value of each wiring is divided into groups within a predetermined range, and as described above, Y
The delay value, which is a parameter in the axial direction, is a bar graph in which the number of wirings is taken in the X-axis direction. For example, if there is a block connected to 30 wires, it is assumed that the distribution of delay values of the 30 wires is as shown in FIG. 9 (A). In this case, the histogram for this block is as shown in FIG. With such a display, the distribution state of the delay value of the wiring can be visually grasped, and it can be one guideline for judging whether or not the current provisional fixed position is appropriate in terms of timing. It is obvious that the X and Y axes may be reversed from the above.

In the present embodiment, the format for displaying the delay value is not limited to the histogram. Any format that is easy for the designer to understand is acceptable.

The displayed delay value is confirmed on the screen (step S7), and if there is a problem with the arrangement position, the block position is corrected. If there is no problem, the temporary fixed state is changed to the fixed state (step S8), and the information of the block layout position is written in the layout information 12.

The above processing is repeated until the arrangement and movement of all blocks are completed (step S9).

In this way, the occurrence status of the critical path can be confirmed in the histogram every time the block is temporarily set, and the designer can determine the layout position of the block while looking at it.

As described above, the effect of the present embodiment is that the number of times of redoing the placement work (the number of trials) and the number of steps can be reduced.

The reason is that the detection of the critical path is performed at the stage of the floor plan, and the result is displayed in a histogram or the like, so that whether or not the block layout position is appropriate in timing while performing the floor plan is determined. This is because it is easier for the designer to make a decision than in the past.

In the layout design of the medium scale circuit,
Re-working of the floor plan due to the detection of the critical path occurs 4 to 5 times, and it takes about 3 days for one re-working.

According to the present invention, the number of redoing is infinite
Since it is close to the number of times, it is possible to save man-hours for about 10 days.

Next, referring to FIG. 10 which is a flowchart showing the critical path information display step S6A which characterizes the second embodiment of the present invention, the first embodiment of the present embodiment shown in this figure is described. The difference is that
In the critical path information display step S6 of this embodiment, only one histogram for a block is created and displayed. However, in the critical path information display step S6A of this embodiment, further details regarding the moving direction of the block are given. As a guide, multiple histograms are displayed for each direction.

The operation of the critical path information display step S6A of the present embodiment will be described with reference to FIG. 10. First, in the wiring direction classification step S61, the wirings connected to the block are classified by the designated direction. Classify. Next, a histogram is created for each wiring classified in step S61 (histogram creation step S62). The last created histogram is displayed (histogram display step S63).

A specific example of creating a histogram in four directions (upper right, lower right, upper left, lower left) will be described below. Although an example of creating four histograms will be described here, the number of histograms is not limited.

An example of the wiring direction classification method will be described with reference to FIG. 11, which is an explanatory diagram. First, the wiring direction classification method will be described. Are divided into four areas according to the direction. The plane is divided into four by a horizontal straight line (dividing line L1) and a vertical straight line (dividing line L2) passing through the center of the block, and the upper left, upper right, lower left,
Define the "bottom right" area. Next, it is checked to which of the four defined areas the coordinates of the connection destination of the wiring connected to the block belong. For example, since the wiring N11 is connected to the upper right block, it becomes the "upper right" region.
Similarly, the wirings N12 and N13 are "lower right", the wiring N14 is "upper left", and the wiring N15 is "lower left" (step S6).
1).

Next, the wiring is classified as described above, a histogram is created for each area, and the histogram is displayed in four directions centering on the block (step S62).

Referring to FIG. 12 which is an explanatory diagram showing an example of a four-direction histogram display, each of the four histograms HR1, HR2, HL1 and HL2 shown in FIG. The histograms of the "upper left" and "lower left" wiring areas are shown. These histograms show the information that "the situation of the delay value in this direction is like this", that is, the information of the delay focused on a specific direction. Will be provided. Based on this information, the designer can determine "in which direction the critical path exists and to what extent" and "in which direction the block should be moved".

Next, referring to FIG. 13, which is a flowchart similarly showing the third embodiment of the present invention, in which components common to those of FIG. 1 are designated by common reference characters / numerals, and shown in this figure. The difference between the present embodiment and the first embodiment described above is that a critical path extraction step S11 and a wiring emphasis display step S12 are provided between the critical path information display step S6 and the placement position validity determination step S7. It is inserted.

With reference to FIG. 13, the process of the present embodiment will be described by focusing on the differences from the first embodiment. A simple delay calculation will be carried out for a block in the temporarily fixed state. (Step S5), a histogram is displayed (step S6), and then a wiring (critical path) having a delay value larger than the delay constraint value is extracted with reference to the list (critical path extraction step S11).

Next, the extracted critical path is highlighted on the screen (critical path highlighting step S
12). At that time, different colors and thicknesses are highlighted according to the extent to which the delay constraint value is exceeded.

Referring again to FIG. 6B, a concrete example in which the critical path is highlighted will be described. From this figure, it can be seen that the wirings exceeding the delay constraint value, that is, the critical paths are the wirings N4 and N5. It can be easily determined (step S11). Next, these critical paths are classified as follows with respect to the difference with the delay constraint value.

That is, the difference from the delay constraint value is 0.5 ns.
Is less than, the difference with the delay constraint value is 0.5 ns or more and less than 2.0 ns, and the difference with the delay constraint value is 2.0 ns or more. For example, as shown in FIG. 14, they are sequentially displayed on the screen in “yellow”, “orange”, and “red” (step S12).

Referring to FIG. 14 showing an example of the critical path highlighting display, the wiring N4 has a constraint value of 0.5.
Since it exceeds ns, it is highlighted in "red". Since the wiring N5 exceeds the constraint value by 0.2 ns, it is highlighted in "yellow".

As described above, when the critical path is displayed on the screen, the color is changed according to the degree to which the delay constraint value is exceeded, so that more detailed information on the critical path (path route, related block, degree of violation) is displayed. ) Also can be visually confirmed, and an effect that the block whose layout is to be corrected can be intuitively recognized is obtained.

[0097]

As described above, according to the method and apparatus for arranging an LSI of the present invention, a block to be arranged is arranged at a desired position for arrangement, and this arrangement position is set to a temporary fixed state,
Obtain a delay information about the block by performing a simple delay calculation, extract the critical path from the delay information, display the placement information of the block including the extracted critical path on the display screen, the critical path is By correcting the placement position of the above block to eliminate it, the critical path is detected at the floorplan stage, and the result is displayed in a histogram etc. Since it becomes easier for the designer to judge whether or not it is appropriate, there is an effect that the number of trials of the placement work and the number of man-hours can be reduced.

[Brief description of drawings]

FIG. 1 is a flowchart showing an embodiment of an LSI placement method of the present invention.

FIG. 2 is an L for executing the LSI placement method of the present embodiment.
It is a block diagram which shows the arrangement | positioning apparatus of SI.

FIG. 3 is a flowchart showing details of a simple delay calculation step.

FIG. 4 is an explanatory diagram showing an example of a screen display including a histogram.

FIG. 5 is a block diagram showing an example of logical connection information.

FIG. 6 is a diagram showing a list of delay constraint values and simple delay calculation results in a table format.

FIG. 7 is an explanatory diagram showing an example of a graphic display.

FIG. 8 is an explanatory diagram showing an example of a simple delay calculation.

FIG. 9 is an explanatory diagram showing an example of a histogram creating method.

FIG. 10 is a flowchart showing a critical path information display step which characterizes the second embodiment of the present invention.

FIG. 11 is an explanatory diagram showing an example of a wiring direction classification method.

FIG. 12 is an explanatory diagram showing an example of display of histograms in four directions.

FIG. 13 is a flowchart showing a third embodiment of the present invention.

FIG. 14 is an explanatory diagram showing an example of critical path emphasis display.

FIG. 15 is a block diagram showing an example of a conventional LSI placement device.

FIG. 16 is a flowchart showing an example of a conventional LSI placement method.

[Explanation of symbols]

1 Input Device 2 Data Processing Device 3 Storage Device 4 Output Device 11, 95 Logical Connection Information 12 Layout Information 13 Delay Information 21 Layout Information Management Means 22 Layout Position Changing Means 23 Delay Calculation Means 24 Delay Information Management Means 31 Logical Connection Information Storage Means 32 placement information storage means 33 delay information storage means 91 control section 92 logical delay calculation section 93 critical path determination section 94 block placement section 96 logical delay information 97 logical path information 98 placement result 99 storage means B1 to B5 blocks H1, HR1, HR2 , HL1, HL2 Histograms N1 to N9 Wiring IN1, IN2 External input terminals OUT1, OUT2 External output terminals

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/82 H01L 21/82 C W (72) Inventor Hideyuki Okabe 1-chome, Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa No. 403 53 NFC System Stock Company Internal F-term (reference) 5B046 AA08 BA05 DA01 GA01 HA09 JA01 5F064 DD02 DD03 DD24 EE02 EE03 EE08 EE47 HH06 HH09 HH12

Claims (13)

[Claims] 1. A method of arranging blocks for arranging blocks in a floor plan, which is a layout design of a LSI, in which blocks to be arranged are arranged at desired positions,
This placement position is set to a tentatively determined state, simple delay calculation is performed to obtain delay information regarding the block, and a critical path that is a wiring route that exceeds a delay constraint value given in advance is extracted from the delay information. A method for arranging an LSI, wherein the arrangement information of the block including the extracted critical path is displayed on a display screen, and the arrangement position of the block is corrected so that the critical path is eliminated. 2. The L according to claim 1, wherein the delay calculation calculates a delay value of the wiring by multiplying a wiring length by a predetermined delay coefficient of each wiring.
SI placement method. 3. The display screen displays a histogram in which the delay value of each wiring is divided into groups in a predetermined range and the number of wirings corresponding to the delay value which is a parameter is represented by a bar graph. The method for arranging the LSI according to claim 1, wherein. 4. The method of arranging LSIs according to claim 1, wherein the display screen highlights the critical path in accordance with the degree to which the delay constraint value is exceeded. 5. An LSI arranging method for arranging blocks in a floor plan, which is a layout design of an LSI, comprising: an information reading step of reading information on a circuit to be the floor plan as read information; and based on the read information. The block display step of displaying the placement information of the first block including the placement position of the block on the display screen, the block selection step of selecting one unplaced block or the already placed block, and the block selected in the block selection step Placement temporarily determining step of temporarily placing in a desired place and placing it in a provisionally determined state; and a simple delay calculation step of performing a simple delay calculation after the block is in the provisionally determined state to obtain a delay value of wiring, The delay value included in the read value and the delay value obtained in the simple delay calculation step. A critical path information displaying step of comparing a wiring with a larger delay value as a critical path by comparing with a reduction value and displaying placement information of a second block including the recognized critical path on the display screen; Referring to the information of the critical path displayed on the display screen, determine whether the position of the block is appropriate,
When the position of the block is not appropriate, the process returns to the block selecting step, and the placement position validity determining step is performed; and when the placement position of the block is determined to be valid in the placement position validity determining step, the placement position of the block is determined. And an end determination step of determining whether or not all blocks have been placed, returning to the block selecting step if there is an unplaced block, and ending the processing if not present. A method for arranging an LSI characterized by the above. 6. The read information includes logical connection information including block connection state information which is information of connection destinations of input and output of each block and connection wirings thereof, and information of a shape size coordinate position unique to each block. 6. The LSI according to claim 5, including layout information including certain block-specific information, and delay information including a delay value imposed on wiring and a delay coefficient necessary for calculating a delay value. Arrangement method. 7. A wiring extraction step in which the simple delay calculation step extracts a target wiring whose positions at both ends are fixed or moved among the wirings connected to the block by the placement of the block. A double-sided coordinate checking step for checking the coordinate positions of both ends of the target wiring from the read information; a wiring length calculating step for calculating a wiring length from the coordinate positions of the both ends of the target wiring; and a delay predetermined for the wiring length. 6. A method for arranging an LSI according to claim 5, further comprising a wiring delay value calculation step of multiplying a coefficient to calculate a delay value of the target wiring. 8. The step of displaying critical path information comprises:
6. The delay value of each wiring is divided into groups in a predetermined range on the display screen, and a histogram in which the number of wirings corresponding to the delay value as a parameter is represented by a bar graph is also displayed together. Arrangement method of the described LSI. 9. A critical path extracting step of extracting the critical path, which is a wiring having a delay value larger than the delay constraint value, between the critical path information displaying step and the placement position validity determining step, 6. The method of arranging LSIs according to claim 5, further comprising: inserting a critical path highlighting step for highlighting the critical path on the screen. 10. The critical path information displaying step classifies wirings connected to the block according to a designated direction, and a histogram for each wiring classified in the wiring direction sorting step. 6. The L according to claim 5, further comprising: a histogram creating step for creating the histogram, and a histogram displaying step for displaying the created histogram.
SI placement method. 11. The method of arranging an LSI according to claim 7, wherein the wiring length calculating step obtains a length of a line segment connecting two coordinates on a plane by the Manhattan distance method. 12. The method of arranging an LSI according to claim 7, wherein the wiring length calculating step obtains a length of a line segment connecting two coordinates on a plane by the Steiner tree method. 13. An LSI arranging device for arranging blocks in a floor plan, which is a layout design of an LSI, comprising: an input device including a keyboard and a mouse; a data processing device operated by program control; and a memory for storing various information. A device and an output device including a display, and the data processing device supplies logical connection information including a netlist, layout information such as the size of each block, and delay information necessary for determining a critical path. Layout information management means for managing the layout positions of all blocks by analyzing the logical connection information, the layout information and the delay information and outputting the analysis result; and the layout position of the blocks by the input from the input device. When you change, the changed placement position information is analyzed and the changed placement position information is output. And a placement position changing unit that displays the result on the output device, and a delay calculation unit that outputs a delay calculation result by performing a simple delay calculation based on the placement information when the placement position of the block is temporarily set. A logical connection information storage unit for storing the analysis result from the arrangement information management unit, an arrangement location for all blocks, and the changed arrangement location. An LSI placement device comprising: placement information storage means for storing placement information including information; and delay information storage means for storing delay information including the delay calculation result.