CN111199133A - Automatic wiring and winding method - Google Patents
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- CN111199133A CN111199133A CN201911374023.8A CN201911374023A CN111199133A CN 111199133 A CN111199133 A CN 111199133A CN 201911374023 A CN201911374023 A CN 201911374023A CN 111199133 A CN111199133 A CN 111199133A
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Abstract
The invention discloses an automatic wiring and winding method, and relates to the technical field of integrated circuits. The method comprises the following steps: acquiring a coordinate array of an initial winding barrier layer of a target design module; multiplying the coordinate array of the initial winding barrier layer and a preset scaling factor to obtain a scaled winding barrier layer coordinate array, and setting the array as a third variable; acquiring a coordinate array of initial winding blocking layers of all pins in a target design module, performing logic operation based on the array to obtain a winding blocking layer coordinate array after each pin is zoomed, and setting the array as a fifth variable; performing logic operation on the fifth variable and the third variable to obtain a coordinate array of the target design module and the winding blocking layer with the pins scaled, and setting the coordinate array as a sixth variable; and generating the layer with the winding blocking layer information based on the sixth variable. According to the technical scheme, the design module with more pins can reduce the workload of workers and improve the design precision.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an automatic wiring and winding method.
Background
In the chip design process, physical positions need to be allocated to cells, macro modules and the like on a layout, so that the cells, the macro modules and other components are not overlapped with each other, and the process is layout. After layout, the exact locations of the cells and pins have been determined, as have the required interconnections. A set of standard cells and macros are given, along with the characteristic widths, heights, etc. of these components, and a set of wires connecting these cells, macros, and pins is given as wiring. And the wiring process is used for realizing the connection of all modules and generating the geometric interconnection layout of all connecting lines. In the wiring process, wiring rules, such as the pitch of the through holes, the distance between the through holes and the metal wire, and the like, need to be observed. The area reserved for wiring is called a wiring area. The routing must be performed within the routing area to comply with routing rules without causing a rule violation of the routing.
In the related art, a chip Design module is generally laid out and wired using a tool in EDA (electronic Design Automation). However, when a part of a certain chip Design module is subjected to layout and routing Design, the routing barrier layer constraint range for automatically routing the chip Design module by using an EDA tool is not enough, and in a physical verification stage, a condition that the distance between an automatic routing pattern and a layout pattern in an adjacent Design is not enough to generate a condition of violating DRC (Design Rule Checking) may occur. In addition, for the design module with more pins, the workload of manually supplementing the winding barrier layer is greater, the multiplexing efficiency is low, and the accurate control is low.
Disclosure of Invention
The invention mainly aims to provide an automatic wiring and winding method, aiming at reducing the winding workload.
In order to achieve the purpose, the invention provides an automatic wiring and winding method, which comprises the following steps:
s1, obtaining a coordinate array of an initial winding barrier layer of the target design module, and setting the array as a first variable;
s2, presetting a scaling factor as a second variable, performing multiplication operation on the first variable and the second variable to obtain a winding barrier coordinate array after the target design module is scaled, and setting the array as a third variable;
s3, obtaining a coordinate array of the initial winding barrier layers of all the pins in the target design module, and setting the array as a fourth variable;
s4, calculating to obtain a polygonal coordinate array corresponding to each pin based on the fourth variable, multiplying the polygonal coordinate array with the second variable to obtain a winding barrier coordinate array after each pin is zoomed, and setting the array as a fifth variable;
s5, carrying out logic operation on the fifth variable and the third variable to obtain a coordinate array of the target design module and the winding barrier layer with the pins scaled, and setting the coordinate array as a sixth variable;
s6, judging whether the sixth variable meets the design requirement:
if the design requirement is not met, returning to the step S2, and modifying the value of the second variable;
if the design requirements are met, generating a layer with winding barrier layer information based on the sixth variable;
and S7, displaying and storing the layer of the winding barrier layer information at the corresponding position of the target design module.
Preferably, before the step S1, the method further includes:
automatically wiring and winding the target design module by using a tool to obtain an initial winding barrier layer of the target design module and pins thereof; judging whether the initial winding blocking layer meets the design requirement: if the design requirement is met, performing step S7; if the design requirement is not met, the process goes to step S1.
Preferably, the verification is performed by the tool to determine whether the routing barrier meets design requirements.
Preferably, the step S1 further includes: and searching an address pointer based on the top layer attribute of the target design module according to the name of the target design module, and then obtaining a coordinate array of an initial winding blocking layer of the target design module according to the address pointer.
Preferably, in step S4, the calculating the polygon coordinate array corresponding to each of the pins based on the fourth variable further includes: and performing negation operation on the fourth variable to obtain a polygon coordinate array corresponding to each pin.
Preferably, in step S5, the logical operation is a nand operation.
According to the technical scheme, the initial winding blocking layer information of the target design module is obtained, and the initial winding blocking layer is zoomed according to the preset zooming factor on the basis to obtain the new winding blocking layer information, so that the zooming of the shape and the restriction range of the winding blocking layer can be flexibly realized; for the design module with more pins, the workload of workers can be reduced, and the design precision is improved.
Drawings
FIG. 1 is a flow chart of the method for automatic wiring and winding according to the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention is further described below with reference to the accompanying drawings.
In the embodiment of the present invention, the target design module is a layout design File of the chip design module, and is generally a File in an LEF (Library Exchange File) format. The tools used are typically back end design tools in EDA tools.
As shown in fig. 1, an embodiment of the present invention provides an automatic wiring and winding method, including the following steps:
s0, automatically wiring and winding the target design module by using a tool to obtain an initial winding barrier layer of the target design module and the pins thereof; judging whether the initial winding blocking layer meets the design requirement: if the design requirement is met, performing step S7; if the design requirement is not met, the process goes to step S1.
In particular, in an EDA tool, wiring routing may be automated on a chip design module for subsequent design. And when the restraint range of the routing barrier layer for automatically wiring the chip design module by using the EDA tool is insufficient, judging that the initial routing barrier layer does not meet the design requirement.
S1, obtaining a coordinate array of an initial winding barrier layer of the target design module, and setting the array as a first variable;
specifically, step S1 further includes: and searching an address pointer based on the top layer attribute of the target design module according to the name of the target design module, and then obtaining a coordinate array of an initial winding blocking layer of the target design module according to the address pointer.
Specifically, the format of the coordinate array of the initial routing barrier of the target design module is generally (x)1，y1，x2，y2) The layout and wiring tool display interface is generally displayed as a quadrangle, and the graphic size of the polygon corresponding to the target design module can be obtained according to the coordinate array.
S2, presetting a scaling factor as a second variable, performing multiplication operation on the first variable and the second variable to obtain a winding barrier coordinate array after the target design module is scaled, and setting the array as a third variable;
in a specific embodiment, the scaling factor is used for controlling the scaling of the size of the routing barrier layer of the target design module, and the scaling factor can be specifically set according to the specific design requirement of the target design module, so that the scaling of the shape and the constraint range of the routing barrier layer can be flexibly realized, whether the set scaling factor meets the design requirement or not can be further verified in the subsequent steps, and if not, the set scaling factor can be modified again to meet the design requirement.
S3, obtaining a coordinate array of the initial winding barrier layers of all the pins in the target design module, and setting the array as a fourth variable;
in one embodiment, the initial routing barrier of the pin in the target design module is generally composed of a plurality of polygons, and the corresponding coordinate arrays have a plurality of sets.
S4, calculating to obtain a polygonal coordinate array corresponding to each pin based on the fourth variable, multiplying the polygonal coordinate array with the second variable to obtain a winding barrier coordinate array after each pin is zoomed, and setting the array as a fifth variable;
preferably, in step S4, the calculating the polygon coordinate array corresponding to each of the pins based on the fourth variable further includes: and performing negation operation on the fourth variable to obtain a polygon coordinate array corresponding to each pin.
S5, carrying out logic operation on the fifth variable and the third variable to obtain a coordinate array of the target design module and the winding barrier layer with the pins scaled, and setting the coordinate array as a sixth variable;
preferably, in step S5, the logical operation is a nand operation.
S6, judging whether the sixth variable meets the design requirement:
if the design requirement is not met, returning to the step S2, and modifying the value of the second variable;
if the design requirements are met, generating a layer with winding barrier layer information based on the sixth variable;
and S7, displaying and storing the layer of the winding barrier layer information at the corresponding position of the target design module.
Preferably, the verification is performed by the tool to determine whether the routing barrier meets design requirements.
According to the technical scheme of the embodiment of the invention, the initial winding blocking layer information of the target design module is obtained, and the initial winding blocking layer is zoomed according to the preset zoom factor on the basis of the initial winding blocking layer information to obtain new winding blocking layer information, so that the zoom of the shape and the restraint range of the winding blocking layer can be flexibly realized; for the design module with more pins, the workload of workers can be reduced, and the design precision is improved.
The target design module in the embodiment of the invention is based on a universal design exchange file, and the technical scheme of the invention can be realized in the same back-end design tool environment without being limited by the process; meanwhile, the technical scheme of the invention has good portability on different EDA tools designed at the back end, and the same function can be realized as long as corresponding tool command languages are replaced correspondingly.
Aiming at the stage requirement of the design process, the technical scheme of the invention can be used as an independent subprocess to be embedded into any stage of the design process of the target design module, and can repeatedly act on the target design module for many times until the design requirement is met.
It should be understood that the above is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures or equivalent flow transformations made by the present specification and drawings, or applied directly or indirectly to other related technical fields, are included in the scope of the present invention.
Claims (6)
1. A method for automatically wiring and winding wires is characterized by comprising the following steps:
s1, obtaining a coordinate array of an initial winding barrier layer of the target design module, and setting the array as a first variable;
s2, presetting a scaling factor as a second variable, performing multiplication operation on the first variable and the second variable to obtain a winding barrier coordinate array after the target design module is scaled, and setting the array as a third variable;
s3, obtaining a coordinate array of the initial winding barrier layers of all the pins in the target design module, and setting the array as a fourth variable;
s4, calculating to obtain a polygonal coordinate array corresponding to each pin based on the fourth variable, multiplying the polygonal coordinate array with the second variable to obtain a winding barrier coordinate array after each pin is zoomed, and setting the array as a fifth variable;
s5, carrying out logic operation on the fifth variable and the third variable to obtain a coordinate array of the target design module and the winding barrier layer with the pins scaled, and setting the coordinate array as a sixth variable;
s6, judging whether the sixth variable meets the design requirement:
if the design requirement is not met, returning to the step S2, and modifying the value of the second variable;
if the design requirements are met, generating a layer with winding barrier layer information based on the sixth variable;
and S7, displaying and storing the layer of the winding barrier layer information at the corresponding position of the target design module.
2. The method for automatic routing and winding of claim 1, further comprising, before said step S1:
automatically wiring and winding the target design module by using a tool to obtain an initial winding barrier layer of the target design module and pins thereof; judging whether the initial winding blocking layer meets the design requirement: if the design requirement is met, performing step S7; if the design requirement is not met, the process goes to step S1.
3. The method of automatic wire routing and winding of claim 2, wherein verification is performed by the tool to determine if the routing barrier meets design requirements.
4. The method for automatic wire routing and winding as claimed in claim 1, wherein said step S1 further comprises: and searching an address pointer based on the top layer attribute of the target design module according to the name of the target design module, and then obtaining a coordinate array of an initial winding blocking layer of the target design module according to the address pointer.
5. The method for automatic routing and winding of claim 1, wherein in step S4, the step of calculating the polygon coordinate array corresponding to each of the pins based on the fourth variable further comprises: and performing negation operation on the fourth variable to obtain a polygon coordinate array corresponding to each pin.
6. The method according to claim 1, wherein in step S5, the logical operation is a nand operation.
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| CN201911374023.8A CN111199133B (en) | 2019-12-27 | 2019-12-27 | Automatic wiring and winding method |
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| CN111199133B CN111199133B (en) | 2023-09-15 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117422042A (en) * | 2023-11-08 | 2024-01-19 | 广芯微电子（广州）股份有限公司 | Design method and device for comb-shaped winding barrier layer |
| CN117422042B (en) * | 2023-11-08 | 2024-07-02 | 广芯微电子（广州）股份有限公司 | Design method and device for comb-shaped winding barrier layer |
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| CN111199133B (en) | 2023-09-15 |
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