JP4907257B2 - Circuit board wiring method and wiring support device - Google Patents

Description

  The present invention forms a single circuit board by interconnecting a plurality of low temperature fired multilayer ceramic substrates (LTCC), and a plurality of low temperature fired multilayer ceramic substrates in the single circuit board. The present invention relates to a circuit board wiring method and a wiring support device for wiring between chips mounted on the board.

In a conventional wiring method, a line search method and a maze method are used in combination in a method of forming a shortest connection line by combining vertical and horizontal line segments between two predetermined points A and B. The shortest connection line is formed (see, for example, Patent Document 1).
JP-A-5-216963 (page 3, left column, line 13-page 4, left column, line 8, FIG. 1)

  The conventional wiring method does not connect a plurality of substrates with a connector as a wiring target, but performs an optimal wiring design and layout design for a single substrate. There is a problem that it is difficult to apply the conventional wiring method as it is to a circuit board in which the boards are connected to each other to form a single board due to restrictions imposed by the connectors.

  For this reason, wiring on a single circuit board in which a plurality of low-temperature fired multilayer ceramic substrates are connected to each other is an effective means other than manual wiring by the wiring designer considering the connection status between the terminals of the LSI and the board. However, this manual operation has a problem that it takes time and lacks accuracy and reliability.

  The present invention has been made to solve the above-described problems, and a wiring method and wiring capable of automatically performing wiring on a single circuit board in which a plurality of low-temperature fired multilayer ceramic substrates are interconnected. A circuit board wiring method and a wiring support apparatus capable of minimizing the wiring length between chips respectively mounted on a plurality of low-temperature fired multilayer ceramic substrates with an optimal wiring path are provided. It is to provide.

In the method of wiring circuit board according to this invention, without a single circuit board are connected to each other by a plurality of low-temperature fired multilayer ceramic substrate via a connector, a plurality of low temperature co-fired multilayer in the single circuit board A circuit board wiring method executed by a circuit board wiring support device for wiring between chips mounted on a ceramic substrate, wherein the schematic automatic wiring processing means provided in the wiring support device is an arbitrary in a net to be wired The terminal of the start point, the terminal corresponding to the start point as a target point, by line search method to generate line segments from the start point until reaching all the target points, by performing a backtrace process, a first step of assigning said net to a connector, the details automatic wiring processing means for the wiring support apparatus comprises, Referring to the net, one of the chip terminals or connector ports in each low-temperature fired multilayer ceramic substrate is a starting point, the chip terminal or connector port corresponding to the starting point is a target point, A grid value is set from the start point to the target point by the maze method, and a back trace process is performed to provide a second step of setting the net wiring route.

Further, in the circuit board wiring method according to the present invention, the step of the terminal shape correcting means provided in the wiring support device defining all the terminals on one side of the chip as a terminal group as needed is the first step . has in front of the first steps, the first of the general automatic wiring process means in step, any terminal the starting point in the wiring nets, the terminals corresponding to the start point and the target point, line search method Thus, a line segment is generated from the terminal group including the start point until reaching all the terminal groups including the target point, and the net is allocated to the connector by performing a backtrace process.

Further, in the circuit board wiring method according to the present invention, the via lead-out wiring means included in the wiring support device pulls out the wiring from each terminal of the chip to each via at the edge of the via dropping area, if necessary. When, a step of ports leading wiring means the wiring support apparatus comprises draws wires from each port of the connector to the edge of the via prohibition area, between said first step the second steps a, the second step each via at the edge of each terminal is the via darken areas of the definitive chips flop, each port at the edge of the ports of the connector definitive said second steps is the via prohibition area These correspond to the end portions of the lead wires.

  Further, in the circuit board wiring method according to the present invention, the terminal of the chip is dropped to the layer where the port lead wiring is formed through the via as necessary, and the port lead is drawn by the wiring on the layer. It connects to the end of the wiring.

  In the circuit board wiring method according to the present invention, if necessary, the power supply or ground terminal of the chip drops to a predetermined layer through the via, and via the wiring on the predetermined layer, It is connected to the end of the port lead wiring through the via.

  Further, in the circuit board wiring support apparatus according to the present invention, a plurality of low-temperature fired multilayer ceramic substrates are connected to each other via a connector to form a single circuit board, A wiring support device for a circuit board for wiring between chips mounted on a fired multilayer ceramic substrate, wherein terminal shape correcting means for defining all terminals on one side of the chip as a terminal group, and a wiring net Using any line as the starting point and the terminal corresponding to the starting point as the target point, the line search method generates a line segment from the terminal group including the starting point until reaching all of the terminal group including the target point. By performing the trace processing, the rough automatic wiring processing means for assigning the net to the connector, and each terminal of the chip Via extraction wiring means for drawing wiring to each via at the edge of the via dropping area, port extraction wiring means for drawing wiring from each port of the connector to the edge of the via prohibited area, and each low temperature with reference to the net One of the ends of the plurality of vias or port lead wires in the fired multilayer ceramic substrate is a start point, and the end of the via or port lead wire corresponding to the start point is a target point. And a detailed automatic wiring processing means for setting the grid value until the target point is reached and performing the back trace process, thereby setting the wiring path of the net.

In the method of wiring circuit board according to this invention, without a single circuit board are connected to each other by a plurality of low-temperature fired multilayer ceramic substrate via a connector, a plurality of low temperature co-fired multilayer in the single circuit board A circuit board wiring method executed by a circuit board wiring support device for wiring between chips mounted on a ceramic substrate, wherein the schematic automatic wiring processing means provided in the wiring support device is an arbitrary in a net to be wired The terminal of the start point, the terminal corresponding to the start point as a target point, by line search method to generate line segments from the start point until reaching all the target points, by performing a backtrace process, a first step of assigning said net to a connector, the details automatic wiring processing means for the wiring support apparatus comprises, Referring to the net, one of the chip terminals or connector ports in each low-temperature fired multilayer ceramic substrate is a starting point, the chip terminal or connector port corresponding to the starting point is a target point, By setting a grid value from the start point to the target point by the maze method, and performing a backtrace process, the second step is used as a wiring route of the net. Wiring can be automatically and efficiently performed to minimize the wiring length between chips mounted on the low-temperature fired multilayer ceramic substrate within the limits of the connector. In particular, even for a plurality of low-temperature fired multilayer ceramic substrates connected in three dimensions, wiring having the shortest length can be performed with an optimal wiring path.

Further, in the circuit board wiring method according to the present invention, the step of the terminal shape correcting means provided in the wiring support device defining all the terminals on one side of the chip as a terminal group as needed is the first step . has in front of the first steps, the first of the general automatic wiring process means in step, any terminal the starting point in the wiring nets, the terminals corresponding to the start point and the target point, line search method By generating a line segment from the terminal group including the start point until reaching all of the terminal group including the target point, and performing a backtrace process, the net is allocated to the connector. You can widen the allowable range of the target point that the line can reach from the start point to the target point The number of times of generation of the line segment to reach can be reduced.

Further, in the circuit board wiring method according to the present invention, the via lead-out wiring means included in the wiring support device pulls out the wiring from each terminal of the chip to each via at the edge of the via dropping area, if necessary. When, a step of ports leading wiring means the wiring support apparatus comprises draws wires from each port of the connector to the edge of the via prohibition area, between said first step the second steps a, the second step each via at the edge of each terminal is the via darken areas of the definitive chips flop, each port at the edge of the ports of the connector definitive said second steps is the via prohibition area Corresponding to the ends of the lead-out wiring, the chip terminals and connector ports can be easily connected to the wiring.

  Further, in the circuit board wiring method according to the present invention, the terminal of the chip is dropped to the layer where the port lead wiring is formed through the via as necessary, and the port lead is drawn by the wiring on the layer. By connecting to the end of the wiring, select the substrate layer that minimizes the wiring length between the chip terminal and connector port for each substrate layer in the low-temperature fired multilayer ceramic substrate, and multiple low-temperature firing The wiring length between the chips mounted on the multilayer ceramic substrate can be minimized.

  In the circuit board wiring method according to the present invention, if necessary, the power supply or ground terminal of the chip drops to a predetermined layer through the via, and via the wiring on the predetermined layer, By connecting to the end of the port lead wiring through the via, the power supply or ground net wiring can be routed to the layer designated by the wiring designer. In particular, the power supply or ground net wiring has priority over the wiring length specified by the wiring designer rather than the routing wiring length, and wiring that prioritizes wiring length, such as clock wiring, which is highly affected by noise. Can be preferentially wired to the substrate layer where the wiring length between the terminal and the port of the chip is the shortest.

  Further, in the circuit board wiring support apparatus according to the present invention, a plurality of low-temperature fired multilayer ceramic substrates are connected to each other via a connector to form a single circuit board, A wiring support device for a circuit board for wiring between chips mounted on a fired multilayer ceramic substrate, wherein terminal shape correcting means for defining all terminals on one side of the chip as a terminal group, and a wiring net Using any line as the starting point and the terminal corresponding to the starting point as the target point, the line search method generates a line segment from the terminal group including the starting point until reaching all of the terminal group including the target point. By performing the trace processing, the rough automatic wiring processing means for assigning the net to the connector, and each terminal of the chip Via extraction wiring means for drawing wiring to each via at the edge of the via dropping area, port extraction wiring means for drawing wiring from each port of the connector to the edge of the via prohibited area, and each low temperature with reference to the net One of the ends of the plurality of vias or port lead wires in the fired multilayer ceramic substrate is a start point, and the end of the via or port lead wire corresponding to the start point is a target point. A plurality of low-temperature firing multilayers in the circuit board, by providing detailed automatic wiring processing means for setting the grid value from the first to the target point and performing backtrace processing to perform wiring of the net. Wiring that minimizes the wiring length between chips mounted on each ceramic substrate within the limits of the connector Automatically and can be efficiently performed. In particular, wiring having the shortest length can be performed with an optimal wiring path for a plurality of low-temperature fired multilayer ceramic substrates connected in three dimensions.

(First embodiment of the present invention)
FIG. 1A is a plan view showing an example of a circuit board to which the wiring method according to the first embodiment for carrying out the present invention is applied, and FIG. 1B is an arrow of the circuit board shown in FIG. FIG. 2A is a cross-sectional view taken along line AA, FIG. 2A is a plan view showing an example of a low-temperature fired multilayer ceramic substrate that is a component of the circuit board shown in FIG. 1, and FIG. FIG. 3A is a partial cross-sectional perspective view showing an example in which a plurality of low-temperature fired multilayer ceramic substrates are connected in three dimensions, and FIG. 3B is a cross-sectional view taken along line BB of the low-temperature fired multilayer ceramic substrate shown in FIG. It is a perspective view which shows the other example which connected the some low-temperature baking multilayer ceramic substrate in three dimensions.

  1 to 3, a low-temperature fired multilayer ceramic substrate 1 has a chip 2 mounted on the front surface or back surface, and a connector 3 (a convex male connector 3a or a concave female connector 3b on the front surface, back surface, or side surface. ) Can be connected to the plurality of low-temperature fired multilayer ceramic substrates 1 by the connector 3. The chip 2 is an integrated circuit in which a plurality of circuit elements and wirings connecting them are integrated and integrated, and depending on the number of integrated circuit elements, IC (Integrated Circuit), LSI ( Large scale integration (VLSI), very large scale integration (VLSI), and ultra large scale integration (ULSI). A plurality of low-temperature fired multilayer ceramic substrates 1 are connected to each other via a connector 3 to form a single circuit board 100.

  In FIG. 1, a plurality of low-temperature fired multilayer ceramic substrates 1 are two-dimensionally connected by disposing a connector 3 on the side surface of the low-temperature fired multilayer ceramic substrate 1, but as shown in FIG. By arranging the connector 3 on the front or back surface of the low-temperature fired multilayer ceramic substrate 1, it is possible to connect a plurality of low-temperature fired multilayer ceramic substrates 1 in three dimensions.

  In this case, since it is difficult to dispose the convex male connector 3a on the front and back surfaces of the low-temperature fired multilayer ceramic substrate 1, it is preferable to dispose the concave female connector 3b. Further, another low-temperature fired multilayer ceramic substrate 1 connected to the low-temperature fired multilayer ceramic substrate 1 provided with the female connector 2b is provided with a female connector by providing a convex male connector 3a on the side surface. The connector 3b and the male connector 3a can be fitted.

  Next, the wiring support device 10 for wiring between the chips 2 mounted on the plurality of low-temperature fired multilayer ceramic substrates 1 in the circuit board 100 in which the plurality of low-temperature fired multilayer ceramic substrates 1 are connected to each other will be described.

  4 is a diagram showing the configuration of the wiring support apparatus according to the first embodiment for carrying out the present invention. FIG. 5 is an example of wiring conditions stored in the wiring condition storage means in the wiring support apparatus shown in FIG. FIG. 6 is an explanatory diagram showing another example of the wiring conditions stored in the wiring condition storage means in the wiring support device shown in FIG. 4, and FIG. 7 is a wiring diagram in the wiring support device shown in FIG. FIG. 8A is an explanatory diagram showing still another example of the wiring conditions stored in the condition storage means, and FIG. 8A is for explaining the terminal shape correction means before the terminal shape correction processing in the wiring support apparatus shown in FIG. FIG. 8B is an explanatory diagram for explaining the terminal shape correcting unit after the terminal shape correction processing in the wiring support apparatus shown in FIG. 4, and FIG. 9 is the wiring support apparatus shown in FIG. Explanation for explaining staggered wiring processing by via lead wiring means 10 is an explanatory diagram for explaining the lead wiring processing from the port by the port lead wiring means in the wiring support apparatus shown in FIG. 4, and FIG. 11 is a schematic automatic wiring processing means in the wiring support apparatus shown in FIG. FIG. 12 is an explanatory diagram for explaining the line search method used, FIG. 12 is an explanatory diagram for explaining the maze method used for the detailed automatic wiring processing means in the wiring support apparatus shown in FIG. 4, and FIG. 13 is the maze method shown in FIG. FIG. 14 is an explanatory diagram for explaining the continuation of the maze method shown in FIG. 13, FIG. 15 is an explanatory diagram for explaining the continuation of the maze method shown in FIG. 4 is an explanatory diagram for explaining dropping of power supply and ground wiring by the detailed automatic wiring processing means in the wiring support apparatus shown in FIG. 4, and FIG. 17 is a power supply by detailed automatic wiring processing means in the wiring support apparatus shown in FIG. G 18A is an explanatory diagram for explaining the wiring processing of the terminal wiring, and FIG. 18A is an explanatory diagram for explaining the wiring merging means before the merging of the wiring in the vicinity of the port lead wiring in the wiring support apparatus shown in FIG. 18 (b) is an explanatory diagram for explaining a state after the merging of the wiring in the vicinity of the port lead wiring by the wiring merging means in the wiring support apparatus shown in FIG.

  In FIG. 4, the layout information storage unit 11 stores layout information generated by the layout design CAD device 200 that performs the shape and layout design of the chip 2 and the shape and layout design of the connector 3. The layout information includes chip arrangement data, chip shape data, chip terminal data, chip terminal attribute data, connector arrangement data, connector shape data, connector port data, board shape data, board layer number data, wiring prohibited area data, etc. It is.

  Here, the chip arrangement data is data relating to the arrangement coordinates of each chip 2. Specifically, it is coordinate data of a point representing the position of the chip 2 (for example, one of the vertices at the lower part of the chip 2). The chip shape data is data relating to the shape of each chip 2. Specifically, in the case of a rectangular parallelepiped chip 2, the data is vertical, horizontal, and height data. The chip terminal data is data of the position of the flip chip bonding terminal 2 a in each chip 2. The position of the terminal 2 a in the chip terminal data indicates relative coordinates with respect to the point represented by the chip 2. The chip terminal attribute data is data indicating the terminal 2a provided on the chip 2 and which terminal 2a performs the respective input / output.

  Further, the connector arrangement data is data relating to the arrangement coordinates of each connector 3. Specifically, the point representing the position of the connector 3 (for example, one of the vertices of the convex portion in the case of the male connector 3a and one of the vertices of the concave portion in the case of the female connector 3b). Coordinate data. The connector shape data is data related to the shape of each connector 3. Specifically, in the case of a male type or a female type or a rectangular parallelepiped connector 3, the data is vertical, horizontal, and thickness data. The connector port data is data on the position of the connection port 3c in each connector 3. The position of the port 3 c in the connector port data indicates relative coordinates with respect to the point represented by the connector 3.

  The substrate shape data is data indicating what shape the target low-temperature fired multilayer ceramic substrate 1 has. For example, a rectangular substrate may have vertical and horizontal dimensions. The substrate layer number data is data indicating how many layers of the target low-temperature fired multilayer ceramic substrate 1 are formed. Further, the wiring prohibition area data is data related to a prohibition area in which wiring cannot be arranged on each substrate layer.

  The wiring condition storage unit 12 stores wiring conditions for wiring. As a special wiring condition by the connector 3 according to the present invention, in the case of executing a rough automatic wiring process to be described later, in the line search method, the restriction that the portion of the connector 3 can pass only a line segment in the same direction as the connector direction, In the case where only the portion of the connector 3 can generate a line segment across adjacent low-temperature fired multilayer ceramic substrates 1 or when the number of nets allocated to the connector 3 reaches the number of ports of the connector 3 There is a restriction that a line segment cannot pass through the connector 3.

  Further, when executing a detailed automatic wiring process described later, as shown in FIG. 5A, a via drop region 4 having a predetermined range with respect to the chip 2 in the uppermost substrate layer of the low-temperature fired multilayer ceramic substrate 1. And the connector 3 of the low-temperature fired multilayer ceramic substrate 1 is disposed as shown in FIG. 5 (b), and the restriction that the adjacent vias 5 are disposed along the edge 4a of the via dropping region 4 in a staggered arrangement. For example, there is a restriction that a via-forbidden area 6 having a predetermined range from the side is provided.

  Note that, as shown in FIG. 6A, if the wiring 7b of the net B and the wiring 7a of the net A are formed on different substrate layers so as not to overlap each other, cost increases due to layer switching. Therefore, as shown in FIG. 6B, the actual wiring length of the net B wiring 7b becomes long, but the net B wiring 7b, which is the same substrate layer as the net A wiring 7a, wraps around. The net B wiring 7b can be performed without changing the substrate layer of the net B wiring 7b, and the layer transfer cost can be reduced to zero. Here, a broken line portion of the wiring 7 is a wiring arranged in a lower layer of the solid line portion. Further, as shown in FIG. 7, a plurality of other low-temperature fired multilayer ceramics can be obtained by wiring between ports 3a of the connector 3 on different sides of the low-temperature fired multilayer ceramic substrate 1 without being connected to the terminals 2a of the chip 2. The net wiring 7 connecting the chips 2 on the substrate 1 can also function as a through wiring.

  The terminal shape correction means 13 is based on the chip terminal data stored in the layout information storage means 11 and in accordance with the rules stored in the wiring condition storage means 12, the terminals 2 a of the chips 2 on each low-temperature fired multilayer ceramic substrate 1. To define all terminals on one side of the chip 2 as a terminal group 2b.

  Specifically, as shown in FIGS. 8A and 8B, port instances (P01 to P08: corresponding to the terminal 2a) in each substrate instance (corresponding to the low-temperature fired multilayer ceramic substrate 1) The entire side of the chip instance (corresponding to chip 2) is a terminal group 2b. Note that it is not necessary to obtain a precise route in the rough automatic wiring process described later, and it is assumed that the route is obtained when the side of the chip 2 is reached by the wiring process.

  Via lead wiring means 14 is based on the chip terminal data stored in the layout information storage means 11, and according to the rules stored in the wiring condition storage means 12, each terminal of the chip 2 in each low-temperature fired multilayer ceramic substrate 1 A process of drawing the wiring from 2a to each via 5 at the edge 4a of the via drop region 4 is performed. In addition, by arranging the adjacent vias 5 at the edge 4a of the via dropping region 4 in a staggered arrangement, a space for driving the vias 5 can be secured.

  Specifically, as shown in FIG. 9, the wiring is drawn from the port instance (corresponding to the terminal 2 a) of the chip instance (corresponding to the chip 2) to the edge 4 a of the via dropping region 4, and the edge of the via dropping region 4 The vias 5 are driven in a staggered arrangement at the part 4a, and the via lead-out wiring means 14 performs processing in the following procedure.

  First, the via drop region 4 is calculated from the zone coordinates of the chip instance stored in the layout information storage unit 11 and the via range value of the rule file stored in the wiring condition storage unit 12.

  Next, all port instances of the chip instance are extracted, and port instances having the same coordinate axis are associated. Note that the target axis changes depending on the arrangement of the chip 3 with respect to the substrate.

Hereinafter, the process is performed for each group in which the port instances are classified.
The port instances are sorted in ascending order based on the X coordinate (Y coordinate), and the port instances are obtained sequentially.
From the odd-numbered port instance, the wiring is drawn up to the edge 4a of the via dropping area 4 and the via 5 is formed. In FIG. 9, wiring is drawn in the left and right directions from the port instances on the left and right sides of the chip on the paper surface. However, the wiring is drawn in the upper and lower directions from the port instances on the top and bottom of the chip on the paper surface. It will be pulled out.
Further, from the even-numbered port instance, the wiring is drawn from the edge 4a of the via drop region 4 to the inside by one via, and the via 5 is formed.

When the via 5 created as described above is wired by the maze method in the detailed automatic wiring process described later, the wiring process is performed as a start point or a target point.
The port lead-out wiring means 15 is based on the connector port data stored in the layout information storage means 11 and in accordance with the rules stored in the wiring condition storage means 12, the port 3 c of the connector 3 in each low-temperature fired multilayer ceramic substrate 1. The wiring is drawn out from the edge 6a to the edge 6a of the via prohibited area 6.

Specifically, processing is performed according to the following procedure.
First, the via prohibition area 6 is calculated from the zone coordinates of the connector 3 written in the board information file stored in the layout information storage means 11 and the via range value of the rule file stored in the wiring condition storage means 12.

Next, the port 3c in the connector 3 is acquired sequentially.
From the acquired port 3c to the edge 6a of the via-forbidden area 6, the wiring is drawn along the extending direction of each port 3c from the outside to the inside of the substrate. In FIG. 10, the wiring is drawn horizontally from the connectors on the left and right sides of the low-temperature fired multilayer ceramic substrate 1 on the paper surface, but from the connectors on the upper and lower sides of the low-temperature fired multilayer ceramic substrate 1 on the paper surface in the vertical direction. Pull out the wiring. The substrate layer for wiring the port lead wiring 3d is a wiring layer corresponding to the substrate layer on which the port 3c is disposed. Moreover, it carries out with respect to all the connectors 3 of the male connector 3a and the female connector 3b.
When the port lead wiring 3d created as described above is wired by the labyrinth method in the detailed automatic wiring process described later, the wiring process is performed as a start point or a target point.

  The parameter setting unit 16 inputs a rule file such as designation of a board layer to be wired and setting of a wiring prohibited area to the layout information storage unit 11 and the wiring condition storage unit 12, a board information file, or a connector information file. Specifically, for example, the parameter setting unit 16 displays an input dialog on the display device 17 such as a CRT or a liquid crystal display, prompts the user to input wiring conditions, board information, or connector information. A program module that saves the rule file, board information file, or connector information file input from the input device 18 such as a keyboard in the layout information storage means 11 and the wiring condition storage means 12 can be used.

  The rough automatic wiring processing means 19 is based on the data stored in the layout information storage means 11 and the data obtained by the terminal shape correction means 13 according to the rules stored in the wiring condition storage means 12 by the line search method. Assign a net to the connector 3.

  Here, the line search method used in the general automatic wiring processing means 19 will be described with reference to FIG. In FIG. 11, a first low-temperature fired multilayer ceramic substrate 1a on which chip A is mounted, a second low-temperature fired multilayer ceramic substrate 1b on which chip B is mounted, and a third low-temperature fired multilayer ceramic substrate on which chip C is mounted. It is assumed that 1c and the fourth low-temperature fired multilayer ceramic substrate 1d on which the chip D is mounted are connected to each other by a connector 3 to form a single circuit substrate 100, and wiring processing is performed on this circuit substrate 100. ing. Hereinafter, in FIG. 11, the top, bottom, left, and right on the paper surface are the top, bottom, left and right of the circuit board 100.

First, an arbitrary terminal in the net to be wired is set as a start point, and a terminal corresponding to the start point is set as a target point.
Next, the first line segment 8a (solid line portion in FIG. 11) is generated from the terminal group 2b including the start point. Here, the first line segment 8a extends within the wiring area until it hits an obstacle. In FIG. 11, the left side of the chip A on the first low-temperature fired multilayer ceramic substrate 1a is the terminal group 2b including the first start point, and the left side of the chip C is the terminal group including the first target point. 2b. The first line segment 8a generated from the left side of the chip A extends to the adjacent second low-temperature fired multilayer ceramic substrate 1b via the connector 3 and is on the left side of the low-temperature fired multilayer ceramic substrate 1b outside the wiring region. This is the end point of the first line segment 8a.

  Next, the second line segment 8b (broken line part in FIG. 11) perpendicularly intersecting the first line segment 8a is extended in the wiring area until it hits an obstacle. In FIG. 11, the lower side of the chip B is the end point of the line corresponding to the lower side of the chip B that is an obstacle among the plurality of second line segments 8 b. Further, the upper and lower sides of the first low-temperature fired multilayer ceramic substrate 1a and the upper and lower sides of the second low-temperature fired multilayer ceramic substrate 2 serve as end points. Further, since only the line segment in the same direction as the connector direction (horizontal direction in FIG. 11) passes through the connector 3 portion, the second line segment 8b is not generated in the connector 3 portion. Incidentally, when the connector 3 is above or below the low-temperature fired multilayer ceramic substrate 1, a line segment is generated only in the vertical direction, and when it is on the left or right side, a line segment only in the horizontal direction is generated.

Next, a third line segment 8c (a chain line portion in FIG. 11) perpendicularly intersecting the second line segment 8b is extended in the wiring area until it hits an obstacle. In FIG. 11, it is only the portion of the connector 3 that can generate a line segment across the adjacent low-temperature fired multilayer ceramic substrates 1 (the adjacent substrate cannot be changed except for the portion of the connector 3). Moreover, it becomes an end point on the right side of the second low-temperature fired multilayer ceramic substrate 1b except for the connector 3 portion. Moreover, it becomes an end point on the left side of the second low-temperature fired multilayer ceramic substrate 1b. In FIG. 11, the third line segment 8 c reaches the left side of the chip C that is the first target point.
The above operation is performed until the line segment reaches all of the terminal group 2b including the target point from the terminal group 2b including the first target point.

  When the line segment reaches all of the terminal group 2b including the target point from the terminal group 2b including the first target point, the line segment is returned in the reverse order (back trace processing is performed), so that the network is connected to the passing connector. Will be set.

  When nets are assigned to all the ports 3c of the connector 3, a line segment cannot pass through the connector 3. Therefore, when the line segment passes through the connector 3, the connector is not connected. It is confirmed whether the number of nets assigned to 3 has reached the number of ports of the connector 3. When a plurality of wiring paths exist with the same number of bends, a path with a small number of low-temperature fired multilayer ceramic substrates 1 that have passed is selected as the wiring path.

  In the above-described line search method, the line search method applied to the two-dimensionally connected circuit boards 100 has been described. However, a plurality of low-temperature fired multilayer ceramic substrates as shown in FIG. 3A or FIG. The above-described line search method can also be applied to the circuit board 100 in which 1s are connected in three dimensions.

  In this case, in the portion of the connector 3 that connects the adjacent low-temperature fired multilayer ceramic substrates 1 vertically to each other, the line extending from one low-temperature fired multilayer ceramic substrate 1 is connected to the other low-temperature fired multilayer ceramic substrate 1. The point which makes a line segment extend over the other low-temperature-fired multilayer ceramic substrate 1 instead of interrupting the substrate 1 as an obstacle is newly added.

  The detailed automatic wiring processing means 20 refers to the net obtained by the general automatic wiring processing means 19, the data stored in the layout information storage means 11, the data obtained by the via lead wiring means 14, and the port lead wiring means. Based on the data obtained in step 15, the net wiring path is processed by the maze method according to the rules stored in the wiring condition storage means 12.

  Here, the maze method used in the detailed automatic wiring processing means 20 will be described with reference to FIGS. In the first embodiment, a 45/90 degree multi-layer maze method is used. The wiring is in the data acquisition order. Hereinafter, application of the maze method when the substrate layer is one layer will be described.

  First, as shown in FIG. 12A, grid formation is performed on the entire wiring region (all substrate layers). In this case, the board layer on which the connector 3 exists is grid-formed in consideration of the unevenness of the connector 3 portion.

  Next, as shown in FIG. 12B, the start point S and the target point T are set on the grid. In this case, the inside of each low-temperature fired multilayer ceramic substrate 1 is a target range using the maze method, and one of the terminals 2a of the chip 2 or each port 3c of the connector 3 in each low-temperature fired multilayer ceramic substrate 1 is a starting point. S, the terminal 2a of the chip 2 or the port 3c of the connector 3 corresponding to the start point S is set as the target point T. That is, the end of the staggered via 5 or the port lead wiring 3d is the start point S or the target point T. Further, the wiring prohibited area 9 is set on the grid. The wiring prohibited area 9 includes a chip instance zone (only the uppermost board layer), a connector port zone (only the board layer with the port), and an existing wiring figure (the outline of the wiring figure is sized according to the spacing rule) ), A rect figure (Z figure coordinate <= Z2 coordinate of the substrate <only a board corresponding to the Z2 coordinate of the figure) is set.

  Next, as shown in FIG. 13A, a value of “0” is set in the grid at the start point S. Then, a value of “1” (the grid value of the start point S is 0 + 1 = 1) is set to the grid that is obliquely adjacent to the grid of the start point S. In addition, the value specified by the via cost value in the rule file is set in the grid adjacent to the start point S in the vertical direction with respect to the Z direction (perpendicular to the page) (for example, 0 + 3 when the via cost value is “3”). = 3). It should be noted that no value is set for the portion that is the wiring prohibited area 9.

  Further, as shown in FIG. 13B, a value of “2” (1 + 1 = 2) is set in a grid that is diagonally adjacent to the grid in which a value of “1” is set. Also, the value specified by the via cost value in the rule file is set to the grid that is in contact with the grid in which the value of “1” is set in the upper and lower directions in the Z direction (vertical direction with respect to the page) (for example, the via cost). When the value is “3”, 1 + 3 = 4). In this case, if a value has already been set in the grid, overwriting is not performed.

  Next, as shown in FIG. 14A, “3” is set around the grid where the value “2” is set, and “4” is set around the grid where the value “3” is set. ”Is set, and the process is repeated in the same manner, and the process is stopped when the target point T is reached. If a value cannot be set for the target point T even if values are set for all the grids traced from the start point S, it is determined that there is no wiring route.

Next, as shown in FIG. 14B, the grid value proceeds from the target point T to the start point S in a direction in which the grid value decreases (back trace processing is performed). In this backtrace process, there is no redundant bending or movement of the substrate layer.
As shown in FIG. 15, when the vehicle reaches the start point S, the route traced by the backtrace process is registered as a wiring diagram as a net wiring route. When the substrate layer changes, a via cell is disposed at that position.

  Here, the wiring of the power supply or the ground net has priority over the wiring of the specified substrate layer rather than the wiring length. For this reason, as shown in FIG. 16, the power supply terminal or the ground terminal of the chip 2 drops from the via 5 to the predetermined substrate layers 30a and 30b specified by the rule file. Further, if there is an obstacle up to the position where the port lead wiring 3d of the connector 3 which is the end point of the wiring exists, another substrate layer may be used, but as much as possible with the predetermined substrate layers 30a and 30b. Wiring. In this case, the wiring of the predetermined substrate layers 30a and 30b is connected to the end of the port lead wiring 3d through the vias 5a and 5b.

  For wiring such as clock wiring that needs to be as short as possible, it is dropped to the substrate layer where the port lead wiring 3d is formed via the via 5, and the port lead wiring is formed by wiring on the substrate layer. By connecting the end of 3d and the terminal 2a of the chip 2, the wiring length between the terminal 2a of the chip 2 and the port lead wiring 3d is minimized with respect to each substrate layer in the low-temperature fired multilayer ceramic substrate 1. can do.

  A value setting method for each grid in the above-described maze method for wiring of a power supply or a ground net will be described with reference to FIG. In FIG. 17, a low-temperature fired multilayer ceramic substrate 1 consisting of four layers is assumed. A start point S is set in the uppermost substrate layer to which the chip 2 is flip-chip bonded, and a port lead wiring 3d is formed. The target point T is set on the second substrate layer, and the third substrate layer is set as the power supply designation layer.

First, the start point S and the target point T are set in the same manner as the maze method described above.
Next, the grid with the smallest value is acquired, and values are set around it. In the case of a grid of a substrate layer (the third substrate layer in FIG. 17) for which a power supply or a ground is specified, this value is set every time one grid is advanced, as in the maze method described above. Is increased by "1". In the case of a grid other than the substrate layer for which the power supply or the ground is designated, the value of the grid is increased by “1000” every time one grid is advanced. Further, when a value is set to a grid of another substrate layer through a via, the via cost of the rule file (for example, in FIG. 17, the case where the via cost value is “5” is shown in the same manner as the maze method described above. Increase the value specified in

  Similarly, the process is repeated until the target point T is reached. When a value is set in the grid, overwriting is not performed if a value has already been set in the grid. When performing backtrace processing, a grid having the smallest value among adjacent grids is selected as a route.

  The wiring merging means 21 is based on the data obtained by the detailed automatic wiring processing means 20, and in accordance with the rules stored in the wiring condition storage means 12, is the same net as the port lead-out wiring 3d and the wiring figure in the same layer is the port. When contacting with the lead wiring 3d, the port lead wiring 3d and the wiring figure are merged.

Specifically, as shown in FIG. 18, the port lead wiring 3d and the portion of the wiring figure 7c added by the wiring processing in contact with the port lead wiring 3d are merged to form one wiring 7. is there.
The output unit 22 outputs the wiring processing result obtained by the detailed automatic wiring processing unit 20 via the wiring merging unit 21 to a file or the display device 17.

  Next, a circuit board wiring method according to the first embodiment for carrying out the present invention will be described. FIG. 19 is a flowchart showing the overall flow of the wiring method according to the first embodiment for carrying out the present invention, and FIG. 20 shows the overall flow of the general automatic wiring process in the overall flow of the wiring method shown in FIG. FIG. 21 is a flowchart showing the continuation of the flowchart shown in FIG. 20, FIG. 22 is a flowchart showing the flow of the detailed automatic wiring process in the overall flow of the wiring method shown in FIG. 19, and FIG. 23 is the detailed automatic wiring shown in FIG. FIG. 24 is a flowchart showing a continuation of the flowchart shown in FIG. 23, and FIG. 25 is a flowchart showing a continuation of the flowchart shown in FIG. 24.

  First, the layout design CAD apparatus 200 is used to design the shape of the chip 2, the layout of the chip 2 on the low-temperature fired multilayer ceramic substrate 1, the design of the connector 3, the layout of the connector 3 on the low-temperature fired multilayer ceramic substrate 1, and the chip. 2 terminal 2a and connector 3 port 3c are arranged. Since this operation is performed by a conventional CAD apparatus, detailed description thereof is omitted. Position information of each chip 2 and connector 3 arranged on the low-temperature fired multilayer ceramic substrate 1 created here, shape information of each chip 2 and connector 3, position of terminal 2a of each chip 2 and port 3c of connector 3 Information and the like are stored in the layout information storage unit 11.

  Next, using the wiring support apparatus 10 described above, a connector 3 through which net wiring passes between adjacent low-temperature fired multilayer ceramic substrates 1 is automatically determined, and rough automatic wiring processing for assigning nets to the connector 3 is executed. (Step S1). The detailed operation of this general automatic wiring process will be described later.

  Here, it is determined whether or not there is a wiring path for another net other than the net to which the connector 3 is assigned (step S2). If there is no wiring path, the wiring of the net to which the connector 3 is assigned passes. The connector to be changed is changed (step S3), and the process returns to step S1 again to automatically determine the connector through which the net wiring passes.

  When it is determined in step S2 that there are wiring paths for all the nets, the wiring support device 10 performs a detailed automatic wiring process for calculating the wiring paths of the nets in each low-temperature fired multilayer ceramic substrate 1 and performing the wiring process. Execute (step S4). The detailed operation of the detailed automatic wiring process will be described later.

First, the wiring process in the general automatic wiring process will be described with reference to FIGS.
As an initial state, the board information is stored in the layout information storage unit 11. Therefore, first, the general automatic wiring processing means 19 reads this board information from the layout information storage means 11. Then, an arbitrary terminal in the net to be wired is set as a start point, and a terminal corresponding to the start point is set as a target point (step S5).

  Next, a first line segment is generated from the terminal group including the start point until reaching the end of the arrangement area or the wiring prohibited area. Here, the first line segment is stored in the memory as the first line segment (step S6). The terminal group defines all terminals on one side of the chip by the terminal shape correcting means 13 described above, and the terminal group including the start point refers to the terminal group including the terminal that is the start point. Yes. Further, the process of step S6 is the process of the line search method described above.

  Next, it is determined whether the first line segment is connected to the terminal group including the target point (step S7). If it is determined in step S7 that the first line segment is connected to the terminal group including the target point, a connection flag is set in the terminal group including the target point to be connected (step S8).

  Next, it is determined whether the connection flag has been set for all the terminal groups including the target point (step S9). If it is determined in step S9 that the connection flag has been set for all the terminal groups including the target, the backtrace process in the above-described line search method is performed (step S10). In addition, when passing through a connector during backtrace processing, a net is assigned to that connector. This completes the wiring process for one net.

  Further, it is determined whether all net wiring processing has been completed (step S11). If it is determined in step S11 that the wiring processing for all nets has been completed, the wiring processing ends. If it is determined that all net wiring processes have not been completed, the process returns to the beginning to start the wiring process in order to perform the next net wiring process (step S12).

  Further, if it is determined in step S7 that the first line segment is not connected to the terminal group including the target point, or in step S9, no connection flag is set for all the terminal groups including the target point. If it is determined, n = 1 is set (step S13), and a line segment perpendicular to the acquired n-th line segment is generated until the end of the arrangement area or the wiring prohibited area is reached. Here, the nth line segment is stored in the memory as the (n + 1) th line segment (step S14). In this case, the line segments are generated at intervals specified by the pitch of the rule file stored in the wiring condition storage unit 12.

  Next, it is determined whether or not one line segment intersecting with the nth line could be drawn (step S15). If it is determined in step S15 that no line segment intersecting with the nth line has been drawn, “error: cannot be wired” is displayed (step S16), and the next net is routed (step S16). S17) Returning to the beginning and starting the wiring process.

  If it is determined that at least one line segment intersecting the nth line has been drawn, n = n + 1 is set (step S18), and it is determined whether the nth line segment is connected to the terminal group including the target point (step S19). ). If it is determined that the nth line segment is not connected to the terminal group including the target point, the process returns to step S14. When it is determined that the nth line segment is connected to the terminal group including the target point, a connection flag is set in the terminal group including the target point to be connected (step S20).

  Next, it is determined whether the connection flag has been set for all the terminal groups including the target point (step S21). If it is determined that the connection flag is not set for all the terminal groups including the target point, the process returns to step S14. If it is determined that the connection flag has been set for all the terminal groups including the target point, the back trace process in the above-described line search method is performed (step S22).

  Further, it is determined whether all net wiring processing has been completed (step S23). If it is determined in step S23 that all nets have been wired, the wiring process is terminated. If it is determined that all net wiring processes have not been completed, the process returns to the beginning to start the wiring process in order to perform the next net wiring process (step S24).

Next, the wiring process in the detailed automatic wiring process will be described with reference to FIGS.
First, the detailed automatic wiring processing means 20 reads board information from the layout information storage means 11, forms a grid on all board layers based on this board information (step S25), and sets a wiring prohibited area (step S26).

  Next, the net acquired by the above-described schematic automatic wiring process is wired by the maze method (step S27). The maze method in step S27 will be described later.

  Next, it is determined whether or not the result obtained in step S27 can be wired (step S28). If it is determined in step S28 that wiring cannot be performed, “Warning: NetXXX cannot be wired” is displayed (step S29), and the process returns to step S27 to perform wiring processing for the next net (step S30).

  If it is determined in step S27 that the next net is routed by the maze method and it is determined in step S28 that all nets have been routed (step S31), it is determined whether all nets have been routed. When the wiring process is completed, the wiring process is terminated. If all the nets have not been routed, the process returns to step S27 to perform the next net routing process (step S30).

Next, the maze method in step S27 will be described with reference to FIGS.
First, a via drawn from a port instance (corresponding to a chip terminal) is set as a start point. If this via does not exist, the end of the wiring drawn out from the connector port (corresponding to the port drawing wiring) is set as the start point (step S32).

Next, the target point is the end of the remaining port lead wiring that is not the start point (step S33). There may be a plurality of target points.
All grid values are initialized (step S34). Further, the grid value at the start point is set to “0” (step S35), and the current number = 0 is set (step S36).

  The value of the current number + 1 is set to the adjacent grid in the same layer as the acquired grid (step S37), and the value of the current number + via cost is set to the grid that is in contact with the acquired grid across the layer (step S38). . Note that grids that already have values are not overwritten.

  Next, it is determined whether a value has been set for the grid at the target point (step S39). If it is determined in step S39 that a value has been set for the grid at the target location, the backtrace process in the maze method described above is performed so that the distance from the target location to the start location is reduced. (Step S40). Note that backtrace processing is performed so that the number of bends in the path is reduced. The route acquired in step S40 is set as the wiring route of the net (step S41).

  Next, it is determined whether another target point exists (step S42). If it is determined in step S42 that another target point exists, the next target point is acquired (step S43). Next, all grids of the wiring route previously wired are set as start points (step S44), and the process returns to step S34.

If it is determined in step S39 that no value is set for the grid at the target location, it is further determined whether a value could not be set for any grid (step S45).
If it is determined in step S45 that no value can be set for any grid, the current current number is set to +1 (step S46), and the process returns to step S37.

  If no value can be set for any grid in step S45, “Error: Net xxx cannot be wired” is displayed (step S47), and it is determined whether wiring to all targets has been completed normally. (Step S48).

In step S48, when the wiring to all the targets is not completed normally, the maze method is terminated. Further, when the wiring to all the targets is completed normally, the obtained wiring path is made into a line figure (step S49). In addition, when there is a wiring route straddling a plurality of substrate layers, a via cell is arranged at a straddling location. Further, when there is a wiring that contacts the port lead wiring in the same layer, a process of merging the port lead wiring and the wiring touching is performed. Further, regarding the grid of the wiring path, the surrounding n grid is set as a wiring prohibited area (step S50), and the maze method is terminated.
If it is determined in step S42 that no other target point exists, the process proceeds to step S48.

  As described above, in the wiring method and the wiring support apparatus according to the first embodiment of the present invention, a substantially automatic wiring process is performed on a single circuit board in which a plurality of low-temperature fired multilayer ceramic substrates are connected to each other. The line search method for the entire circuit board is used to determine the connector through which the net wiring connecting adjacent low-temperature fired multilayer ceramic boards passes, and after assigning the nets, each low-temperature fired multilayer ceramic board is subjected to detailed automatic wiring processing. By performing detailed wiring processing in each low-temperature fired multilayer ceramic substrate by a maze method, a plurality of chips in a circuit board are considered while considering restrictions due to connectors connecting adjacent low-temperature fired multilayer ceramic substrates It is possible to efficiently and automatically perform the wiring of the nets connecting between them so as to be the shortest length with the optimal wiring route.

It is a figure which shows an example of the circuit board to which the wiring method in 1st Embodiment for implementing this invention is applied, (a) is a top view, (b) is the arrow of the circuit board shown to Fig.1 (a) It is sectional drawing of a view AA. It is a figure which shows an example of the low-temperature baking multilayer ceramic substrate which is a structural member of the circuit board shown in FIG. 1, (a) is a top view, (b) is an arrow view of the low-temperature baking multilayer ceramic substrate shown in FIG. It is sectional drawing of a BB line. It is a figure which shows an example which connected the several low-temperature baking multilayer ceramic substrate in three dimensions, (a) is a fragmentary sectional perspective view, (b) is a perspective view which shows another example. It is a figure which shows the structure of the wiring assistance apparatus in 1st Embodiment for implementing this invention. It is explanatory drawing which showed an example of the wiring conditions stored in the wiring condition memory | storage means among the wiring assistance apparatuses shown in FIG. It is explanatory drawing which showed the other example of the wiring conditions stored in the wiring condition memory | storage means among the wiring assistance apparatuses shown in FIG. It is explanatory drawing which showed the further another example of the wiring conditions stored in the wiring condition memory | storage means among the wiring assistance apparatuses shown in FIG. 5A and 5B are explanatory diagrams for explaining a terminal shape correction process performed by a terminal shape correcting unit in the wiring support apparatus shown in FIG. 4, wherein FIG. 5A is an explanatory diagram for explaining before the correction process, and FIG. It is explanatory drawing for demonstrating the back. FIG. 5 is an explanatory diagram for explaining staggered wiring processing by via lead wiring means in the wiring support apparatus shown in FIG. 4. FIG. 5 is an explanatory diagram for explaining a lead wiring process from a port by a port lead wiring means in the wiring support apparatus shown in FIG. 4. It is explanatory drawing for demonstrating the line search method used for a rough automatic wiring process means among the wiring assistance apparatuses shown in FIG. It is explanatory drawing for demonstrating the maze method used for a detailed automatic wiring process means among the wiring assistance apparatuses shown in FIG. It is explanatory drawing for demonstrating the continuation of the maze method shown in FIG. It is explanatory drawing for demonstrating the continuation of the maze method shown in FIG. It is explanatory drawing for demonstrating the continuation of the maze method shown in FIG. FIG. 5 is an explanatory diagram for explaining dropping of power supply and ground wiring by detailed automatic wiring processing means in the wiring support apparatus shown in FIG. 4. FIG. 5 is an explanatory diagram for explaining wiring processing of power supply and ground wiring by detailed automatic wiring processing means in the wiring support apparatus shown in FIG. 4. 5A and 5B are explanatory diagrams for explaining the merging of the wiring in the vicinity of the port lead wiring by the wiring merging means in the wiring support apparatus shown in FIG. 4, (a) is an explanatory diagram for explaining before merging, and (b) is the merging. It is explanatory drawing for demonstrating the back. It is a flowchart which shows the whole flow of the wiring method in 1st Embodiment for implementing this invention. FIG. 20 is a flowchart showing an overall flow of a schematic automatic wiring process in the entire flow of the wiring method shown in FIG. 19. FIG. FIG. 21 is a flowchart showing a continuation of the flowchart shown in FIG. 20. FIG. It is a flowchart which shows the flow of a detailed automatic wiring process among the whole flows of the wiring method shown in FIG. It is a flowchart which shows the flow of a maze method among the whole flows of the detailed automatic wiring process shown in FIG. 24 is a flowchart showing a continuation of the flowchart shown in FIG. It is a flowchart which shows the continuation of the flowchart shown in FIG.

Explanation of symbols

1 Low temperature fired multilayer ceramic substrate
1a First low-temperature fired multilayer ceramic substrate
1b Second low-temperature fired multilayer ceramic substrate
1c Third low-temperature fired multilayer ceramic substrate
1d Fourth low-temperature fired multilayer ceramic substrate
2 chips
2a terminal
2b terminal group
3 Connector
3a Male connector
3b Female connector
3c port
3d port lead wiring
4 Via drop area
4a Edge
5 Beer
6 Via prohibited area
6a Edge 7, 7a, 7b Wiring
7c Wiring figure
8 line segments
8a First line segment
8b Second line segment
8c 3rd line segment
9 Wiring prohibited area
10 Wiring support device
11 Layout information storage means
12 Wiring condition storage means
13 Terminal shape correction means
14 Via lead wiring means
15 Port lead wiring means
16 Parameter setting means
17 Display device
18 Input device
19 Outline automatic wiring processing means
20 Detailed automatic wiring processing means
21 Wiring merge means
22 Output means 30a, 30b Predetermined substrate layer 100 Circuit board 200 Wiring design CAD device

Claims (6)

A plurality of low-temperature fired multilayer ceramic substrates are interconnected via a connector to form a single circuit board, and wiring between chips mounted on the plurality of low-temperature fired multilayer ceramic substrates in the single circuit board A circuit board wiring method executed by a circuit board wiring support apparatus ,
The rough automatic wiring processing means provided in the wiring support device uses any terminal in the net to be wired as a start point, a terminal corresponding to the start point as a target point, and from the start point to all the target points by a line search method. A first step of assigning the net to the connector by generating a line segment until it reaches
The detailed automatic wiring processing means provided in the wiring support device refers to the net, and corresponds to the start point of each terminal of the chip or each port of the connector in each low-temperature fired multilayer ceramic substrate. A second terminal is used as a wiring path of the net by setting a grid value from the start point to the target point by a maze method and performing a backtrace process by using a chip terminal or a connector port as a target point. Steps,
Circuit board how to wire characterized in that it comprises a. The circuit board wiring method according to claim 1 ,
The terminal shape correcting means provided in the wiring support device has a step of defining all terminals on one side of the chip as a terminal group before the first step,
The rough automatic wiring processing means in the first step uses a terminal corresponding to the start point as an arbitrary terminal in the net to be wired, and a terminal corresponding to the start point as a target point, and from a terminal group including the start point by a line search method. A circuit board wiring method , wherein a line segment is generated until reaching all of the terminal groups including the target point, and the net is assigned to the connector by performing a backtrace process . In the circuit board wiring method according to claim 1 or 2,
A step of drawing out wiring from each terminal of the chip to each via at an edge of a via dropping area; and a port leading wiring means provided in the wiring support device from each port of the connector. Drawing the wiring to the edge of the via-forbidden region, between the first step and the second step,
Each terminal of the chip in the second step is each via in the edge of the via dropping area, each port of the connector in the second step is an end of each port lead wiring in the edge of the via prohibited area, A circuit board wiring method characterized by corresponding to each . In the wiring method according to claim 3 ,
The circuit board wiring method according to claim 1, wherein the terminal of the chip is dropped to a layer in which the port lead wiring is formed through the via and is connected to an end portion of the port lead wiring by the wiring on the layer . In the wiring method according to claim 2 or 3 ,
The power supply or ground terminal of the chip is dropped to a predetermined layer through the via, and is connected to the end of the port lead wiring through the via via the wiring on the predetermined layer. Circuit board wiring method.   A plurality of low-temperature fired multilayer ceramic substrates are interconnected via a connector to form a single circuit board, and wiring between chips mounted on the plurality of low-temperature fired multilayer ceramic substrates in the single circuit board A circuit board wiring support device,
  Terminal shape correcting means for defining all terminals on one side of the chip as a terminal group;
  Arbitrary terminals on the net to be wired are set as start points, terminals corresponding to the start points are set as target points, and line segments are used to search for line segments from the terminal group including the start point to all the terminal groups including the target point. Generating an automatic trace processing unit that assigns the net to the connector by performing backtrace processing;
  Via lead wiring means for drawing wiring from each terminal of the chip to each via at the edge of the via drop region;
  Port lead-out wiring means for drawing wiring from each port of the connector to the edge of the via-prohibited area;
  Referring to the net, one end of a plurality of vias or port lead wires in each low-temperature fired multilayer ceramic substrate is a start point, and the end of the via or port lead wire corresponding to the start point is a target point. And, by setting the grid value from the start point to the target point by the maze method, by performing the back trace process, detailed automatic wiring processing means as the wiring path of the net,
A circuit board wiring support apparatus comprising:

Images