CN113434346B - Automatic detection method and system for differential signal polarity connection - Google Patents
Automatic detection method and system for differential signal polarity connection Download PDFInfo
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Abstract
The invention discloses an automatic detection method and system for differential signal polarity connection, comprising the steps of automatically compiling schematic diagram engineering and obtaining engineering data; and removing devices and principle drawings which do not need to be detected, analyzing and judging the differential polarity of the differential pins of the devices and the connected network names by screening all the principle drawings and device position numbers which need to be detected, so as to judge whether the differential signal connection of the principle drawings is wrong or not, and generating an alarm report after all the detection is finished. According to the invention, the schematic diagram engineering data is automatically checked for the correctness of the polarity connection of the differential signals in a schematic diagram engineering generation mode, and a report is generated so as to be confirmed by a hardware engineer, so that the checking workload is greatly reduced, the defect of manual omission or error detection is avoided, the product research and development time is shortened, and the research and development efficiency is improved.
Description
Technical Field
The invention relates to the field of integrated chips, in particular to an automatic detection method and system for differential signal polarity connection.
Background
With the trend of electronic systems and integrated chips toward high speed and high density, most of communication modes inside the chip, between chips, and between devices have been converted from a conventional parallel bus to a serial bus. Currently, in addition to high-speed serial buses (such as SGMII, QSGMII, XAUI, SRIO, PCIE, SATA, etc.), some low-speed serial signals (such as RS422, RS485, CAN) adopt differential signals to perform data transmission in order to improve the reliability and transmission distance of data transmission.
In high-speed and high-density digital products (such as switches, routers and some embedded data processing devices), because of a large amount of high-speed data interaction, there may be hundreds and thousands of pairs of differential signals in principle, and once the situation of error connection of the polarities of the differential signals occurs in the schematic diagram design, the board can be changed, so that the research and development cost is increased, the research and development period of the product is increased, and the market window period of the product is possibly missed. Therefore, it is important to ensure the connection accuracy of serial bus differential signals between chips and between devices. Because the existing mainstream schematic diagram design software (such as the aluminum design, cadence, pads, etc.) cannot directly detect the polarity connection relationship of the differential signals, in order to ensure the connection correctness of the differential signals, a hardware engineer must manually check the polarity of each group of differential signals after the schematic diagram design is completed, and then confirm by other project members in the same group in a manual check mode.
With the continuous increase of the data exchange capacity, the differential signals in the schematic diagrams of various products are more and more, if the existing manual inspection method is still adopted, not only is larger workload and more manpower resources needed, but also the defects of low efficiency, manual omission or error detection and the like are caused.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, solve the problem that in a high-speed and high-density digital product which involves a large number of differential signals between chips and between devices for data transmission, automatically realize the check of the polarity connection correctness of the differential signals in a schematic diagram script mode, and provide an automatic detection method and an automatic detection system for the polarity connection of the differential signals.
The aim of the invention is realized by the following technical scheme:
an automatic detection method for differential signal polarity connection comprises the following steps:
step 1: automatically compiling the whole schematic engineering design file through a script program;
step 2: acquiring basic data of schematic engineering, and caching each data by adopting a linked list storage structure;
step 3: calculating a drawing name set S of a principle to be detected and a device position number set Z to be detected by adopting a method of collecting a remainder set;
step 4: starting traversing schematic drawing in the set S;
step 5: traversing the device position number in the current principle drawing;
step 6: acquiring a network name connected with each pin of the current device;
step 7: judging whether the acquired network name is a differential signal according to the requirements of the naming standards of the schematic diagram network labels, if so, entering the step 8, and if not, entering the step 1;
step 8: judging whether the current device is a resistor, a capacitor or an inductor according to the naming rule of the device bit number of the schematic diagram, if not, acquiring the name of the pin of the current device, and then entering the step 9; if yes, obtaining a network name connected with a pin at the other end of the resistor or the capacitor;
step 9: comparing the device pin name with the acquired network name according to the requirements of the pin naming specification of the device of the principle drawing integrated circuit, judging whether the differential polarity of the pin name is consistent with the differential polarity of the network name, if not, adopting a linked list storage structure, adding the current device bit number and the network name connected with the pin into an alarm linked list structure, and if so, entering a step l0;
step 10: judging whether the pins of the current device are all traversed, if so, entering a step 11, and if not, entering a step 6;
step 11: judging whether all devices in the current principle drawing have been traversed, if so, entering a step 12, and if not, entering a step 5;
step 12: judging whether all principle drawings have been traversed in the schematic diagram engineering, if so, generating an alarm report of the polarity connection correctness of the whole schematic diagram engineering with respect to the differential network, and if not, entering step 4.
Further, the schematic engineering basic data in the step 2 includes schematic engineering names, schematic engineering paths, schematic drawing names, device position numbers, network names in the schematic and device pin names.
Further, the step 8 further includes comparing the two network names obtained in the step 8 and the step 6, judging whether the differential polarities of the two ends of the resistor or the capacitor are consistent, if not, adding the current device bit number and the network name connected with the pin into an alarm linked list structure, and then entering the step 11; otherwise, directly go to step 11.
Further, the step 3 includes the following substeps:
step 301: assuming that all principle drawing names and device position numbers of the extracted part of the principle drawing parameters are respectively set A and set X;
step 302: selecting a principle drawing name set B which does not need to be detected and a device position number set Y which does not need to be detected;
step 303: the calculation is carried out by a method of collecting the remainder set, and the formula is as follows:
S=C A b, B may be
Z=C X Y, Y may be
Wherein, represent empty set, S represents the drawing name set of the principle to be detected, Z represents the device number set to be detected.
The automatic detection system for the differential signal polarity connection comprises a schematic diagram parameter extraction module, a visual window data selection module, a data set operation and signal comparison module and an alarm report generation module, wherein the data set operation and signal comparison module is respectively connected with the schematic diagram parameter extraction module, the visual window data selection module and the alarm report generation module; the schematic diagram parameter extraction module automatically compiles schematic diagram engineering file design, the data set operation and signal comparison module analyzes and judges the differential polarity of the differential pins of the device and the connected network name according to the schematic diagram engineering file data and the configuration data of the visual window data selection module, so that whether the schematic diagram differential signal connection is wrong or not is judged, and finally an alarm report is generated in the alarm report generation module.
Further, the schematic diagram parameter extraction module is used for obtaining schematic diagram engineering names, schematic diagram engineering paths, schematic drawing names, device position numbers, network names in the schematic diagrams and device pin names.
Further, the visual window data selection module is used for selecting devices and principle drawings which do not need to be added into the detection range.
Furthermore, the data set operation and signal comparison module adopts the technology of the set remainder to screen the principle drawing and the device position number to be detected, analyzes and judges the differential polarity of the device differential pin and the connected network name, thereby judging whether the differential signal connection of the principle drawing is wrong.
Furthermore, the alarm report generating module is used for generating documents of all principle drawing differential signal polarity connection errors in the whole principle drawing engineering.
The invention has the beneficial effects that: the invention mainly solves the problems that in high-speed and high-density digital products which relate to data transmission by using a large amount of differential signals between chips and between devices, the checking of the polarity connection correctness of the differential signals is automatically realized by adopting a schematic diagram script mode, so that the defects of huge workload, human resource waste, low efficiency, manual omission or error detection and the like of the traditional manual detection method are avoided.
Drawings
Fig. 1 is a flow chart of the method of the present invention.
Fig. 2 is a system architecture diagram of the present invention.
Detailed Description
For a clearer understanding of technical features, objects, and effects of the present invention, a specific embodiment of the present invention will be described with reference to the accompanying drawings.
In this embodiment, as shown in fig. 1, an automatic detection method for differential signal polarity connection includes the following steps:
step 1: automatically compiling the whole schematic engineering design file through a script program;
step 2: acquiring basic data of schematic engineering, and caching each data by adopting a linked list storage structure;
step 3: calculating a drawing name set S of a principle to be detected and a device position number set Z to be detected by adopting a method of collecting a remainder set;
step 4: starting traversing schematic drawing in the set S;
step 5: traversing the device position number in the current principle drawing;
step 6: acquiring a network name connected with each pin of the current device;
step 7: judging whether the acquired network name is a differential signal according to the requirements of the naming standards of the schematic diagram network labels, if so, entering the step 8, and if not, entering the step 1;
step 8: judging whether the current device is a resistor, a capacitor or an inductor according to the naming rule of the device bit number of the schematic diagram, if not, acquiring the name of the pin of the current device, and then entering the step 9; if yes, obtaining a network name connected with a pin at the other end of the resistor or the capacitor;
step 9: comparing the device pin name with the acquired network name according to the requirements of the pin naming specification of the device of the principle drawing integrated circuit, judging whether the differential polarity of the pin name is consistent with the differential polarity of the network name, if not, adopting a linked list storage structure, adding the current device bit number and the network name connected with the pin into an alarm linked list structure, and if so, entering a step l0;
step 10: judging whether the pins of the current device are all traversed, if so, entering a step 11, and if not, entering a step 6;
step 11: judging whether all devices in the current principle drawing have been traversed, if so, entering a step 12, and if not, entering a step 5;
step 12: judging whether all principle drawings have been traversed in the schematic diagram engineering, if so, generating an alarm report of the polarity connection correctness of the whole schematic diagram engineering with respect to the differential network, and if not, entering step 4.
Further, the schematic engineering basic data in the step 2 includes schematic engineering names, schematic engineering paths, schematic drawing names, device position numbers, network names in the schematic and device pin names.
Further, the step 8 further includes comparing the two network names obtained in the step 8 and the step 6, judging whether the differential polarities of the two ends of the resistor or the capacitor are consistent, if not, adding the current device bit number and the network name connected with the pin into an alarm linked list structure, and then entering the step 11; otherwise, directly go to step 11.
Further, the step 3 includes the following substeps:
step 301: assuming that all principle drawing names and device position numbers of the extracted part of the principle drawing parameters are respectively set A and set X;
step 302: selecting a principle drawing name set B which does not need to be detected and a device position number set Y which does not need to be detected;
step 303: the calculation is carried out by a method of collecting the remainder set, and the formula is as follows:
S=C A b, B may be
Z=C X Y, Y may be
Wherein, represent empty set, S represents the drawing name set of the principle to be detected, Z represents the device number set to be detected.
As shown in fig. 2, the automatic detection system for the differential signal polarity connection comprises a schematic diagram parameter extraction module, a visual window data selection module, a data set operation and signal comparison module and an alarm report generation module, wherein the data set operation and signal comparison module is respectively connected with the schematic diagram parameter extraction module, the visual window data selection module and the alarm report generation module; the schematic diagram parameter extraction module automatically compiles schematic diagram engineering file design, the data set operation and signal comparison module analyzes and judges the differential polarity of the differential pins of the device and the connected network name according to the schematic diagram engineering file data and the configuration data of the visual window data selection module, so that whether the schematic diagram differential signal connection is wrong or not is judged, and finally an alarm report is generated in the alarm report generation module.
Further, the schematic diagram parameter extraction module is used for obtaining schematic diagram engineering names, schematic diagram engineering paths, schematic drawing names, device position numbers, network names in the schematic diagrams and device pin names.
Further, the visual window data selection module is used for selecting devices and principle drawings which do not need to be added into the detection range.
Furthermore, the data set operation and signal comparison module adopts the technology of the set remainder to realize screening of principle drawings and device position numbers to be detected.
Furthermore, the alarm report generating module is used for generating documents of all principle drawing differential signal polarity connection errors in the whole principle drawing engineering.
Example 1: the implementation case of the automatic detection method for the polarity connection correctness of the differential signal is as follows:
taking an AltiumDesigner schematic design platform as an example, the process of checking the correctness of the differential signal polarity connection of a service data exchange card in a certain exchange device based on DelphiScript script language is as follows:
1. calling a GetWorkspace.DM_FocusedProject to locate the current schematic diagram engineering working space, and calling a project.DM_Compilefunction to automatically Compile the schematic diagram engineering;
2. filling device bit numbers which do not need to be checked in a visual window: XS1 (if there are multiple digits, the digits are separated by commas, where XS1 is a connector that connects a board card and a backplane, and because the pin names of the connector are not named according to differential signals, detection is not needed, otherwise, a large amount of alarm information is generated), and the principle drawing that is not needed to be checked is filled in: (if a plurality of principle drawings exist, the drawings are separated by commas, and no differential signal exists in the 06_MISC drawing, so that detection is not needed, and the operation efficiency of the detection method is improved);
3. obtaining the whole schematic diagram information, including:
schematic engineering name: LPU_SWITCH. PrjPcb
Schematic engineering path: f \TB2005\AltiumDesigner_Prj\00_LPU_SWITCH
All principle drawing names set: a is that
All device bit number sets: x is X
4. Acquiring a drawing name set S of a principle to be detected, namely a remainder set of a set B (element: 06_MISC) in the set A;
5. acquiring a bit number set Z of a device to be detected, namely a remainder set of a set Y (element: XS 1) in the set X;
6. traversing to a principle drawing 01_SWITCH in the set S;
7. the first device bit number in the 01_SWITCH principle drawing is obtained: d1;
8. judging that D1 is an element of the set Z, so that the device needs to be checked;
9. obtain the first pin of D1: d1.a1;
10. the network name to which d1 a1 is connected is obtained: SGMII_TX_P0 judges that the network name is a differential signal and the polarity is positive according to a principle diagram network label naming rule (the network name is finally "_P" or "_P+digital", then the network name is finally "_N" or "_N+digital", then the network name is the negative electrode of the differential signal);
11. judging that the current device D1 is an integrated circuit component and is not a resistor, a capacitor or an inductor according to the naming rule of the device bit number;
12. obtain d1.a1 pin name: SGMII_TX_N0, according to the schematic diagram device pin naming specification (the pin name is finally "_P" or "_P+digital", then the pin name is the positive pole of the differential signal, the pin name is finally "_N" or "_N+digital", then the negative pole of the differential signal), judging that the differential polarity of the pin is negative, and contradicting the differential signal polarity obtained in the step 10 as positive, so that the device bit number D1 and the network name SGMII_TX_P0 are added into an alarm linked list structure warning. List;
13. repeating the steps 9-12, and traversing all the remaining pins of the D1;
14. repeating the steps 7-13, and traversing all the remaining device position numbers under the 01_SWITCH principle drawing;
15. repeating the steps 6-14, and traversing all principle drawings in the set S;
under the F\TB 2005\AltuDesigner_Prj\00_LPU_SWITCH path, an alarm report LPU_SWITCH.schpck is created according to the selected file type, data in an alarm linked list structure Warning.List is written into the report, and after the data writing is completed, the report is automatically opened in AltuDesigner software.
According to the invention, the schematic diagram engineering data is automatically checked for the correctness of the polarity connection of the differential signals in a schematic diagram engineering generation mode, and a report is generated so as to be confirmed by a hardware engineer, so that the checking workload is greatly reduced, the defect of manual omission or error detection is avoided, the product research and development time is shortened, and the research and development efficiency is improved.
The foregoing has shown and described the basic principles and main features of the present invention and the advantages of the present invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made without departing from the spirit and scope of the invention, which is defined in the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (8)
1. An automatic detection method for differential signal polarity connection is characterized by comprising the following steps:
step 1: automatically compiling the whole schematic engineering design file through a script program;
step 2: acquiring basic data of schematic engineering, and caching each data by adopting a linked list storage structure;
step 3: calculating a drawing name set S of a principle to be detected and a device position number set Z to be detected by adopting a method of collecting a remainder set;
step 4: starting traversing schematic drawing in the set S;
step 5: traversing the device position number in the current principle drawing;
step 6: acquiring a network name connected with each pin of the current device;
step 7: judging whether the acquired network name is a differential signal according to the requirements of the naming standards of the schematic diagram network labels, if so, entering the step 8, and if not, entering the step 1;
step 8: judging whether the current device is a resistor, a capacitor or an inductor according to the naming rule of the device bit number of the schematic diagram, if not, acquiring the name of the pin of the current device, and then entering the step 9; if yes, obtaining a network name connected with pins at the other end of the resistor, the capacitor or the inductor; the step 8 further includes comparing the two network names obtained in the step 8 and the step 6, judging whether the differential polarities at the two ends of the resistor or the capacitor are consistent, if not, adding the current device bit number and the network name connected with the pin into an alarm linked list structure, and then entering the step 11; otherwise, directly entering step 11;
step 9: comparing the device pin name with the acquired network name according to the requirements of the pin naming specification of the device of the principle drawing integrated circuit, judging whether the differential polarity of the pin name is consistent with the differential polarity of the network name, if not, adopting a linked list storage structure, adding the current device bit number and the network name connected with the pin into an alarm linked list structure, and if so, entering a step l0;
step 10: judging whether the pins of the current device are all traversed, if so, entering a step 11, and if not, entering a step 6;
step 11: judging whether all devices in the current principle drawing have been traversed, if so, entering a step 12, and if not, entering a step 5;
step 12: judging whether all principle drawings have been traversed in the schematic diagram engineering, if so, generating an alarm report of the polarity connection correctness of the whole schematic diagram engineering with respect to the differential network, and if not, entering step 4.
2. The automatic detection method for differential signal polarity connection according to claim 1, wherein the schematic engineering basic data in the step 2 includes schematic engineering names, schematic engineering paths, schematic drawing names, device bit numbers, network names in the schematic and device pin names.
3. The automatic detection method of differential signal polarity connection according to claim 1, wherein said step 3 comprises the sub-steps of:
step 301: assuming that all principle drawing names and device position numbers of the extracted part of the principle drawing parameters are respectively set A and set X;
step 302: selecting a principle drawing name set B which does not need to be detected and a device position number set Y which does not need to be detected;
step 303: the calculation is carried out by a method of collecting the remainder set, and the formula is as follows:
S=C A b, B may be
Z=C X Y, Y may be
Wherein, represent empty set, S represents the drawing name set of the principle to be detected, Z represents the device number set to be detected.
4. An automatic detection system for differential signal polarity connection, which is used for realizing the automatic detection method for differential signal polarity connection according to any one of claims 1-3, and is characterized by comprising a schematic diagram parameter extraction module, a visual window data selection module, a data set operation and signal comparison module and an alarm report generation module, wherein the data set operation and signal comparison module is respectively connected with the schematic diagram parameter extraction module, the visual window data selection module and the alarm report generation module; the schematic diagram parameter extraction module automatically compiles schematic diagram engineering file design, the data set operation and signal comparison module analyzes and judges the differential polarity of the differential pins of the device and the connected network name according to the schematic diagram engineering file data and the configuration data of the visual window data selection module, so that whether the schematic diagram differential signal connection is wrong or not is judged, and finally an alarm report is generated in the alarm report generation module.
5. The system of claim 4, wherein the schematic parameter extraction module is configured to obtain a schematic engineering name, a schematic engineering path, a schematic drawing name, a device bit number, a network name in a schematic, and a device pin name.
6. The system of claim 4, wherein the visual window data selection module is configured to select devices and principle drawings that do not need to be added to the detection range.
7. The automatic detection system for differential signal polarity connection according to claim 4, wherein the data set operation and signal comparison module uses a set redundancy technique to screen the principle drawing and the device bit number to be detected, and analyzes and judges the differential polarity of the differential pins of the device and the connected network name, so as to judge whether the differential signal connection of the schematic diagram is wrong.
8. The system of claim 4, wherein the alarm report generating module is configured to generate a document of all schematic drawing differential signal polarity connection errors in the whole schematic engineering.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102156789A (en) * | 2011-04-27 | 2011-08-17 | 迈普通信技术股份有限公司 | System and method for automatically generating constraint file of field programmable gate array (FPGA) |
| US8161429B1 (en) * | 2004-08-20 | 2012-04-17 | Altera Corporation | Methods and apparatus for initializing serial links |
| CN202916447U (en) * | 2012-10-29 | 2013-05-01 | 成都理工大学 | MRPC detector front-end electronics module |
| CN105181597A (en) * | 2015-08-04 | 2015-12-23 | 宁波摩米创新工场电子科技有限公司 | High speed difference based digital photoelectric detection system |
| CN105701317A (en) * | 2016-03-01 | 2016-06-22 | 上海斐讯数据通信技术有限公司 | Method and system for correcting signal missing in schematic diagram designing |
| CN107491369A (en) * | 2017-08-18 | 2017-12-19 | 郑州云海信息技术有限公司 | A kind of detection method and system of quick PCIE3.0 signal integrities |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003103244A1 (en) * | 2002-05-31 | 2003-12-11 | 松下電器産業株式会社 | Data transmission system |
-
2021
- 2021-05-26 CN CN202110578568.1A patent/CN113434346B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8161429B1 (en) * | 2004-08-20 | 2012-04-17 | Altera Corporation | Methods and apparatus for initializing serial links |
| CN102156789A (en) * | 2011-04-27 | 2011-08-17 | 迈普通信技术股份有限公司 | System and method for automatically generating constraint file of field programmable gate array (FPGA) |
| CN202916447U (en) * | 2012-10-29 | 2013-05-01 | 成都理工大学 | MRPC detector front-end electronics module |
| CN105181597A (en) * | 2015-08-04 | 2015-12-23 | 宁波摩米创新工场电子科技有限公司 | High speed difference based digital photoelectric detection system |
| CN105701317A (en) * | 2016-03-01 | 2016-06-22 | 上海斐讯数据通信技术有限公司 | Method and system for correcting signal missing in schematic diagram designing |
| CN107491369A (en) * | 2017-08-18 | 2017-12-19 | 郑州云海信息技术有限公司 | A kind of detection method and system of quick PCIE3.0 signal integrities |
Non-Patent Citations (1)
| Title |
|---|
| 板级设计中硬件连接部分的验证方法探讨;蒋媛君 等;《计算机工程应用技术》;第4卷(第6期);第1496-1510页 * |
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